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Improve dagcombining for sext-loads and sext-in-reg nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54239 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3060,8 +3060,12 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
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LN0->isVolatile(),
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LN0->getAlignment());
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CombineTo(N, ExtLoad);
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CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
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ExtLoad.getValue(1));
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// Redirect any chain users to the new load.
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DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), SDValue(ExtLoad.Val, 1));
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// If any node needs the original loaded value, recompute it.
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if (!LN0->use_empty())
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CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
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ExtLoad.getValue(1));
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return SDValue(N, 0); // Return N so it doesn't get rechecked!
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}
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@ -3169,17 +3173,16 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
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// Do not generate loads of non-round integer types since these can
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// be expensive (and would be wrong if the type is not byte sized).
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if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && VT.isRound() &&
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if (isa<LoadSDNode>(N0) && N0.hasOneUse() && VT.isRound() &&
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cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits &&
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// Do not change the width of a volatile load.
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!cast<LoadSDNode>(N0)->isVolatile()) {
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assert(N0.getValueType().getSizeInBits() > EVTBits &&
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"Cannot truncate to larger type!");
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LoadSDNode *LN0 = cast<LoadSDNode>(N0);
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MVT PtrType = N0.getOperand(1).getValueType();
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// For big endian targets, we need to adjust the offset to the pointer to
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// load the correct bytes.
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if (TLI.isBigEndian()) {
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unsigned LVTStoreBits = N0.getValueType().getStoreSizeInBits();
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unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
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unsigned EVTStoreBits = EVT.getStoreSizeInBits();
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ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
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}
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@ -3190,11 +3193,11 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
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AddToWorkList(NewPtr.Val);
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SDValue Load = (ExtType == ISD::NON_EXTLOAD)
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? DAG.getLoad(VT, LN0->getChain(), NewPtr,
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LN0->getSrcValue(), LN0->getSrcValueOffset(),
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LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
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LN0->isVolatile(), NewAlign)
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: DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr,
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LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
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LN0->isVolatile(), NewAlign);
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LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
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EVT, LN0->isVolatile(), NewAlign);
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AddToWorkList(N);
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if (CombineSRL) {
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WorkListRemover DeadNodes(*this);
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@ -3238,6 +3241,15 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
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return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
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}
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// fold (sext_in_reg (sext x)) -> (sext x)
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// fold (sext_in_reg (aext x)) -> (sext x)
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// if x is small enough.
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if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
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SDValue N00 = N0.getOperand(0);
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if (N00.getValueType().getSizeInBits() < EVTBits)
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return DAG.getNode(ISD::SIGN_EXTEND, VT, N00, N1);
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}
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// fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
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if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
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return DAG.getZeroExtendInReg(N0, EVT);
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9
test/CodeGen/X86/sext-trunc.ll
Normal file
9
test/CodeGen/X86/sext-trunc.ll
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@ -0,0 +1,9 @@
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; RUN: llvm-as < %s | llc -march=x86 > %t
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; RUN: grep movsbl %t
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; RUN: not grep movz %t
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; RUN: not grep and %t
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define i8 @foo(i16 signext %x) signext nounwind {
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%retval56 = trunc i16 %x to i8
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ret i8 %retval56
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}
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