6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-20 10:30:03 +00:00
Code Issues Projects Releases Wiki Activity

R600/SI: add proper 64bit immediate support v2

Browse Source 
v2: rebased on current upstream

Patch by: Christian König

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174652 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2013-02-07 19:39:38 +00:00
parent b0b1a7feee
commit 75ddd4cd4c
3 changed files with 18 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
lib/Target/R600/SIInstrInfo.td
View File

@ -38,6 +38,16 @@ def SIvcc_bitcast : SDNode<"SIISD::VCC_BITCAST",
SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>]>
>;
// Transformation function, extract the lower 32bit of a 64bit immediate
def LO32 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
}]>;
// Transformation function, extract the upper 32bit of a 64bit immediate
def HI32 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
}]>;
class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
AMDGPUInst<outs, ins, asm, pattern> {

19
lib/Target/R600/SIInstructions.td
View File

@ -1019,19 +1019,16 @@ def S_MOV_IMM_I32 : InstSI <
[(set SReg_32:$dst, (imm:$src0))]
>;
// i64 immediates aren't really supported in hardware, but LLVM will use the i64
// type for indices on load and store instructions. The pattern for
// S_MOV_IMM_I64 will only match i64 immediates that can fit into 32-bits,
// which the hardware can handle.
def S_MOV_IMM_I64 : InstSI <
(outs SReg_64:$dst),
(ins i64imm:$src0),
"S_MOV_IMM_I64 $dst, $src0",
[(set SReg_64:$dst, (IMM32bitIn64bit:$src0))]
>;
} // End isCodeGenOnly, isPseudo = 1
// i64 immediates aren't supported in hardware, split it into two 32bit values
def : Pat <
(i64 imm:$imm),
(INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(S_MOV_IMM_I32 (LO32 imm:$imm)), sub0),
(S_MOV_IMM_I32 (HI32 imm:$imm)), sub1)
>;
class SI_LOAD_LITERAL<Operand ImmType> :
Enc32 <(outs), (ins ImmType:$imm), "LOAD_LITERAL $imm", []> {

1
lib/Target/R600/SILowerLiteralConstants.cpp
View File

@ -73,7 +73,6 @@ bool SILowerLiteralConstantsPass::runOnMachineFunction(MachineFunction &MF) {
switch (MI.getOpcode()) {
default: break;
case AMDGPU::S_MOV_IMM_I32:
case AMDGPU::S_MOV_IMM_I64:
case AMDGPU::V_MOV_IMM_F32:
case AMDGPU::V_MOV_IMM_I32: {
unsigned MovOpcode;