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R600/SI: add proper 64bit immediate support v2
v2: rebased on current upstream Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174652 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -38,6 +38,16 @@ def SIvcc_bitcast : SDNode<"SIISD::VCC_BITCAST",
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SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>]>
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SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>]>
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>;
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>;
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// Transformation function, extract the lower 32bit of a 64bit immediate
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def LO32 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
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}]>;
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// Transformation function, extract the upper 32bit of a 64bit immediate
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def HI32 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
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}]>;
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class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
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class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
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AMDGPUInst<outs, ins, asm, pattern> {
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AMDGPUInst<outs, ins, asm, pattern> {
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@ -1019,19 +1019,16 @@ def S_MOV_IMM_I32 : InstSI <
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[(set SReg_32:$dst, (imm:$src0))]
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[(set SReg_32:$dst, (imm:$src0))]
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>;
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>;
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// i64 immediates aren't really supported in hardware, but LLVM will use the i64
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// type for indices on load and store instructions. The pattern for
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// S_MOV_IMM_I64 will only match i64 immediates that can fit into 32-bits,
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// which the hardware can handle.
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def S_MOV_IMM_I64 : InstSI <
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(outs SReg_64:$dst),
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(ins i64imm:$src0),
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"S_MOV_IMM_I64 $dst, $src0",
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[(set SReg_64:$dst, (IMM32bitIn64bit:$src0))]
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>;
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} // End isCodeGenOnly, isPseudo = 1
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} // End isCodeGenOnly, isPseudo = 1
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// i64 immediates aren't supported in hardware, split it into two 32bit values
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def : Pat <
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(i64 imm:$imm),
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(INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(S_MOV_IMM_I32 (LO32 imm:$imm)), sub0),
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(S_MOV_IMM_I32 (HI32 imm:$imm)), sub1)
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>;
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class SI_LOAD_LITERAL<Operand ImmType> :
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class SI_LOAD_LITERAL<Operand ImmType> :
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Enc32 <(outs), (ins ImmType:$imm), "LOAD_LITERAL $imm", []> {
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Enc32 <(outs), (ins ImmType:$imm), "LOAD_LITERAL $imm", []> {
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@ -73,7 +73,6 @@ bool SILowerLiteralConstantsPass::runOnMachineFunction(MachineFunction &MF) {
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switch (MI.getOpcode()) {
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switch (MI.getOpcode()) {
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default: break;
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default: break;
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case AMDGPU::S_MOV_IMM_I32:
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case AMDGPU::S_MOV_IMM_I32:
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case AMDGPU::S_MOV_IMM_I64:
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case AMDGPU::V_MOV_IMM_F32:
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case AMDGPU::V_MOV_IMM_F32:
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case AMDGPU::V_MOV_IMM_I32: {
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case AMDGPU::V_MOV_IMM_I32: {
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unsigned MovOpcode;
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unsigned MovOpcode;
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