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remove all but one reference to TargetRegisterDesc::AsmName.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81714 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2009-09-13 20:31:40 +00:00
parent d95148f073
commit 762ccea600
14 changed files with 49 additions and 80 deletions
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6
include/llvm/Target/TargetRegisterInfo.h
View File

@ -368,12 +368,6 @@ public:
return get(RegNo).SuperRegs;
}
/// getAsmName - Return the symbolic target-specific name for the
/// specified physical register.
const char *getAsmName(unsigned RegNo) const {
return get(RegNo).AsmName;
}
/// getName - Return the human-readable symbolic target-specific name for the
/// specified physical register.
const char *getName(unsigned RegNo) const {

60
lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
View File

@ -314,15 +314,15 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
O << '{'
<< TRI->getAsmName(DRegLo) << ',' << TRI->getAsmName(DRegHi)
<< getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
<< '}';
} else if (Modifier && strcmp(Modifier, "lane") == 0) {
unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 0 : 1,
&ARM::DPRRegClass);
O << TRI->getAsmName(DReg) << '[' << (RegNum & 1) << ']';
O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
} else {
O << TRI->getAsmName(Reg);
O << getRegisterName(Reg);
}
} else
llvm_unreachable("not implemented");
@ -428,8 +428,7 @@ void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
const MachineOperand &MO2 = MI->getOperand(Op+1);
const MachineOperand &MO3 = MI->getOperand(Op+2);
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
O << TRI->getAsmName(MO1.getReg());
O << getRegisterName(MO1.getReg());
// Print the shift opc.
O << ", "
@ -437,8 +436,7 @@ void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
<< " ";
if (MO2.getReg()) {
assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
O << TRI->getAsmName(MO2.getReg());
O << getRegisterName(MO2.getReg());
assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
} else {
O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
@ -455,7 +453,7 @@ void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
return;
}
O << "[" << TRI->getAsmName(MO1.getReg());
O << "[" << getRegisterName(MO1.getReg());
if (!MO2.getReg()) {
if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
@ -468,7 +466,7 @@ void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
O << ", "
<< (char)ARM_AM::getAM2Op(MO3.getImm())
<< TRI->getAsmName(MO2.getReg());
<< getRegisterName(MO2.getReg());
if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
O << ", "
@ -491,7 +489,7 @@ void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
}
O << (char)ARM_AM::getAM2Op(MO2.getImm())
<< TRI->getAsmName(MO1.getReg());
<< getRegisterName(MO1.getReg());
if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
O << ", "
@ -505,12 +503,12 @@ void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
const MachineOperand &MO3 = MI->getOperand(Op+2);
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
O << "[" << TRI->getAsmName(MO1.getReg());
O << "[" << getRegisterName(MO1.getReg());
if (MO2.getReg()) {
O << ", "
<< (char)ARM_AM::getAM3Op(MO3.getImm())
<< TRI->getAsmName(MO2.getReg())
<< getRegisterName(MO2.getReg())
<< "]";
return;
}
@ -528,7 +526,7 @@ void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
if (MO1.getReg()) {
O << (char)ARM_AM::getAM3Op(MO2.getImm())
<< TRI->getAsmName(MO1.getReg());
<< getRegisterName(MO1.getReg());
return;
}
@ -588,13 +586,13 @@ void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
return;
} else if (Modifier && strcmp(Modifier, "base") == 0) {
// Used for FSTM{D|S} and LSTM{D|S} operations.
O << TRI->getAsmName(MO1.getReg());
O << getRegisterName(MO1.getReg());
if (ARM_AM::getAM5WBFlag(MO2.getImm()))
O << "!";
return;
}
O << "[" << TRI->getAsmName(MO1.getReg());
O << "[" << getRegisterName(MO1.getReg());
if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
O << ", #"
@ -610,13 +608,13 @@ void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
const MachineOperand &MO3 = MI->getOperand(Op+2);
// FIXME: No support yet for specifying alignment.
O << "[" << TRI->getAsmName(MO1.getReg()) << "]";
O << "[" << getRegisterName(MO1.getReg()) << "]";
if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
if (MO2.getReg() == 0)
O << "!";
else
O << ", " << TRI->getAsmName(MO2.getReg());
O << ", " << getRegisterName(MO2.getReg());
}
}
@ -629,7 +627,7 @@ void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
const MachineOperand &MO1 = MI->getOperand(Op);
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
O << "[pc, +" << TRI->getAsmName(MO1.getReg()) << "]";
O << "[pc, +" << getRegisterName(MO1.getReg()) << "]";
}
void
@ -663,8 +661,8 @@ void
ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
const MachineOperand &MO1 = MI->getOperand(Op);
const MachineOperand &MO2 = MI->getOperand(Op+1);
O << "[" << TRI->getAsmName(MO1.getReg());
O << ", " << TRI->getAsmName(MO2.getReg()) << "]";
O << "[" << getRegisterName(MO1.getReg());
O << ", " << getRegisterName(MO2.getReg()) << "]";
}
void
@ -679,9 +677,9 @@ ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
return;
}
O << "[" << TRI->getAsmName(MO1.getReg());
O << "[" << getRegisterName(MO1.getReg());
if (MO3.getReg())
O << ", " << TRI->getAsmName(MO3.getReg());
O << ", " << getRegisterName(MO3.getReg());
else if (unsigned ImmOffs = MO2.getImm()) {
O << ", #" << ImmOffs;
if (Scale > 1)
@ -706,7 +704,7 @@ ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
const MachineOperand &MO1 = MI->getOperand(Op);
const MachineOperand &MO2 = MI->getOperand(Op+1);
O << "[" << TRI->getAsmName(MO1.getReg());
O << "[" << getRegisterName(MO1.getReg());
if (unsigned ImmOffs = MO2.getImm())
O << ", #" << ImmOffs << " * 4";
O << "]";
@ -724,7 +722,7 @@ void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
unsigned Reg = MO1.getReg();
assert(TargetRegisterInfo::isPhysicalRegister(Reg));
O << TRI->getAsmName(Reg);
O << getRegisterName(Reg);
// Print the shift opc.
O << ", "
@ -740,7 +738,7 @@ void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
const MachineOperand &MO1 = MI->getOperand(OpNum);
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
O << "[" << TRI->getAsmName(MO1.getReg());
O << "[" << getRegisterName(MO1.getReg());
unsigned OffImm = MO2.getImm();
if (OffImm) // Don't print +0.
@ -753,7 +751,7 @@ void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
const MachineOperand &MO1 = MI->getOperand(OpNum);
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
O << "[" << TRI->getAsmName(MO1.getReg());
O << "[" << getRegisterName(MO1.getReg());
int32_t OffImm = (int32_t)MO2.getImm();
// Don't print +0.
@ -769,7 +767,7 @@ void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
const MachineOperand &MO1 = MI->getOperand(OpNum);
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
O << "[" << TRI->getAsmName(MO1.getReg());
O << "[" << getRegisterName(MO1.getReg());
int32_t OffImm = (int32_t)MO2.getImm() / 4;
// Don't print +0.
@ -797,10 +795,10 @@ void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
const MachineOperand &MO3 = MI->getOperand(OpNum+2);
O << "[" << TRI->getAsmName(MO1.getReg());
O << "[" << getRegisterName(MO1.getReg());
assert(MO2.getReg() && "Invalid so_reg load / store address!");
O << ", " << TRI->getAsmName(MO2.getReg());
O << ", " << getRegisterName(MO2.getReg());
unsigned ShAmt = MO3.getImm();
if (ShAmt) {
@ -952,7 +950,7 @@ void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
}
void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
O << "[pc, " << TRI->getAsmName(MI->getOperand(OpNum).getReg());
O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
if (MI->getOpcode() == ARM::t2TBH)
O << ", lsl #1";
O << ']';
@ -972,7 +970,7 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
default: return true; // Unknown modifier.
case 'a': // Print as a memory address.
if (MI->getOperand(OpNum).isReg()) {
O << "[" << TRI->getAsmName(MI->getOperand(OpNum).getReg()) << "]";
O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
return false;
}
// Fallthrough

6
lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
View File

@ -75,7 +75,7 @@ void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum)
if (MO.getType() == MachineOperand::MO_Register) {
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
"Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
O << getRegisterName(MO.getReg());
} else if (MO.isImm()) {
O << MO.getImm();
assert(MO.getImm() < (1 << 30));
@ -86,11 +86,9 @@ void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum)
void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
const TargetRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_Register:
O << RI.get(MO.getReg()).AsmName;
O << getRegisterName(MO.getReg());
return;
case MachineOperand::MO_Immediate:

2
lib/Target/Blackfin/AsmPrinter/BlackfinAsmPrinter.cpp
View File

@ -172,7 +172,7 @@ void BlackfinAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
case MachineOperand::MO_Register:
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
"Virtual registers should be already mapped!");
O << RI.get(MO.getReg()).AsmName;
O << getRegisterName(MO.getReg());
break;
case MachineOperand::MO_Immediate:

8
lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
View File

@ -80,14 +80,13 @@ namespace {
unsigned RegNo = MO.getReg();
assert(TargetRegisterInfo::isPhysicalRegister(RegNo) &&
"Not physreg??");
O << TM.getRegisterInfo()->get(RegNo).AsmName;
O << getRegisterName(RegNo);
}
void printOperand(const MachineInstr *MI, unsigned OpNo) {
const MachineOperand &MO = MI->getOperand(OpNo);
if (MO.isReg()) {
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
O << getRegisterName(MO.getReg());
} else if (MO.isImm()) {
O << MO.getImm();
} else {
@ -154,8 +153,7 @@ namespace {
// the value contained in the register. For this reason, the darwin
// assembler requires that we print r0 as 0 (no r) when used as the base.
const MachineOperand &MO = MI->getOperand(OpNo);
O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
O << ", ";
O << getRegisterName(MO.getReg()) << ", ";
printOperand(MI, OpNo+1);
}

4
lib/Target/MSP430/AsmPrinter/MSP430AsmPrinter.cpp
View File

@ -163,9 +163,7 @@ void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
const MachineOperand &MO = MI->getOperand(OpNum);
switch (MO.getType()) {
case MachineOperand::MO_Register:
assert (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
"Virtual registers should be already mapped!");
O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
O << getRegisterName(MO.getReg());
return;
case MachineOperand::MO_Immediate:
if (!Modifier || strcmp(Modifier, "nohash"))

13
lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
View File

@ -189,9 +189,9 @@ void MipsAsmPrinter::emitFrameDirective(MachineFunction &MF) {
unsigned stackSize = MF.getFrameInfo()->getStackSize();
O << "\t.frame\t" << '$' << LowercaseString(RI.get(stackReg).AsmName)
O << "\t.frame\t" << '$' << LowercaseString(getRegisterName(stackReg))
<< ',' << stackSize << ','
<< '$' << LowercaseString(RI.get(returnReg).AsmName)
<< '$' << LowercaseString(getRegisterName(returnReg))
<< '\n';
}
@ -314,7 +314,6 @@ bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
const MachineOperand &MO = MI->getOperand(opNum);
const TargetRegisterInfo &RI = *TM.getRegisterInfo();
bool closeP = false;
if (MO.getTargetFlags())
@ -337,13 +336,9 @@ void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
break;
}
switch (MO.getType())
{
switch (MO.getType()) {
case MachineOperand::MO_Register:
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
O << '$' << LowercaseString (RI.get(MO.getReg()).AsmName);
else
O << '$' << MO.getReg();
O << '$' << LowercaseString(getRegisterName(MO.getReg()));
break;
case MachineOperand::MO_Immediate:

5
lib/Target/PIC16/AsmPrinter/PIC16AsmPrinter.cpp
View File

@ -131,10 +131,7 @@ void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
switch (MO.getType()) {
case MachineOperand::MO_Register:
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
else
llvm_unreachable("not implemented");
O << getRegisterName(MO.getReg());
return;
case MachineOperand::MO_Immediate:

2
lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
View File

@ -151,7 +151,7 @@ namespace {
return;
}
const char *RegName = TM.getRegisterInfo()->get(RegNo).AsmName;
const char *RegName = getRegisterName(RegNo);
// Linux assembler (Others?) does not take register mnemonics.
// FIXME - What about special registers used in mfspr/mtspr?
if (!Subtarget.isDarwin()) RegName = stripRegisterPrefix(RegName);

5
lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
View File

@ -162,10 +162,7 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
}
switch (MO.getType()) {
case MachineOperand::MO_Register:
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
O << "%" << LowercaseString (RI.get(MO.getReg()).AsmName);
else
O << "%reg" << MO.getReg();
O << "%" << LowercaseString(getRegisterName(MO.getReg()));
break;
case MachineOperand::MO_Immediate:

2
lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp
View File

@ -223,7 +223,7 @@ void SystemZAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
assert(0 && "Invalid subreg modifier");
}
O << '%' << TRI->getAsmName(Reg);
O << '%' << getRegisterName(Reg);
return;
}
case MachineOperand::MO_Immediate:

6
lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
View File

@ -441,8 +441,6 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
switch (MO.getType()) {
default: llvm_unreachable("unknown operand type!");
case MachineOperand::MO_Register: {
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
"Virtual registers should not make it this far!");
O << '%';
unsigned Reg = MO.getReg();
if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
@ -451,7 +449,7 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
Reg = getX86SubSuperRegister(Reg, VT);
}
O << TRI->getAsmName(Reg);
O << X86ATTInstPrinter::getRegisterName(Reg);
return;
}
@ -611,7 +609,7 @@ bool X86ATTAsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode) {
break;
}
O << '%'<< TRI->getAsmName(Reg);
O << '%' << X86ATTInstPrinter::getRegisterName(Reg);
return false;
}

1
lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
View File

@ -223,7 +223,6 @@ void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
const char *Modifier) {
switch (MO.getType()) {
case MachineOperand::MO_Register: {
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()));
unsigned Reg = MO.getReg();
if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
EVT VT = (strcmp(Modifier,"subreg64") == 0) ?

9
lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp
View File

@ -315,7 +315,7 @@ void XCoreAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
const MachineOperand &MO = MI->getOperand(opNum);
switch (MO.getType()) {
case MachineOperand::MO_Register:
O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
O << getRegisterName(MO.getReg());
break;
case MachineOperand::MO_Immediate:
O << MO.getImm();
@ -359,11 +359,8 @@ void XCoreAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
// Check for mov mnemonic
unsigned src, dst, srcSR, dstSR;
if (TM.getInstrInfo()->isMoveInstr(*MI, src, dst, srcSR, dstSR)) {
O << "\tmov ";
O << TM.getRegisterInfo()->get(dst).AsmName;
O << ", ";
O << TM.getRegisterInfo()->get(src).AsmName;
O << "\n";
O << "\tmov " << getRegisterName(dst) << ", ";
O << getRegisterName(src) << '\n';
return;
}
printInstruction(MI);