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Revise ARM inline assembly memory operands to require the memory address to

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be in a register.  The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb.  Radar 7137468.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84022 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2009-10-13 20:50:28 +00:00
parent 4360298d2b
commit 765cc0b9d5
3 changed files with 11 additions and 10 deletions
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12
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@ -2156,14 +2156,10 @@ bool ARMDAGToDAGISel::
SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
std::vector<SDValue> &OutOps) {
assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
SDValue Base, Offset, Opc;
if (!SelectAddrMode2(Op, Op, Base, Offset, Opc))
return true;
OutOps.push_back(Base);
OutOps.push_back(Offset);
OutOps.push_back(Opc);
// Require the address to be in a register. That is safe for all ARM
// variants and it is hard to do anything much smarter without knowing
// how the operand is used.
OutOps.push_back(Op);
return false;
}

5
lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
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@ -1017,7 +1017,10 @@ bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
const char *ExtraCode) {
if (ExtraCode && ExtraCode[0])
return true; // Unknown modifier.
printAddrMode2Operand(MI, OpNum);
const MachineOperand &MO = MI->getOperand(OpNum);
assert(MO.isReg() && "unexpected inline asm memory operand");
O << "[" << getRegisterName(MO.getReg()) << "]";
return false;
}

4
test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll
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@ -1,7 +1,9 @@
; RUN: llc < %s -march=arm | grep swp
; RUN: llc < %s -march=arm | FileCheck %s
; RUN: llc < %s -march=thumb | FileCheck %s
; PR4091
define void @foo(i32 %i, i32* %p) nounwind {
;CHECK: swp r2, r0, [r1]
%asmtmp = call i32 asm sideeffect "swp $0, $2, $3", "=&r,=*m,r,*m,~{memory}"(i32* %p, i32 %i, i32* %p) nounwind
ret void
}