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TableGen: Generate more const goodness
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233857 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -233,7 +233,7 @@ EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
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OS << "// Get the name of this register unit pressure set.\n"
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<< "const char *" << ClassName << "::\n"
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<< "getRegPressureSetName(unsigned Idx) const {\n"
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<< " static const char *PressureNameTable[] = {\n";
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<< " static const char *const PressureNameTable[] = {\n";
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unsigned MaxRegUnitWeight = 0;
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for (unsigned i = 0; i < NumSets; ++i ) {
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const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
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@ -752,7 +752,7 @@ RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS,
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Idx += Sequence.size() + 1;
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}
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OS << " };\n"
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" static const MaskRolOp *CompositeSequences[] = {\n";
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" static const MaskRolOp *const CompositeSequences[] = {\n";
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for (size_t i = 0, e = SubRegIndices.size(); i != e; ++i) {
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OS << " ";
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unsigned Idx = SubReg2SequenceIndexMap[i];
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