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Merge intrinsic instruction definitions for SSE and AVX versions of RCPPS and RSQRTPS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171339 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3007,7 +3007,32 @@ let Predicates = [HasAVX] in {
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/// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
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multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
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Intrinsic V4F32Int, OpndItins itins> {
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Intrinsic V4F32Int, Intrinsic V8F32Int,
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OpndItins itins> {
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let Predicates = [HasAVX] in {
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def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(!strconcat("v", OpcodeStr),
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"ps\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (V4F32Int VR128:$src))],
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itins.rr>, VEX;
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def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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!strconcat(!strconcat("v", OpcodeStr),
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"ps\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
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itins.rm>, VEX;
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def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
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!strconcat(!strconcat("v", OpcodeStr),
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"ps\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst, (V8F32Int VR256:$src))],
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itins.rr>, VEX, VEX_L;
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def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
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(ins f256mem:$src),
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!strconcat(!strconcat("v", OpcodeStr),
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"ps\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst, (V8F32Int (memopv8f32 addr:$src)))],
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itins.rm>, VEX, VEX_L;
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}
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def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (V4F32Int VR128:$src))],
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@ -3018,19 +3043,6 @@ multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
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itins.rm>;
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}
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/// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
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multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
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Intrinsic V4F32Int, OpndItins itins> {
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def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
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!strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst, (V4F32Int VR256:$src))],
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itins.rr>, VEX_L;
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def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
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!strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))],
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itins.rm>, VEX_L;
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}
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/// sse2_fp_unop_s - SSE2 unops in scalar form.
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multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
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SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
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@ -3103,8 +3115,12 @@ let Predicates = [HasAVX] in {
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defm SQRT : sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTP>,
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sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTP>;
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defm RSQRT : sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTP>;
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defm RCP : sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>;
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defm RSQRT : sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTP>,
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sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
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int_x86_avx_rsqrt_ps_256, SSE_SQRTP>;
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defm RCP : sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
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sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
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int_x86_avx_rcp_ps_256, SSE_RCPP>;
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let Predicates = [HasAVX] in {
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// Square root.
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@ -3114,16 +3130,7 @@ let Predicates = [HasAVX] in {
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// Reciprocal approximations. Note that these typically require refinement
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// in order to obtain suitable precision.
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defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
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defm VRSQRT : sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256,
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SSE_SQRTP>,
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sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps,
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SSE_SQRTP>, VEX;
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defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
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defm VRCP : sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256,
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SSE_RCPP>,
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sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps,
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SSE_RCPP>, VEX;
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}
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def : Pat<(f32 (fsqrt FR32:$src)),
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@ -3215,17 +3222,14 @@ multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,
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// Reciprocal approximations. Note that these typically require refinement
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// in order to obtain suitable precision.
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defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss,
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SSE_SQRTS>,
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sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
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SSE_SQRTP>;
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SSE_SQRTS>;
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let Predicates = [UseSSE1] in {
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def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
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(RSQRTSSr_Int VR128:$src, VR128:$src)>;
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}
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defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss,
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SSE_RCPS>,
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sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps, SSE_RCPP>;
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SSE_RCPS>;
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let Predicates = [UseSSE1] in {
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def : Pat<(int_x86_sse_rcp_ss VR128:$src),
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(RCPSSr_Int VR128:$src, VR128:$src)>;
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