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Add codegen support for NEON vld4 intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83479 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1445,18 +1445,61 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
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return NULL;
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if (VT.is64BitVector()) {
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vld4 type");
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case MVT::v8i8: Opc = ARM::VLD4d8; break;
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case MVT::v4i16: Opc = ARM::VLD4d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VLD4d32; break;
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}
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SDValue Chain = N->getOperand(0);
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
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std::vector<EVT> ResTys(4, VT);
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ResTys.push_back(MVT::Other);
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return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 4);
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}
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// Quad registers are loaded with two separate instructions, where one
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// loads the even registers and the other loads the odd registers.
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EVT RegVT = VT;
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unsigned Opc2 = 0;
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vld4 type");
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case MVT::v8i8: Opc = ARM::VLD4d8; break;
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case MVT::v4i16: Opc = ARM::VLD4d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VLD4d32; break;
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case MVT::v16i8:
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Opc = ARM::VLD4q8a; Opc2 = ARM::VLD4q8b; RegVT = MVT::v8i8; break;
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case MVT::v8i16:
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Opc = ARM::VLD4q16a; Opc2 = ARM::VLD4q16b; RegVT = MVT::v4i16; break;
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case MVT::v4f32:
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Opc = ARM::VLD4q32a; Opc2 = ARM::VLD4q32b; RegVT = MVT::v2f32; break;
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case MVT::v4i32:
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Opc = ARM::VLD4q32a; Opc2 = ARM::VLD4q32b; RegVT = MVT::v2i32; break;
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}
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SDValue Chain = N->getOperand(0);
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
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std::vector<EVT> ResTys(4, VT);
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// Enable writeback to the address register.
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MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
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std::vector<EVT> ResTys(4, RegVT);
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ResTys.push_back(MemAddr.getValueType());
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ResTys.push_back(MVT::Other);
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return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 4);
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const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, Chain };
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SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 4);
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Chain = SDValue(VLdA, 5);
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const SDValue OpsB[] = { SDValue(VLdA, 4), MemUpdate, MemOpc, Chain };
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SDNode *VLdB = CurDAG->getMachineNode(Opc2, dl, ResTys, OpsB, 4);
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Chain = SDValue(VLdB, 5);
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SDNode *Q0 = PairDRegs(VT, SDValue(VLdA, 0), SDValue(VLdB, 0));
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SDNode *Q1 = PairDRegs(VT, SDValue(VLdA, 1), SDValue(VLdB, 1));
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SDNode *Q2 = PairDRegs(VT, SDValue(VLdA, 2), SDValue(VLdB, 2));
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SDNode *Q3 = PairDRegs(VT, SDValue(VLdA, 3), SDValue(VLdB, 3));
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ReplaceUses(SDValue(N, 0), SDValue(Q0, 0));
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ReplaceUses(SDValue(N, 1), SDValue(Q1, 0));
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ReplaceUses(SDValue(N, 2), SDValue(Q2, 0));
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ReplaceUses(SDValue(N, 3), SDValue(Q3, 0));
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ReplaceUses(SDValue(N, 4), Chain);
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return NULL;
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}
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case Intrinsic::arm_neon_vld2lane: {
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@ -227,11 +227,26 @@ class VLD4D<string OpcodeStr>
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(ins addrmode6:$addr), IIC_VLD4,
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!strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"),
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"", []>;
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class VLD4WB<string OpcodeStr>
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: NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
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(ins addrmode6:$addr), IIC_VLD4,
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!strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"),
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"$addr.addr = $wb", []>;
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def VLD4d8 : VLD4D<"vld4.8">;
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def VLD4d16 : VLD4D<"vld4.16">;
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def VLD4d32 : VLD4D<"vld4.32">;
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// vld4 to double-spaced even registers.
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def VLD4q8a : VLD4WB<"vld4.8">;
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def VLD4q16a : VLD4WB<"vld4.16">;
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def VLD4q32a : VLD4WB<"vld4.32">;
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// vld4 to double-spaced odd registers.
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def VLD4q8b : VLD4WB<"vld4.8">;
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def VLD4q16b : VLD4WB<"vld4.16">;
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def VLD4q32b : VLD4WB<"vld4.32">;
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// VLD2LN : Vector Load (single 2-element structure to one lane)
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class VLD2LND<string OpcodeStr>
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: NLdSt<(outs DPR:$dst1, DPR:$dst2),
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@ -101,6 +101,24 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
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NumRegs = 4;
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return true;
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case ARM::VLD4q8a:
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case ARM::VLD4q16a:
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case ARM::VLD4q32a:
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FirstOpnd = 0;
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NumRegs = 4;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VLD4q8b:
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case ARM::VLD4q16b:
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case ARM::VLD4q32b:
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FirstOpnd = 0;
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NumRegs = 4;
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Offset = 1;
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Stride = 2;
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return true;
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case ARM::VST2d8:
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case ARM::VST2d16:
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case ARM::VST2d32:
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@ -5,6 +5,11 @@
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%struct.__neon_int32x2x4_t = type { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> }
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%struct.__neon_float32x2x4_t = type { <2 x float>, <2 x float>, <2 x float>, <2 x float> }
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%struct.__neon_int8x16x4_t = type { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> }
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%struct.__neon_int16x8x4_t = type { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }
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%struct.__neon_int32x4x4_t = type { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> }
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%struct.__neon_float32x4x4_t = type { <4 x float>, <4 x float>, <4 x float>, <4 x float> }
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define <8 x i8> @vld4i8(i8* %A) nounwind {
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;CHECK: vld4i8:
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;CHECK: vld4.8
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@ -45,7 +50,56 @@ define <2 x float> @vld4f(float* %A) nounwind {
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ret <2 x float> %tmp4
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}
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define <16 x i8> @vld4Qi8(i8* %A) nounwind {
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;CHECK: vld4Qi8:
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;CHECK: vld4.8
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;CHECK: vld4.8
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%tmp1 = call %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8(i8* %A)
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%tmp2 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 2
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%tmp4 = add <16 x i8> %tmp2, %tmp3
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ret <16 x i8> %tmp4
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}
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define <8 x i16> @vld4Qi16(i16* %A) nounwind {
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;CHECK: vld4Qi16:
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;CHECK: vld4.16
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;CHECK: vld4.16
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%tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i16* %A)
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%tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 2
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%tmp4 = add <8 x i16> %tmp2, %tmp3
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vld4Qi32(i32* %A) nounwind {
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;CHECK: vld4Qi32:
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;CHECK: vld4.32
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;CHECK: vld4.32
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%tmp1 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32(i32* %A)
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%tmp2 = extractvalue %struct.__neon_int32x4x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int32x4x4_t %tmp1, 2
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%tmp4 = add <4 x i32> %tmp2, %tmp3
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ret <4 x i32> %tmp4
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}
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define <4 x float> @vld4Qf(float* %A) nounwind {
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;CHECK: vld4Qf:
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;CHECK: vld4.32
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;CHECK: vld4.32
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%tmp1 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32(float* %A)
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%tmp2 = extractvalue %struct.__neon_float32x4x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_float32x4x4_t %tmp1, 2
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%tmp4 = add <4 x float> %tmp2, %tmp3
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ret <4 x float> %tmp4
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}
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declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8*) nounwind readonly
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declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16(i8*) nounwind readonly
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declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8*) nounwind readonly
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declare %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32(i8*) nounwind readonly
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declare %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8(i8*) nounwind readonly
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declare %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8*) nounwind readonly
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declare %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32(i8*) nounwind readonly
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declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32(i8*) nounwind readonly
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