mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
84fbac5809
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770bcc7b15
@ -433,14 +433,6 @@ public:
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return true;
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}
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/// getPointerRegClass - Returns a TargetRegisterClass used for pointer
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/// values.
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virtual const TargetRegisterClass *getPointerRegClass() const {
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assert(0 && "Target didn't implement getPointerRegClass!");
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abort();
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return 0; // Must return a value in order to compile with VS 2005
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}
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/// GetInstSize - Returns the size of the specified Instruction.
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///
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virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const {
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@ -422,11 +422,13 @@ public:
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return i ? RegClassBegin[i - 1] : NULL;
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}
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//===--------------------------------------------------------------------===//
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// Interfaces used by the register allocator and stack frame
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// manipulation passes to move data around between registers,
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// immediates and memory. FIXME: Move these to TargetInstrInfo.h.
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//
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/// getPointerRegClass - Returns a TargetRegisterClass used for pointer
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/// values.
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virtual const TargetRegisterClass *getPointerRegClass() const {
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assert(0 && "Target didn't implement getPointerRegClass!");
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abort();
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return 0; // Must return a value in order to compile with VS 2005
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}
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/// getCrossCopyRegClass - Returns a legal register class to copy a register
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/// in the specified class to or from. Returns NULL if it is possible to copy
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@ -479,7 +481,6 @@ public:
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int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
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int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
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/// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
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/// code insertion to eliminate call frame setup and destroy pseudo
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/// instructions (but only if the Target is using them). It is responsible
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@ -237,12 +237,11 @@ void SchedulePostRATDList::Schedule() {
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/// instruction of the specified TargetInstrDesc.
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static const TargetRegisterClass*
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getInstrOperandRegClass(const TargetRegisterInfo *TRI,
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const TargetInstrInfo *TII, const TargetInstrDesc &II,
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unsigned Op) {
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const TargetInstrDesc &II, unsigned Op) {
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if (Op >= II.getNumOperands())
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return NULL;
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if (II.OpInfo[Op].isLookupPtrRegClass())
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return TII->getPointerRegClass();
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return TRI->getPointerRegClass();
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return TRI->getRegClass(II.OpInfo[Op].RegClass);
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}
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@ -490,7 +489,7 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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const TargetRegisterClass *NewRC =
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getInstrOperandRegClass(TRI, TII, MI->getDesc(), i);
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getInstrOperandRegClass(TRI, MI->getDesc(), i);
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// If this instruction has a use of AntiDepReg, breaking it
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// is invalid.
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@ -625,7 +624,7 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
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if (!MO.isUse()) continue;
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const TargetRegisterClass *NewRC =
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getInstrOperandRegClass(TRI, TII, MI->getDesc(), i);
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getInstrOperandRegClass(TRI, MI->getDesc(), i);
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// For now, only allow the register to be changed if its register
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// class is consistent across all uses.
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@ -32,14 +32,13 @@ using namespace llvm;
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/// instruction of the specified TargetInstrDesc.
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static const TargetRegisterClass*
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getInstrOperandRegClass(const TargetRegisterInfo *TRI,
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const TargetInstrInfo *TII, const TargetInstrDesc &II,
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unsigned Op) {
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const TargetInstrDesc &II, unsigned Op) {
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if (Op >= II.getNumOperands()) {
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assert(II.isVariadic() && "Invalid operand # of instruction");
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return NULL;
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}
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if (II.OpInfo[Op].isLookupPtrRegClass())
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return TII->getPointerRegClass();
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return TRI->getPointerRegClass();
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return TRI->getRegClass(II.OpInfo[Op].RegClass);
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}
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@ -91,7 +90,7 @@ void ScheduleDAGSDNodes::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
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if (User->isMachineOpcode()) {
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const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
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const TargetRegisterClass *RC =
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getInstrOperandRegClass(TRI,TII,II,i+II.getNumDefs());
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getInstrOperandRegClass(TRI, II, i+II.getNumDefs());
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if (!UseRC)
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UseRC = RC;
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else if (RC)
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@ -190,7 +189,7 @@ void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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// Create the result registers for this node and add the result regs to
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// the machine instruction.
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if (VRBase == 0) {
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const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TII, II, i);
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const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, II, i);
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assert(RC && "Isn't a register operand!");
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VRBase = MRI.createVirtualRegister(RC);
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MI->addOperand(MachineOperand::CreateReg(VRBase, true));
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@ -258,8 +257,7 @@ void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op,
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// There may be no register class for this operand if it is a variadic
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// argument (RC will be NULL in this case). In this case, we just assume
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// the regclass is ok.
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const TargetRegisterClass *RC =
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getInstrOperandRegClass(TRI, TII, *II, IIOpNum);
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const TargetRegisterClass *RC= getInstrOperandRegClass(TRI, *II, IIOpNum);
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assert((RC || II->isVariadic()) && "Expected reg class info!");
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const TargetRegisterClass *VRC = MRI.getRegClass(VReg);
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if (RC && VRC != RC) {
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@ -327,7 +325,7 @@ void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op,
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// an FP vreg on x86.
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assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
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if (II && !II->isVariadic()) {
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assert(getInstrOperandRegClass(TRI, TII, *II, IIOpNum) &&
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assert(getInstrOperandRegClass(TRI, *II, IIOpNum) &&
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"Don't have operand info for this instruction!");
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}
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}
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@ -43,9 +43,6 @@ ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
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RI(*this, STI) {
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}
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const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
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return &ARM::GPRRegClass;
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}
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/// Return true if the instruction is a register to register move and
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/// leave the source and dest operands in the passed parameters.
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@ -151,10 +151,6 @@ public:
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///
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virtual const ARMRegisterInfo &getRegisterInfo() const { return RI; }
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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virtual const TargetRegisterClass *getPointerRegClass() const;
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/// Return true if the instruction is a register to register move and return
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/// the source and dest operands and their sub-register indices by reference.
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virtual bool isMoveInstr(const MachineInstr &MI,
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@ -191,6 +191,10 @@ void ARMRegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
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.addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
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}
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const TargetRegisterClass *ARMRegisterInfo::getPointerRegClass() const {
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return &ARM::GPRRegClass;
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}
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/// isLowRegister - Returns true if the register is low register r0-r7.
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///
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bool ARMRegisterInfo::isLowRegister(unsigned Reg) const {
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@ -48,6 +48,10 @@ public:
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/// if the register is a single precision VFP register.
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static unsigned getRegisterNumbering(unsigned RegEnum, bool &isSPVFP);
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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const TargetRegisterClass *getPointerRegClass() const;
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/// Code Generation virtual methods...
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const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
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@ -53,14 +53,6 @@ SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
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RI(*TM.getSubtargetImpl(), *this)
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{ /* NOP */ }
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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const TargetRegisterClass *
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SPUInstrInfo::getPointerRegClass() const
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{
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return &SPU::R32CRegClass;
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}
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bool
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SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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@ -45,10 +45,6 @@ namespace llvm {
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///
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virtual const SPURegisterInfo &getRegisterInfo() const { return RI; }
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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virtual const TargetRegisterClass *getPointerRegClass() const;
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/// Return true if the instruction is a register to register move and return
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/// the source and dest operands and their sub-register indices by reference.
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virtual bool isMoveInstr(const MachineInstr &MI,
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@ -216,6 +216,13 @@ SPURegisterInfo::getNumArgRegs()
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return sizeof(SPU_ArgRegs) / sizeof(SPU_ArgRegs[0]);
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}
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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const TargetRegisterClass * SPURegisterInfo::getPointerRegClass() const
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{
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return &SPU::R32CRegClass;
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}
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const unsigned *
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SPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const
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{
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*/
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static unsigned getRegisterNumbering(unsigned RegEnum);
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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virtual const TargetRegisterClass *getPointerRegClass() const;
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//! Return the array of callee-saved registers
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virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF) const;
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: TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
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RI(*TM.getSubtargetImpl(), *this) {}
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
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if (TM.getSubtargetImpl()->isPPC64())
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return &PPC::G8RCRegClass;
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else
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return &PPC::GPRCRegClass;
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}
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bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg,
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///
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virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; }
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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virtual const TargetRegisterClass *getPointerRegClass() const;
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/// Return true if the instruction is a register to register move and return
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/// the source and dest operands and their sub-register indices by reference.
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virtual bool isMoveInstr(const MachineInstr &MI,
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ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
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}
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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const TargetRegisterClass *PPCRegisterInfo::getPointerRegClass() const {
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if (Subtarget.isPPC64())
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return &PPC::G8RCRegClass;
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else
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return &PPC::GPRCRegClass;
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}
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const unsigned*
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PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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// 32-bit Darwin calling convention.
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/// PPC::F14, return the number that it corresponds to (e.g. 14).
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static unsigned getRegisterNumbering(unsigned RegEnum);
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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virtual const TargetRegisterClass *getPointerRegClass() const;
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/// Code Generation virtual methods...
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const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
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const TargetInstrDesc &TID = get(Opc);
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const TargetOperandInfo &TOI = TID.OpInfo[Index];
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const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
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? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
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? RI.getPointerRegClass() : RI.getRegClass(TOI.RegClass);
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SmallVector<MachineOperand,4> AddrOps;
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SmallVector<MachineOperand,2> BeforeOps;
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SmallVector<MachineOperand,2> AfterOps;
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@ -2345,7 +2345,7 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
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if (UnfoldStore) {
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const TargetOperandInfo &DstTOI = TID.OpInfo[0];
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const TargetRegisterClass *DstRC = DstTOI.isLookupPtrRegClass()
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? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
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? RI.getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
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storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
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}
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@ -2369,7 +2369,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
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const TargetInstrDesc &TID = get(Opc);
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const TargetOperandInfo &TOI = TID.OpInfo[Index];
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const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
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? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
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? RI.getPointerRegClass() : RI.getRegClass(TOI.RegClass);
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std::vector<SDValue> AddrOps;
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std::vector<SDValue> BeforeOps;
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std::vector<SDValue> AfterOps;
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@ -2406,7 +2406,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
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if (TID.getNumDefs() > 0) {
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const TargetOperandInfo &DstTOI = TID.OpInfo[0];
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DstRC = DstTOI.isLookupPtrRegClass()
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? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
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? RI.getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
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VTs.push_back(*DstRC->vt_begin());
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}
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for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
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@ -2490,14 +2490,6 @@ isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
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RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
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}
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const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
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const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
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if (Subtarget->is64Bit())
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return &X86::GR64RegClass;
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else
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return &X86::GR32RegClass;
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}
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unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) {
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switch (Desc->TSFlags & X86II::ImmMask) {
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case X86II::Imm8: return 1;
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/// instruction that defines the specified register class.
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bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
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const TargetRegisterClass *getPointerRegClass() const;
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// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
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// specified machine instruction.
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//
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}
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}
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const TargetRegisterClass *X86RegisterInfo::getPointerRegClass() const {
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const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
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if (Subtarget->is64Bit())
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return &X86::GR64RegClass;
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else
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return &X86::GR32RegClass;
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}
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const TargetRegisterClass *
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X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
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if (RC == &X86::CCRRegClass) {
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@ -93,6 +93,10 @@ public:
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/// Code Generation virtual methods...
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///
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/// getPointerRegClass - Returns a TargetRegisterClass used for pointer
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/// values.
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const TargetRegisterClass *getPointerRegClass() const;
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/// getCrossCopyRegClass - Returns a legal register class to copy a register
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/// in the specified class to or from. Returns NULL if it is possible to copy
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/// between a two registers of the specified class.
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