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Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2009-02-06 17:43:24 +00:00
parent 84fbac5809
commit 770bcc7b15
20 changed files with 65 additions and 74 deletions
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9
lib/CodeGen/PostRASchedulerList.cpp
View File

@@ -237,12 +237,11 @@ void SchedulePostRATDList::Schedule() {
/// instruction of the specified TargetInstrDesc.
static const TargetRegisterClass*
getInstrOperandRegClass(const TargetRegisterInfo *TRI,
const TargetInstrInfo *TII, const TargetInstrDesc &II,
unsigned Op) {
const TargetInstrDesc &II, unsigned Op) {
if (Op >= II.getNumOperands())
return NULL;
if (II.OpInfo[Op].isLookupPtrRegClass())
return TII->getPointerRegClass();
return TRI->getPointerRegClass();
return TRI->getRegClass(II.OpInfo[Op].RegClass);
}
@@ -490,7 +489,7 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
unsigned Reg = MO.getReg();
if (Reg == 0) continue;
const TargetRegisterClass *NewRC =
getInstrOperandRegClass(TRI, TII, MI->getDesc(), i);
getInstrOperandRegClass(TRI, MI->getDesc(), i);
// If this instruction has a use of AntiDepReg, breaking it
// is invalid.
@@ -625,7 +624,7 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
if (!MO.isUse()) continue;
const TargetRegisterClass *NewRC =
getInstrOperandRegClass(TRI, TII, MI->getDesc(), i);
getInstrOperandRegClass(TRI, MI->getDesc(), i);
// For now, only allow the register to be changed if its register
// class is consistent across all uses.

14
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
View File

@@ -32,14 +32,13 @@ using namespace llvm;
/// instruction of the specified TargetInstrDesc.
static const TargetRegisterClass*
getInstrOperandRegClass(const TargetRegisterInfo *TRI,
const TargetInstrInfo *TII, const TargetInstrDesc &II,
unsigned Op) {
const TargetInstrDesc &II, unsigned Op) {
if (Op >= II.getNumOperands()) {
assert(II.isVariadic() && "Invalid operand # of instruction");
return NULL;
}
if (II.OpInfo[Op].isLookupPtrRegClass())
return TII->getPointerRegClass();
return TRI->getPointerRegClass();
return TRI->getRegClass(II.OpInfo[Op].RegClass);
}
@@ -91,7 +90,7 @@ void ScheduleDAGSDNodes::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
if (User->isMachineOpcode()) {
const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
const TargetRegisterClass *RC =
getInstrOperandRegClass(TRI,TII,II,i+II.getNumDefs());
getInstrOperandRegClass(TRI, II, i+II.getNumDefs());
if (!UseRC)
UseRC = RC;
else if (RC)
@@ -190,7 +189,7 @@ void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
// Create the result registers for this node and add the result regs to
// the machine instruction.
if (VRBase == 0) {
const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TII, II, i);
const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, II, i);
assert(RC && "Isn't a register operand!");
VRBase = MRI.createVirtualRegister(RC);
MI->addOperand(MachineOperand::CreateReg(VRBase, true));
@@ -258,8 +257,7 @@ void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op,
// There may be no register class for this operand if it is a variadic
// argument (RC will be NULL in this case). In this case, we just assume
// the regclass is ok.
const TargetRegisterClass *RC =
getInstrOperandRegClass(TRI, TII, *II, IIOpNum);
const TargetRegisterClass *RC= getInstrOperandRegClass(TRI, *II, IIOpNum);
assert((RC || II->isVariadic()) && "Expected reg class info!");
const TargetRegisterClass *VRC = MRI.getRegClass(VReg);
if (RC && VRC != RC) {
@@ -327,7 +325,7 @@ void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op,
// an FP vreg on x86.
assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II && !II->isVariadic()) {
assert(getInstrOperandRegClass(TRI, TII, *II, IIOpNum) &&
assert(getInstrOperandRegClass(TRI, *II, IIOpNum) &&
"Don't have operand info for this instruction!");
}
}