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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-07-28 19:25:00 +00:00
Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -237,12 +237,11 @@ void SchedulePostRATDList::Schedule() {
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/// instruction of the specified TargetInstrDesc.
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static const TargetRegisterClass*
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getInstrOperandRegClass(const TargetRegisterInfo *TRI,
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const TargetInstrInfo *TII, const TargetInstrDesc &II,
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unsigned Op) {
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const TargetInstrDesc &II, unsigned Op) {
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if (Op >= II.getNumOperands())
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return NULL;
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if (II.OpInfo[Op].isLookupPtrRegClass())
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return TII->getPointerRegClass();
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return TRI->getPointerRegClass();
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return TRI->getRegClass(II.OpInfo[Op].RegClass);
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}
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@@ -490,7 +489,7 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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const TargetRegisterClass *NewRC =
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getInstrOperandRegClass(TRI, TII, MI->getDesc(), i);
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getInstrOperandRegClass(TRI, MI->getDesc(), i);
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// If this instruction has a use of AntiDepReg, breaking it
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// is invalid.
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@@ -625,7 +624,7 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
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if (!MO.isUse()) continue;
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const TargetRegisterClass *NewRC =
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getInstrOperandRegClass(TRI, TII, MI->getDesc(), i);
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getInstrOperandRegClass(TRI, MI->getDesc(), i);
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// For now, only allow the register to be changed if its register
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// class is consistent across all uses.
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@@ -32,14 +32,13 @@ using namespace llvm;
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/// instruction of the specified TargetInstrDesc.
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static const TargetRegisterClass*
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getInstrOperandRegClass(const TargetRegisterInfo *TRI,
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const TargetInstrInfo *TII, const TargetInstrDesc &II,
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unsigned Op) {
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const TargetInstrDesc &II, unsigned Op) {
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if (Op >= II.getNumOperands()) {
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assert(II.isVariadic() && "Invalid operand # of instruction");
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return NULL;
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}
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if (II.OpInfo[Op].isLookupPtrRegClass())
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return TII->getPointerRegClass();
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return TRI->getPointerRegClass();
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return TRI->getRegClass(II.OpInfo[Op].RegClass);
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}
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@@ -91,7 +90,7 @@ void ScheduleDAGSDNodes::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
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if (User->isMachineOpcode()) {
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const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
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const TargetRegisterClass *RC =
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getInstrOperandRegClass(TRI,TII,II,i+II.getNumDefs());
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getInstrOperandRegClass(TRI, II, i+II.getNumDefs());
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if (!UseRC)
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UseRC = RC;
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else if (RC)
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@@ -190,7 +189,7 @@ void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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// Create the result registers for this node and add the result regs to
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// the machine instruction.
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if (VRBase == 0) {
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const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TII, II, i);
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const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, II, i);
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assert(RC && "Isn't a register operand!");
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VRBase = MRI.createVirtualRegister(RC);
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MI->addOperand(MachineOperand::CreateReg(VRBase, true));
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@@ -258,8 +257,7 @@ void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op,
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// There may be no register class for this operand if it is a variadic
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// argument (RC will be NULL in this case). In this case, we just assume
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// the regclass is ok.
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const TargetRegisterClass *RC =
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getInstrOperandRegClass(TRI, TII, *II, IIOpNum);
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const TargetRegisterClass *RC= getInstrOperandRegClass(TRI, *II, IIOpNum);
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assert((RC || II->isVariadic()) && "Expected reg class info!");
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const TargetRegisterClass *VRC = MRI.getRegClass(VReg);
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if (RC && VRC != RC) {
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@@ -327,7 +325,7 @@ void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op,
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// an FP vreg on x86.
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assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
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if (II && !II->isVariadic()) {
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assert(getInstrOperandRegClass(TRI, TII, *II, IIOpNum) &&
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assert(getInstrOperandRegClass(TRI, *II, IIOpNum) &&
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"Don't have operand info for this instruction!");
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}
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}
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