Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/Target/TargetInstrInfo.h

@@ -433,14 +433,6 @@ public:
     return true;
   }
 
-  /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
-  /// values.
-  virtual const TargetRegisterClass *getPointerRegClass() const {
-    assert(0 && "Target didn't implement getPointerRegClass!");
-    abort();
-    return 0; // Must return a value in order to compile with VS 2005
-  }
-
   /// GetInstSize - Returns the size of the specified Instruction.
   /// 
   virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const {

include/llvm/Target/TargetRegisterInfo.h

@@ -422,11 +422,13 @@ public:
     return i ? RegClassBegin[i - 1] : NULL;
   }
 
-  //===--------------------------------------------------------------------===//
+  /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
-  // Interfaces used by the register allocator and stack frame
+  /// values.
-  // manipulation passes to move data around between registers,
+  virtual const TargetRegisterClass *getPointerRegClass() const {
-  // immediates and memory.  FIXME: Move these to TargetInstrInfo.h.
+    assert(0 && "Target didn't implement getPointerRegClass!");
-  //
+    abort();
+    return 0; // Must return a value in order to compile with VS 2005
+  }
 
   /// getCrossCopyRegClass - Returns a legal register class to copy a register
   /// in the specified class to or from. Returns NULL if it is possible to copy
@@ -479,7 +481,6 @@ public:
   int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
   int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
 
-
   /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
   /// code insertion to eliminate call frame setup and destroy pseudo
   /// instructions (but only if the Target is using them).  It is responsible

lib/CodeGen/PostRASchedulerList.cpp

@@ -237,12 +237,11 @@ void SchedulePostRATDList::Schedule() {
 /// instruction of the specified TargetInstrDesc.
 static const TargetRegisterClass*
 getInstrOperandRegClass(const TargetRegisterInfo *TRI,
-                        const TargetInstrInfo *TII, const TargetInstrDesc &II,
+                         const TargetInstrDesc &II, unsigned Op) {
-                        unsigned Op) {
   if (Op >= II.getNumOperands())
     return NULL;
   if (II.OpInfo[Op].isLookupPtrRegClass())
-    return TII->getPointerRegClass();
+    return TRI->getPointerRegClass();
   return TRI->getRegClass(II.OpInfo[Op].RegClass);
 }
 
@@ -490,7 +489,7 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
       unsigned Reg = MO.getReg();
       if (Reg == 0) continue;
       const TargetRegisterClass *NewRC =
-        getInstrOperandRegClass(TRI, TII, MI->getDesc(), i);
+        getInstrOperandRegClass(TRI, MI->getDesc(), i);
 
       // If this instruction has a use of AntiDepReg, breaking it
       // is invalid.
@@ -625,7 +624,7 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
       if (!MO.isUse()) continue;
 
       const TargetRegisterClass *NewRC =
-        getInstrOperandRegClass(TRI, TII, MI->getDesc(), i);
+        getInstrOperandRegClass(TRI, MI->getDesc(), i);
 
       // For now, only allow the register to be changed if its register
       // class is consistent across all uses.

lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp

@@ -32,14 +32,13 @@ using namespace llvm;
 /// instruction of the specified TargetInstrDesc.
 static const TargetRegisterClass*
 getInstrOperandRegClass(const TargetRegisterInfo *TRI, 
-                        const TargetInstrInfo *TII, const TargetInstrDesc &II,
+                        const TargetInstrDesc &II, unsigned Op) {
-                        unsigned Op) {
   if (Op >= II.getNumOperands()) {
     assert(II.isVariadic() && "Invalid operand # of instruction");
     return NULL;
   }
   if (II.OpInfo[Op].isLookupPtrRegClass())
-    return TII->getPointerRegClass();
+    return TRI->getPointerRegClass();
   return TRI->getRegClass(II.OpInfo[Op].RegClass);
 }
 
@@ -91,7 +90,7 @@ void ScheduleDAGSDNodes::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
           if (User->isMachineOpcode()) {
             const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
             const TargetRegisterClass *RC =
-              getInstrOperandRegClass(TRI,TII,II,i+II.getNumDefs());
+              getInstrOperandRegClass(TRI, II, i+II.getNumDefs());
             if (!UseRC)
               UseRC = RC;
             else if (RC)
@@ -190,7 +189,7 @@ void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
     // Create the result registers for this node and add the result regs to
     // the machine instruction.
     if (VRBase == 0) {
-      const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TII, II, i);
+      const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, II, i);
       assert(RC && "Isn't a register operand!");
       VRBase = MRI.createVirtualRegister(RC);
       MI->addOperand(MachineOperand::CreateReg(VRBase, true));
@@ -258,8 +257,7 @@ void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op,
       // There may be no register class for this operand if it is a variadic
       // argument (RC will be NULL in this case).  In this case, we just assume
       // the regclass is ok.
-      const TargetRegisterClass *RC =
+      const TargetRegisterClass *RC= getInstrOperandRegClass(TRI, *II, IIOpNum);
-                          getInstrOperandRegClass(TRI, TII, *II, IIOpNum);
       assert((RC || II->isVariadic()) && "Expected reg class info!");
       const TargetRegisterClass *VRC = MRI.getRegClass(VReg);
       if (RC && VRC != RC) {
@@ -327,7 +325,7 @@ void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op,
     // an FP vreg on x86.
     assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
     if (II && !II->isVariadic()) {
-      assert(getInstrOperandRegClass(TRI, TII, *II, IIOpNum) &&
+      assert(getInstrOperandRegClass(TRI, *II, IIOpNum) &&
              "Don't have operand info for this instruction!");
     }
   }  

lib/Target/ARM/ARMInstrInfo.cpp

@@ -43,9 +43,6 @@ ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
     RI(*this, STI) {
 }
 
-const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
-  return &ARM::GPRRegClass;
-}
 
 /// Return true if the instruction is a register to register move and
 /// leave the source and dest operands in the passed parameters.

lib/Target/ARM/ARMInstrInfo.h

@@ -151,10 +151,6 @@ public:
   ///
   virtual const ARMRegisterInfo &getRegisterInfo() const { return RI; }
 
-  /// getPointerRegClass - Return the register class to use to hold pointers.
-  /// This is used for addressing modes.
-  virtual const TargetRegisterClass *getPointerRegClass() const;
-
   /// Return true if the instruction is a register to register move and return
   /// the source and dest operands and their sub-register indices by reference.
   virtual bool isMoveInstr(const MachineInstr &MI,

lib/Target/ARM/ARMRegisterInfo.cpp

@@ -191,6 +191,10 @@ void ARMRegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
       .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
 }
 
+const TargetRegisterClass *ARMRegisterInfo::getPointerRegClass() const {
+  return &ARM::GPRRegClass;
+}
+
 /// isLowRegister - Returns true if the register is low register r0-r7.
 ///
 bool ARMRegisterInfo::isLowRegister(unsigned Reg) const {

lib/Target/ARM/ARMRegisterInfo.h

@@ -48,6 +48,10 @@ public:
   /// if the register is a single precision VFP register.
   static unsigned getRegisterNumbering(unsigned RegEnum, bool &isSPVFP);
 
+  /// getPointerRegClass - Return the register class to use to hold pointers.
+  /// This is used for addressing modes.
+  const TargetRegisterClass *getPointerRegClass() const;
+
   /// Code Generation virtual methods...
   const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
 

lib/Target/CellSPU/SPUInstrInfo.cpp

@@ -53,14 +53,6 @@ SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
     RI(*TM.getSubtargetImpl(), *this)
 { /* NOP */ }
 
-/// getPointerRegClass - Return the register class to use to hold pointers.
-/// This is used for addressing modes.
-const TargetRegisterClass *
-SPUInstrInfo::getPointerRegClass() const
-{
-  return &SPU::R32CRegClass;
-}
-
 bool
 SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
                           unsigned& sourceReg,

lib/Target/CellSPU/SPUInstrInfo.h

@@ -45,10 +45,6 @@ namespace llvm {
     ///
     virtual const SPURegisterInfo &getRegisterInfo() const { return RI; }
 
-    /// getPointerRegClass - Return the register class to use to hold pointers.
-    /// This is used for addressing modes.
-    virtual const TargetRegisterClass *getPointerRegClass() const;
-
     /// Return true if the instruction is a register to register move and return
     /// the source and dest operands and their sub-register indices by reference.
     virtual bool isMoveInstr(const MachineInstr &MI,

lib/Target/CellSPU/SPURegisterInfo.cpp

@@ -216,6 +216,13 @@ SPURegisterInfo::getNumArgRegs()
   return sizeof(SPU_ArgRegs) / sizeof(SPU_ArgRegs[0]);
 }
 
+/// getPointerRegClass - Return the register class to use to hold pointers.
+/// This is used for addressing modes.
+const TargetRegisterClass * SPURegisterInfo::getPointerRegClass() const
+{
+  return &SPU::R32CRegClass;
+}
+
 const unsigned *
 SPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const
 {

lib/Target/CellSPU/SPURegisterInfo.h

@@ -41,6 +41,10 @@ namespace llvm {
      */
     static unsigned getRegisterNumbering(unsigned RegEnum);
 
+    /// getPointerRegClass - Return the register class to use to hold pointers.
+    /// This is used for addressing modes.
+    virtual const TargetRegisterClass *getPointerRegClass() const;
+
     //! Return the array of callee-saved registers
     virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF) const;
 

lib/Target/PowerPC/PPCInstrInfo.cpp

@@ -30,16 +30,6 @@ PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
   : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
     RI(*TM.getSubtargetImpl(), *this) {}
 
-/// getPointerRegClass - Return the register class to use to hold pointers.
-/// This is used for addressing modes.
-const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
-  if (TM.getSubtargetImpl()->isPPC64())
-    return &PPC::G8RCRegClass;
-  else
-    return &PPC::GPRCRegClass;
-}
-
-
 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
                                unsigned& sourceReg,
                                unsigned& destReg,

lib/Target/PowerPC/PPCInstrInfo.h

@@ -82,10 +82,6 @@ public:
   ///
   virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; }
 
-  /// getPointerRegClass - Return the register class to use to hold pointers.
-  /// This is used for addressing modes.
-  virtual const TargetRegisterClass *getPointerRegClass() const;  
-
   /// Return true if the instruction is a register to register move and return
   /// the source and dest operands and their sub-register indices by reference.
   virtual bool isMoveInstr(const MachineInstr &MI,

lib/Target/PowerPC/PPCRegisterInfo.cpp

@@ -137,6 +137,15 @@ PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
   ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
 }
 
+/// getPointerRegClass - Return the register class to use to hold pointers.
+/// This is used for addressing modes.
+const TargetRegisterClass *PPCRegisterInfo::getPointerRegClass() const {
+  if (Subtarget.isPPC64())
+    return &PPC::G8RCRegClass;
+  else
+    return &PPC::GPRCRegClass;
+}
+
 const unsigned*
 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   // 32-bit Darwin calling convention. 

lib/Target/PowerPC/PPCRegisterInfo.h

@@ -35,6 +35,10 @@ public:
   /// PPC::F14, return the number that it corresponds to (e.g. 14).
   static unsigned getRegisterNumbering(unsigned RegEnum);
 
+  /// getPointerRegClass - Return the register class to use to hold pointers.
+  /// This is used for addressing modes.
+  virtual const TargetRegisterClass *getPointerRegClass() const;  
+
   /// Code Generation virtual methods...
   const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
 

lib/Target/X86/X86InstrInfo.cpp

@@ -2270,7 +2270,7 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
   const TargetInstrDesc &TID = get(Opc);
   const TargetOperandInfo &TOI = TID.OpInfo[Index];
   const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
-    ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
+    ? RI.getPointerRegClass() : RI.getRegClass(TOI.RegClass);
   SmallVector<MachineOperand,4> AddrOps;
   SmallVector<MachineOperand,2> BeforeOps;
   SmallVector<MachineOperand,2> AfterOps;
@@ -2345,7 +2345,7 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
   if (UnfoldStore) {
     const TargetOperandInfo &DstTOI = TID.OpInfo[0];
     const TargetRegisterClass *DstRC = DstTOI.isLookupPtrRegClass()
-      ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
+      ? RI.getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
   }
 
@@ -2369,7 +2369,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
   const TargetInstrDesc &TID = get(Opc);
   const TargetOperandInfo &TOI = TID.OpInfo[Index];
   const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
-    ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
+    ? RI.getPointerRegClass() : RI.getRegClass(TOI.RegClass);
   std::vector<SDValue> AddrOps;
   std::vector<SDValue> BeforeOps;
   std::vector<SDValue> AfterOps;
@@ -2406,7 +2406,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
   if (TID.getNumDefs() > 0) {
     const TargetOperandInfo &DstTOI = TID.OpInfo[0];
     DstRC = DstTOI.isLookupPtrRegClass()
-      ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
+      ? RI.getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
     VTs.push_back(*DstRC->vt_begin());
   }
   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
@@ -2490,14 +2490,6 @@ isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
 }
 
-const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
-  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
-  if (Subtarget->is64Bit())
-    return &X86::GR64RegClass;
-  else
-    return &X86::GR32RegClass;
-}
-
 unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) {
   switch (Desc->TSFlags & X86II::ImmMask) {
   case X86II::Imm8:   return 1;

lib/Target/X86/X86InstrInfo.h

@@ -410,8 +410,6 @@ public:
   /// instruction that defines the specified register class.
   bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
 
-  const TargetRegisterClass *getPointerRegClass() const;
-
   // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
   // specified machine instruction.
   //

lib/Target/X86/X86RegisterInfo.cpp

@@ -151,6 +151,14 @@ unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
   }
 }
 
+const TargetRegisterClass *X86RegisterInfo::getPointerRegClass() const {
+  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
+  if (Subtarget->is64Bit())
+    return &X86::GR64RegClass;
+  else
+    return &X86::GR32RegClass;
+}
+
 const TargetRegisterClass *
 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
   if (RC == &X86::CCRRegClass) {

lib/Target/X86/X86RegisterInfo.h

@@ -93,6 +93,10 @@ public:
   /// Code Generation virtual methods...
   /// 
 
+  /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
+  /// values.
+  const TargetRegisterClass *getPointerRegClass() const;
+
   /// getCrossCopyRegClass - Returns a legal register class to copy a register
   /// in the specified class to or from. Returns NULL if it is possible to copy
   /// between a two registers of the specified class.