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R600: support fpext/fptrunc operations to and from f16.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213376 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2014-07-18 13:01:37 +00:00
parent 1a8bcdb72e
commit 7714a60ed1
2 changed files with 35 additions and 0 deletions
lib/Target/R600
AMDGPUISelLowering.cpp
test/CodeGen/R600
half.ll

4
lib/Target/R600/AMDGPUISelLowering.cpp

@ -244,6 +244,10 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
setTruncStoreAction(MVT::f32, MVT::f16, Expand);
setTruncStoreAction(MVT::f64, MVT::f16, Expand);
const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
for (MVT VT : ScalarIntVTs) {
setOperationAction(ISD::SREM, VT, Expand);

31
test/CodeGen/R600/half.ll

@ -28,3 +28,34 @@ define void @test_bitcast_to_half(half addrspace(1)* %out, i16 addrspace(1)* %in
store half %val_fp, half addrspace(1)* %out
ret void
}
define void @test_extend32(half addrspace(1)* %in, float addrspace(1)* %out) {
; CHECK-LABEL: @test_extend32
; CHECK: V_CVT_F32_F16_e32
%val16 = load half addrspace(1)* %in
%val32 = fpext half %val16 to float
store float %val32, float addrspace(1)* %out
ret void
}
define void @test_extend64(half addrspace(1)* %in, double addrspace(1)* %out) {
; CHECK-LABEL: @test_extend64
; CHECK: V_CVT_F32_F16_e32
; CHECK: V_CVT_F64_F32_e32
%val16 = load half addrspace(1)* %in
%val64 = fpext half %val16 to double
store double %val64, double addrspace(1)* %out
ret void
}
define void @test_trunc32(float addrspace(1)* %in, half addrspace(1)* %out) {
; CHECK-LABEL: @test_trunc32
; CHECK: V_CVT_F16_F32_e32
%val32 = load float addrspace(1)* %in
%val16 = fptrunc float %val32 to half
store half %val16, half addrspace(1)* %out
ret void
}