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Add support for emitting non-temporal stores for DAGs marked
non-temporal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96241 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Greene
parent
1e559443a1
commit
786da7dec2
@ -160,6 +160,32 @@ def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
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def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
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def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
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// MOVNT Support
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// Like 'store', but requires the non-temporal bit to be set
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def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
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(st node:$val, node:$ptr), [{
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if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
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return ST->isNonTemporal();
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return false;
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}]>;
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def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
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(st node:$val, node:$ptr), [{
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if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
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return ST->isNonTemporal() && !ST->isTruncatingStore() &&
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ST->getAddressingMode() == ISD::UNINDEXED &&
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ST->getAlignment() >= 16;
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return false;
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}]>;
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def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
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(st node:$val, node:$ptr), [{
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if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
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return ST->isNonTemporal() &&
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ST->getAlignment() < 16;
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return false;
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}]>;
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def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
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def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
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def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
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@ -1013,10 +1039,33 @@ def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
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"prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
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// Non-temporal stores
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def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
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def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
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"movntps\t{$src, $dst|$dst, $src}",
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[(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
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let AddedComplexity = 400 in { // Prefer non-temporal versions
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def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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"movntps\t{$src, $dst|$dst, $src}",
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[(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
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def MOVNTDQ_64mr : PSI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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"movntdq\t{$src, $dst|$dst, $src}",
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[(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
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def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
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(MOVNTDQ_64mr VR128:$src, addr:$dst)>;
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def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
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"movnti\t{$src, $dst|$dst, $src}",
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[(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
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TB, Requires<[HasSSE2]>;
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def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
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"movnti\t{$src, $dst|$dst, $src}",
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[(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
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TB, Requires<[HasSSE2]>;
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}
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// Load, store, and memory fence
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def SFENCE : PSI<0xAE, MRM7r, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
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@ -2298,17 +2347,30 @@ def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
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[(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
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// Non-temporal stores
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def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
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"movntpd\t{$src, $dst|$dst, $src}",
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[(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
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def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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"movntdq\t{$src, $dst|$dst, $src}",
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[(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
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def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
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def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
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"movntpd\t{$src, $dst|$dst, $src}",
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[(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
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def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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"movntdq\t{$src, $dst|$dst, $src}",
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[(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
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def MOVNTImr_Int : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
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"movnti\t{$src, $dst|$dst, $src}",
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[(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
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TB, Requires<[HasSSE2]>;
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let AddedComplexity = 400 in { // Prefer non-temporal versions
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def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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"movntpd\t{$src, $dst|$dst, $src}",
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[(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
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def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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"movntdq\t{$src, $dst|$dst, $src}",
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[(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
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def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
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(MOVNTDQmr VR128:$src, addr:$dst)>;
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}
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// Flush cache
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def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
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"clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
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84
test/CodeGen/X86/2010-02-11-NonTemporal.ll
Normal file
84
test/CodeGen/X86/2010-02-11-NonTemporal.ll
Normal file
@ -0,0 +1,84 @@
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; RUN: llc < %s -march=x86-64 | FileCheck %s
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; CHECK: movnt
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
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target triple = "x86_64-unknown-linux-gnu"
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@blk_ = linkonce global [700000 x i64] zeroinitializer, align 64 ; <[700000 x i64]*> [#uses=3]
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@_dm_my_pe = external global [1 x i64], align 64 ; <[1 x i64]*> [#uses=1]
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@_dm_pes_in_prog = external global [1 x i64], align 64 ; <[1 x i64]*> [#uses=1]
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@_dm_npes_div_mult = external global [1 x i64], align 64 ; <[1 x i64]*> [#uses=1]
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@_dm_npes_div_shift = external global [1 x i64], align 64 ; <[1 x i64]*> [#uses=1]
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@_dm_pe_addr_loc = external global [1 x i64], align 64 ; <[1 x i64]*> [#uses=1]
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@_dm_offset_addr_mask = external global [1 x i64], align 64 ; <[1 x i64]*> [#uses=1]
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!0 = metadata !{ i32 1 }
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define void @sub_(i32* noalias %n) {
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"file movnt.f90, line 2, bb1": ; srcLine 2
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%n1 = alloca i32*, align 8 ; <i32**> [#uses=1] ; [oox.12 : sln.2]
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%i = alloca i32, align 4 ; <i32*> [#uses=0] ; [oox.14 : sln.2]
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%"$LIS_E0" = alloca i64, align 8 ; <i64*> [#uses=2] ; [oox.72 : sln.2]
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%"$LCS_0" = alloca i64, align 8 ; <i64*> [#uses=7] ; [oox.73 : sln.2]
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%"$SI_S1" = alloca i64, align 8 ; <i64*> [#uses=4] ; [oox.75 : sln.2]
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%"$LCS_S2" = alloca <2 x double>, align 16 ; <<2 x double>*> [#uses=6] ; [oox.76 : sln.2]
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%"$LC_S3" = alloca i64, align 8 ; <i64*> [#uses=4] ; [oox.77 : sln.2]
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volatile store i32* %n, i32** %n1 ; [oox.12 : sln.2]
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br label %"file movnt.f90, line 2, bb32" ; [oox.0 : sln.0]
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"file movnt.f90, line 2, bb32": ; srcLine 2 ; preds = %"file movnt.f90, line 2, bb1"
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store i64 -50000, i64* %"$LC_S3", align 8 ; [oox.160 : sln.10]
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store i64 0, i64* %"$SI_S1", align 8 ; [oox.161 : sln.10]
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store i64 ptrtoint ([700000 x i64]* @blk_ to i64), i64* %"$LIS_E0", align 8 ; [oox.162 : sln.11]
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br label %"file movnt.f90, line 2, in inner vector loop at depth 0, bb25" ; [oox.0 : sln.0]
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"file movnt.f90, line 2, in inner vector loop at depth 0, bb25": ; srcLine 2 ; preds = %"file movnt.f90, line 11, in inner vector loop at depth 0, bb23", %"file movnt.f90, line 2, bb32"
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br label %"file movnt.f90, line 11, in inner vector loop at depth 0, bb23" ; [oox.0 : sln.0]
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"file movnt.f90, line 11, in inner vector loop at depth 0, bb23": ; srcLine 11 ; preds = %"file movnt.f90, line 2, in inner vector loop at depth 0, bb25"
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%r = load i64* %"$LIS_E0", align 8 ; <i64> [#uses=1] ; [oox.159 : sln.11]
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%r2 = load i64* %"$SI_S1", align 8 ; <i64> [#uses=1] ; [oox.159 : sln.11]
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%r3 = add i64 %r, %r2 ; <i64> [#uses=1] ; [oox.159 : sln.11]
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store i64 %r3, i64* %"$LCS_0", align 8 ; [oox.159 : sln.11]
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%r4 = load i64* %"$LCS_0", align 8 ; <i64> [#uses=1] ; [oox.160 : sln.11]
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%r5 = add i64 4000000, %r4 ; <i64> [#uses=1] ; [oox.160 : sln.11]
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%r6 = inttoptr i64 %r5 to <2 x double>* ; <<2 x double>*> [#uses=2] ; [oox.160 : sln.11]
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%r8 = load <2 x double>* %r6, align 16, !nontemporal !0 ; <<2 x double>> [#uses=1] ; [oox.160 : sln.11]
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store <2 x double> %r8, <2 x double>* %"$LCS_S2", align 8 ; [oox.160 : sln.11]
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%r9 = load <2 x double>* %"$LCS_S2", align 8 ; <<2 x double>> [#uses=1] ; [oox.161 : sln.11]
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%r10 = load i64* %"$LCS_0", align 8 ; <i64> [#uses=1] ; [oox.161 : sln.11]
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%r11 = inttoptr i64 %r10 to <2 x double>* ; <<2 x double>*> [#uses=2] ; [oox.161 : sln.11]
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store <2 x double> %r9, <2 x double>* %r11, align 16, !nontemporal !0 ; [oox.161 : sln.11]
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%r13 = load <2 x double>* %"$LCS_S2", align 8 ; <<2 x double>> [#uses=1] ; [oox.162 : sln.12]
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%r14 = load i64* %"$LCS_0", align 8 ; <i64> [#uses=1] ; [oox.162 : sln.12]
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%r15 = add i64 800000, %r14 ; <i64> [#uses=1] ; [oox.162 : sln.12]
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%r16 = inttoptr i64 %r15 to <2 x double>* ; <<2 x double>*> [#uses=2] ; [oox.162 : sln.12]
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store <2 x double> %r13, <2 x double>* %r16, align 16, !nontemporal !0 ; [oox.162 : sln.12]
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%r18 = load <2 x double>* %"$LCS_S2", align 8 ; <<2 x double>> [#uses=1] ; [oox.163 : sln.13]
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%r19 = load i64* %"$LCS_0", align 8 ; <i64> [#uses=1] ; [oox.163 : sln.13]
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%r20 = add i64 1600000, %r19 ; <i64> [#uses=1] ; [oox.163 : sln.13]
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%r21 = inttoptr i64 %r20 to <2 x double>* ; <<2 x double>*> [#uses=2] ; [oox.163 : sln.13]
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store <2 x double> %r18, <2 x double>* %r21, align 16, !nontemporal !0 ; [oox.163 : sln.13]
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%r23 = load <2 x double>* %"$LCS_S2", align 8 ; <<2 x double>> [#uses=1] ; [oox.164 : sln.14]
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%r24 = load i64* %"$LCS_0", align 8 ; <i64> [#uses=1] ; [oox.164 : sln.14]
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%r25 = add i64 2400000, %r24 ; <i64> [#uses=1] ; [oox.164 : sln.14]
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%r26 = inttoptr i64 %r25 to <2 x double>* ; <<2 x double>*> [#uses=2] ; [oox.164 : sln.14]
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store <2 x double> %r23, <2 x double>* %r26, align 16, !nontemporal !0 ; [oox.164 : sln.14]
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%r28 = load <2 x double>* %"$LCS_S2", align 8 ; <<2 x double>> [#uses=1] ; [oox.165 : sln.15]
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%r29 = load i64* %"$LCS_0", align 8 ; <i64> [#uses=1] ; [oox.165 : sln.15]
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%r30 = add i64 3200000, %r29 ; <i64> [#uses=1] ; [oox.165 : sln.15]
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%r31 = inttoptr i64 %r30 to <2 x double>* ; <<2 x double>*> [#uses=2] ; [oox.165 : sln.15]
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store <2 x double> %r28, <2 x double>* %r31, align 16, !nontemporal !0 ; [oox.165 : sln.15]
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%r33 = load i64* %"$SI_S1", align 8 ; <i64> [#uses=1] ; [oox.166 : sln.10]
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%r34 = add i64 16, %r33 ; <i64> [#uses=1] ; [oox.166 : sln.10]
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store i64 %r34, i64* %"$SI_S1", align 8 ; [oox.166 : sln.10]
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%r35 = load i64* %"$LC_S3", align 8 ; <i64> [#uses=1] ; [oox.167 : sln.10]
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%r36 = add i64 1, %r35 ; <i64> [#uses=1] ; [oox.167 : sln.10]
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store i64 %r36, i64* %"$LC_S3", align 8 ; [oox.167 : sln.10]
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%r37 = load i64* %"$LC_S3", align 8 ; <i64> [#uses=1] ; [oox.168 : sln.10]
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%r38 = icmp slt i64 %r37, 0 ; <i1> [#uses=1] ; [oox.168 : sln.10]
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%r39 = zext i1 %r38 to i64 ; <i64> [#uses=1] ; [oox.168 : sln.10]
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%r40 = icmp ne i64 %r39, 0 ; <i1> [#uses=1] ; [oox.168 : sln.10]
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br i1 %r40, label %"file movnt.f90, line 2, in inner vector loop at depth 0, bb25", label %"file movnt.f90, line 18, bb5" ; [oox.168 : sln.10]
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"file movnt.f90, line 18, bb5": ; srcLine 18 ; preds = %"file movnt.f90, line 11, in inner vector loop at depth 0, bb23"
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ret void ; [oox.159 : sln.18]
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}
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