mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-18 12:29:21 +00:00
Added special register class containing (for now) %fsr.
Fixed spilling of %fcc[0-3] which are part of %fsr. Moved some machine-independent reg-class code to class TargetRegInfo from SparcReg{Class,}Info. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6339 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -302,7 +302,7 @@ private :
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void emitMachineInst(const MachineInstr *MI);
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void emitMachineInst(const MachineInstr *MI);
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unsigned int printOperands(const MachineInstr *MI, unsigned int opNum);
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unsigned int printOperands(const MachineInstr *MI, unsigned int opNum);
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void printOneOperand(const MachineOperand &Op);
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void printOneOperand(const MachineOperand &Op, MachineOpCode opCode);
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bool OpIsBranchTargetLabel(const MachineInstr *MI, unsigned int opNum);
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bool OpIsBranchTargetLabel(const MachineInstr *MI, unsigned int opNum);
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bool OpIsMemoryAddressBase(const MachineInstr *MI, unsigned int opNum);
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bool OpIsMemoryAddressBase(const MachineInstr *MI, unsigned int opNum);
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@ -341,10 +341,10 @@ SparcFunctionAsmPrinter::OpIsMemoryAddressBase(const MachineInstr *MI,
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}
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}
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#define PrintOp1PlusOp2(mop1, mop2) \
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#define PrintOp1PlusOp2(mop1, mop2, opCode) \
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printOneOperand(mop1); \
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printOneOperand(mop1, opCode); \
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toAsm << "+"; \
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toAsm << "+"; \
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printOneOperand(mop2);
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printOneOperand(mop2, opCode);
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unsigned int
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unsigned int
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SparcFunctionAsmPrinter::printOperands(const MachineInstr *MI,
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SparcFunctionAsmPrinter::printOperands(const MachineInstr *MI,
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@ -354,26 +354,26 @@ SparcFunctionAsmPrinter::printOperands(const MachineInstr *MI,
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if (OpIsBranchTargetLabel(MI, opNum))
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if (OpIsBranchTargetLabel(MI, opNum))
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{
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{
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PrintOp1PlusOp2(mop, MI->getOperand(opNum+1));
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PrintOp1PlusOp2(mop, MI->getOperand(opNum+1), MI->getOpCode());
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return 2;
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return 2;
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}
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}
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else if (OpIsMemoryAddressBase(MI, opNum))
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else if (OpIsMemoryAddressBase(MI, opNum))
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{
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{
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toAsm << "[";
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toAsm << "[";
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PrintOp1PlusOp2(mop, MI->getOperand(opNum+1));
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PrintOp1PlusOp2(mop, MI->getOperand(opNum+1), MI->getOpCode());
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toAsm << "]";
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toAsm << "]";
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return 2;
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return 2;
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}
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}
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else
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else
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{
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{
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printOneOperand(mop);
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printOneOperand(mop, MI->getOpCode());
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return 1;
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return 1;
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}
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}
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}
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}
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void
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void
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SparcFunctionAsmPrinter::printOneOperand(const MachineOperand &mop)
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SparcFunctionAsmPrinter::printOneOperand(const MachineOperand &mop,
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MachineOpCode opCode)
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{
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{
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bool needBitsFlag = true;
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bool needBitsFlag = true;
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@ -394,13 +394,13 @@ SparcFunctionAsmPrinter::printOneOperand(const MachineOperand &mop)
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case MachineOperand::MO_CCRegister:
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case MachineOperand::MO_CCRegister:
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case MachineOperand::MO_MachineRegister:
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case MachineOperand::MO_MachineRegister:
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{
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{
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int RegNum = (int)mop.getAllocatedRegNum();
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int regNum = (int)mop.getAllocatedRegNum();
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if (regNum == Target.getRegInfo().getInvalidRegNum()) {
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// better to print code with NULL registers than to die
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// better to print code with NULL registers than to die
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if (RegNum == Target.getRegInfo().getInvalidRegNum()) {
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toAsm << "<NULL VALUE>";
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toAsm << "<NULL VALUE>";
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} else {
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} else {
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toAsm << "%" << Target.getRegInfo().getUnifiedRegName(RegNum);
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toAsm << "%" << Target.getRegInfo().getUnifiedRegName(regNum);
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}
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}
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break;
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break;
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}
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}
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@ -1318,8 +1318,8 @@ ForwardOperand(InstructionNode* treeNode,
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for (unsigned i=0,numOps=minstr->getNumImplicitRefs(); i<numOps; ++i)
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for (unsigned i=0,numOps=minstr->getNumImplicitRefs(); i<numOps; ++i)
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if (minstr->getImplicitRef(i) == unusedOp)
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if (minstr->getImplicitRef(i) == unusedOp)
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minstr->setImplicitRef(i, fwdOp,
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minstr->setImplicitRef(i, fwdOp,
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minstr->implicitRefIsDefined(i),
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minstr->getImplicitOp(i).opIsDefOnly(),
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minstr->implicitRefIsDefinedAndUsed(i));
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minstr->getImplicitOp(i).opIsDefAndUse());
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}
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}
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}
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}
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}
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}
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@ -255,7 +255,8 @@ class UltraSparcRegInfo : public TargetRegInfo {
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IntRegClassID, // Integer
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IntRegClassID, // Integer
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FloatRegClassID, // Float (both single/double)
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FloatRegClassID, // Float (both single/double)
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IntCCRegClassID, // Int Condition Code
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IntCCRegClassID, // Int Condition Code
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FloatCCRegClassID // Float Condition code
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FloatCCRegClassID, // Float Condition code
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SpecialRegClassID // Special (unallocated) registers
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};
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};
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@ -268,7 +269,8 @@ class UltraSparcRegInfo : public TargetRegInfo {
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FPSingleRegType,
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FPSingleRegType,
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FPDoubleRegType,
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FPDoubleRegType,
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IntCCRegType,
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IntCCRegType,
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FloatCCRegType
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FloatCCRegType,
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SpecialRegType
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};
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};
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// **** WARNING: If the above enum order is changed, also modify
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// **** WARNING: If the above enum order is changed, also modify
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@ -308,6 +310,9 @@ class UltraSparcRegInfo : public TargetRegInfo {
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std::vector<MachineInstr *>& AddedInstrnsBefore)
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std::vector<MachineInstr *>& AddedInstrnsBefore)
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const;
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const;
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// Get the register type for a register identified different ways.
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// The first function is a helper used by the all the hoter functions.
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int getRegTypeForClassAndType(unsigned regClassID, const Type* type) const;
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int getRegType(const Type* type) const;
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int getRegType(const Type* type) const;
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int getRegType(const LiveRange *LR) const;
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int getRegType(const LiveRange *LR) const;
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int getRegType(int unifiedRegNum) const;
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int getRegType(int unifiedRegNum) const;
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@ -352,7 +357,6 @@ public:
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// To find the register class to which a specified register belongs
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// To find the register class to which a specified register belongs
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//
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//
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unsigned getRegClassIDOfReg(int unifiedRegNum) const;
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unsigned getRegClassIDOfRegType(int regType) const;
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unsigned getRegClassIDOfRegType(int regType) const;
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// getZeroRegNum - returns the register that contains always zero this is the
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// getZeroRegNum - returns the register that contains always zero this is the
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@ -403,55 +407,7 @@ public:
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// method used for printing a register for debugging purposes
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// method used for printing a register for debugging purposes
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//
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//
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static void printReg(const LiveRange *LR);
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void printReg(const LiveRange *LR) const;
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// Each register class has a seperate space for register IDs. To convert
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// a regId in a register class to a common Id, or vice versa,
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// we use the folloing methods.
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//
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// This method provides a unique number for each register
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inline int getUnifiedRegNum(unsigned regClassID, int reg) const {
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if (regClassID == IntRegClassID) {
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assert(reg < 32 && "Invalid reg. number");
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return reg;
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}
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else if (regClassID == FloatRegClassID) {
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assert(reg < 64 && "Invalid reg. number");
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return reg + 32; // we have 32 int regs
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}
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else if (regClassID == FloatCCRegClassID) {
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assert(reg < 4 && "Invalid reg. number");
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return reg + 32 + 64; // 32 int, 64 float
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}
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else if (regClassID == IntCCRegClassID ) {
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assert(reg == 0 && "Invalid reg. number");
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return reg + 4+ 32 + 64; // only one int CC reg
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}
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else if (reg==InvalidRegNum) {
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return InvalidRegNum;
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}
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else
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assert(0 && "Invalid register class");
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return 0;
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}
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// This method converts the unified number to the number in its class,
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// and returns the class ID in regClassID.
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inline int getClassRegNum(int ureg, unsigned& regClassID) const {
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if (ureg < 32) { regClassID = IntRegClassID; return ureg; }
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else if (ureg < 32+64) { regClassID = FloatRegClassID; return ureg-32; }
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else if (ureg < 4 +96) { regClassID = FloatCCRegClassID; return ureg-96; }
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else if (ureg < 1 +100) { regClassID = IntCCRegClassID; return ureg-100;}
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else if (ureg == InvalidRegNum) { return InvalidRegNum; }
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else { assert(0 && "Invalid unified register number"); }
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return 0;
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}
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// Returns the assembly-language name of the specified machine register.
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//
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virtual const char * const getUnifiedRegName(int reg) const;
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// returns the # of bytes of stack space allocated for each register
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// returns the # of bytes of stack space allocated for each register
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// type. For Sparc, currently we allocate 8 bytes on stack for all
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// type. For Sparc, currently we allocate 8 bytes on stack for all
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@ -63,7 +63,7 @@ struct SparcIntRegClass : public TargetRegClassInfo {
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StartOfAllRegs = o0,
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StartOfAllRegs = o0,
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};
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};
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static const char * const getRegName(unsigned reg);
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const char * const getRegName(unsigned reg) const;
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};
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};
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@ -104,7 +104,7 @@ public:
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StartOfAllRegs = f0,
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StartOfAllRegs = f0,
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};
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};
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static const char * const getRegName(unsigned reg);
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const char * const getRegName(unsigned reg) const;
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};
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};
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@ -138,7 +138,7 @@ struct SparcIntCCRegClass : public TargetRegClassInfo {
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xcc, ccr // only one is available - see the note above
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xcc, ccr // only one is available - see the note above
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};
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};
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static const char * const getRegName(unsigned reg);
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const char * const getRegName(unsigned reg) const;
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};
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};
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@ -146,12 +146,12 @@ struct SparcIntCCRegClass : public TargetRegClassInfo {
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Float CC Register Class
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// Float CC Register Class
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// Only 4 Float CC registers are available
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// Only 4 Float CC registers are available for allocation.
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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struct SparcFloatCCRegClass : public TargetRegClassInfo {
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struct SparcFloatCCRegClass : public TargetRegClassInfo {
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SparcFloatCCRegClass(unsigned ID)
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SparcFloatCCRegClass(unsigned ID)
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: TargetRegClassInfo(ID, 4, 4) { }
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: TargetRegClassInfo(ID, 4, 5) { }
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void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const {
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void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const {
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for(unsigned c = 0; c != 4; ++c)
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for(unsigned c = 0; c != 4; ++c)
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@ -168,10 +168,33 @@ struct SparcFloatCCRegClass : public TargetRegClassInfo {
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inline bool isRegVolatile(int Reg) const { return true; }
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inline bool isRegVolatile(int Reg) const { return true; }
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enum {
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enum {
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fcc0, fcc1, fcc2, fcc3
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fcc0, fcc1, fcc2, fcc3, fsr // fsr is not used in allocation
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}; // but has a name in getRegName()
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const char * const getRegName(unsigned reg) const;
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};
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//-----------------------------------------------------------------------------
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// Sparc special register class. These registers are not used for allocation
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// but are used as arguments of some instructions.
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//-----------------------------------------------------------------------------
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struct SparcSpecialRegClass : public TargetRegClassInfo {
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SparcSpecialRegClass(unsigned ID)
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: TargetRegClassInfo(ID, 0, 1) { }
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void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const {
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assert(0 && "SparcSpecialRegClass should never be used for allocation");
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}
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// all currently included special regs are volatile
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inline bool isRegVolatile(int Reg) const { return true; }
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enum {
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fsr // floating point state register
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};
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};
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static const char * const getRegName(unsigned reg);
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const char * const getRegName(unsigned reg) const;
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};
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};
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#endif
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#endif
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@ -32,6 +32,7 @@ UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
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MachineRegClassArr.push_back(new SparcFloatRegClass(FloatRegClassID));
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MachineRegClassArr.push_back(new SparcFloatRegClass(FloatRegClassID));
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MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID));
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MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID));
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MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID));
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MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID));
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MachineRegClassArr.push_back(new SparcSpecialRegClass(SpecialRegClassID));
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assert(SparcFloatRegClass::StartOfNonVolatileRegs == 32 &&
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assert(SparcFloatRegClass::StartOfNonVolatileRegs == 32 &&
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"32 Float regs are used for float arg passing");
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"32 Float regs are used for float arg passing");
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@ -75,7 +76,7 @@ static const char * const IntRegNames[] = {
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"o6"
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"o6"
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};
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};
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const char * const SparcIntRegClass::getRegName(unsigned reg) {
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const char * const SparcIntRegClass::getRegName(unsigned reg) const {
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assert(reg < NumOfAllRegs);
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assert(reg < NumOfAllRegs);
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return IntRegNames[reg];
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return IntRegNames[reg];
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}
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}
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@ -90,7 +91,7 @@ static const char * const FloatRegNames[] = {
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"f60", "f61", "f62", "f63"
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"f60", "f61", "f62", "f63"
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};
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};
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const char * const SparcFloatRegClass::getRegName(unsigned reg) {
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const char * const SparcFloatRegClass::getRegName(unsigned reg) const {
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assert (reg < NumOfAllRegs);
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assert (reg < NumOfAllRegs);
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return FloatRegNames[reg];
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return FloatRegNames[reg];
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}
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}
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@ -100,7 +101,7 @@ static const char * const IntCCRegNames[] = {
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"xcc", "ccr"
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"xcc", "ccr"
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};
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};
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const char * const SparcIntCCRegClass::getRegName(unsigned reg) {
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const char * const SparcIntCCRegClass::getRegName(unsigned reg) const {
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assert(reg < 2);
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assert(reg < 2);
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return IntCCRegNames[reg];
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return IntCCRegNames[reg];
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}
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}
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@ -109,28 +110,18 @@ static const char * const FloatCCRegNames[] = {
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"fcc0", "fcc1", "fcc2", "fcc3"
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"fcc0", "fcc1", "fcc2", "fcc3"
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};
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};
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const char * const SparcFloatCCRegClass::getRegName(unsigned reg) {
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const char * const SparcFloatCCRegClass::getRegName(unsigned reg) const {
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assert (reg < 4);
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assert (reg < 5);
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return FloatCCRegNames[reg];
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return FloatCCRegNames[reg];
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}
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}
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// given the unified register number, this gives the name
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static const char * const SpecialRegNames[] = {
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// for generating assembly code or debugging.
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"fsr"
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//
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};
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const char * const UltraSparcRegInfo::getUnifiedRegName(int reg) const {
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if( reg < 32 )
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const char * const SparcSpecialRegClass::getRegName(unsigned reg) const {
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return SparcIntRegClass::getRegName(reg);
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assert (reg < 1);
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else if ( reg < (64 + 32) )
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return SpecialRegNames[reg];
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return SparcFloatRegClass::getRegName( reg - 32);
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else if( reg < (64+32+4) )
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return SparcFloatCCRegClass::getRegName( reg -32 - 64);
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else if( reg < (64+32+4+2) ) // two names: %xcc and %ccr
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return SparcIntCCRegClass::getRegName( reg -32 - 64 - 4);
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else if (reg== InvalidRegNum) //****** TODO: Remove */
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return "<*NoReg*>";
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else
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assert(0 && "Invalid register number");
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return "";
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}
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}
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// Get unified reg number for frame pointer
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// Get unified reg number for frame pointer
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@ -230,43 +221,34 @@ UltraSparcRegInfo::regNumForFPArg(unsigned regType,
|
|||||||
// The following 4 methods are used to find the RegType (SparcInternals.h)
|
// The following 4 methods are used to find the RegType (SparcInternals.h)
|
||||||
// of a LiveRange, a Value, and for a given register unified reg number.
|
// of a LiveRange, a Value, and for a given register unified reg number.
|
||||||
//
|
//
|
||||||
int UltraSparcRegInfo::getRegType(const Type* type) const {
|
int UltraSparcRegInfo::getRegTypeForClassAndType(unsigned regClassID,
|
||||||
unsigned regClassID = getRegClassIDOfType(type);
|
const Type* type) const
|
||||||
|
{
|
||||||
switch (regClassID) {
|
switch (regClassID) {
|
||||||
case IntRegClassID: return IntRegType;
|
case IntRegClassID: return IntRegType;
|
||||||
case FloatRegClassID: {
|
case FloatRegClassID:
|
||||||
if (type == Type::FloatTy)
|
if (type == Type::FloatTy) return FPSingleRegType;
|
||||||
return FPSingleRegType;
|
else if (type == Type::DoubleTy) return FPDoubleRegType;
|
||||||
else if (type == Type::DoubleTy)
|
assert(0 && "Unknown type in FloatRegClass"); return 0;
|
||||||
return FPDoubleRegType;
|
|
||||||
assert(0 && "Unknown type in FloatRegClass");
|
|
||||||
}
|
|
||||||
case IntCCRegClassID: return IntCCRegType;
|
case IntCCRegClassID: return IntCCRegType;
|
||||||
case FloatCCRegClassID: return FloatCCRegType;
|
case FloatCCRegClassID: return FloatCCRegType;
|
||||||
|
case SpecialRegClassID: return SpecialRegType;
|
||||||
default: assert( 0 && "Unknown reg class ID"); return 0;
|
default: assert( 0 && "Unknown reg class ID"); return 0;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
int UltraSparcRegInfo::getRegType(const LiveRange *LR) const {
|
int UltraSparcRegInfo::getRegType(const Type* type) const
|
||||||
const Type* type = LR->getType();
|
{
|
||||||
|
return getRegTypeForClassAndType(getRegClassIDOfType(type), type);
|
||||||
unsigned regClassID = LR->getRegClassID();
|
|
||||||
switch (regClassID) {
|
|
||||||
default: assert( 0 && "Unknown reg class ID");
|
|
||||||
case IntRegClassID: return IntRegType;
|
|
||||||
case FloatRegClassID:
|
|
||||||
if (type == Type::FloatTy)
|
|
||||||
return FPSingleRegType;
|
|
||||||
else if (type == Type::DoubleTy)
|
|
||||||
return FPDoubleRegType;
|
|
||||||
assert(0 && "Unknown type in FloatRegClass");
|
|
||||||
case IntCCRegClassID: return IntCCRegType;
|
|
||||||
case FloatCCRegClassID: return FloatCCRegType;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
int UltraSparcRegInfo::getRegType(const LiveRange *LR) const
|
||||||
|
{
|
||||||
|
return getRegTypeForClassAndType(LR->getRegClassID(), LR->getType());
|
||||||
|
}
|
||||||
|
|
||||||
int UltraSparcRegInfo::getRegType(int unifiedRegNum) const {
|
int UltraSparcRegInfo::getRegType(int unifiedRegNum) const
|
||||||
|
{
|
||||||
if (unifiedRegNum < 32)
|
if (unifiedRegNum < 32)
|
||||||
return IntRegType;
|
return IntRegType;
|
||||||
else if (unifiedRegNum < (32 + 32))
|
else if (unifiedRegNum < (32 + 32))
|
||||||
@ -308,14 +290,6 @@ unsigned UltraSparcRegInfo::getRegClassIDOfType(const Type *type,
|
|||||||
return res;
|
return res;
|
||||||
}
|
}
|
||||||
|
|
||||||
// To find the register class to which a specified register belongs
|
|
||||||
//
|
|
||||||
unsigned UltraSparcRegInfo::getRegClassIDOfReg(int unifiedRegNum) const {
|
|
||||||
unsigned classId = 0;
|
|
||||||
(void) getClassRegNum(unifiedRegNum, classId);
|
|
||||||
return classId;
|
|
||||||
}
|
|
||||||
|
|
||||||
unsigned UltraSparcRegInfo::getRegClassIDOfRegType(int regType) const {
|
unsigned UltraSparcRegInfo::getRegClassIDOfRegType(int regType) const {
|
||||||
switch(regType) {
|
switch(regType) {
|
||||||
case IntRegType: return IntRegClassID;
|
case IntRegType: return IntRegClassID;
|
||||||
@ -1183,13 +1157,14 @@ UltraSparcRegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
|
|||||||
cpReg2MemMI(mvec, scratchReg, DestPtrReg, Offset, IntRegType);
|
cpReg2MemMI(mvec, scratchReg, DestPtrReg, Offset, IntRegType);
|
||||||
return;
|
return;
|
||||||
|
|
||||||
case FloatCCRegType:
|
case FloatCCRegType: {
|
||||||
assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here");
|
|
||||||
assert(target.getInstrInfo().constantFitsInImmedField(V9::STXFSR, Offset));
|
assert(target.getInstrInfo().constantFitsInImmedField(V9::STXFSR, Offset));
|
||||||
MI = BuildMI(V9::STXFSR, 3).addMReg(SrcReg).addMReg(DestPtrReg)
|
unsigned fsrRegNum = getUnifiedRegNum(UltraSparcRegInfo::SpecialRegClassID,
|
||||||
.addSImm(Offset);
|
SparcSpecialRegClass::fsr);
|
||||||
|
MI = BuildMI(V9::STXFSR, 3)
|
||||||
|
.addMReg(fsrRegNum).addMReg(DestPtrReg).addSImm(Offset);
|
||||||
break;
|
break;
|
||||||
|
}
|
||||||
default:
|
default:
|
||||||
assert(0 && "Unknown RegType in cpReg2MemMI");
|
assert(0 && "Unknown RegType in cpReg2MemMI");
|
||||||
}
|
}
|
||||||
@ -1239,14 +1214,14 @@ UltraSparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
|
|||||||
MI = BuildMI(V9::WRCCR, 2).addMReg(scratchReg).addMReg(DestReg+1,MOTy::Def);
|
MI = BuildMI(V9::WRCCR, 2).addMReg(scratchReg).addMReg(DestReg+1,MOTy::Def);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case FloatCCRegType:
|
case FloatCCRegType: {
|
||||||
assert(0 && "Tell Vikram if this assertion fails: we may have to mask "
|
|
||||||
"out the other bits here");
|
|
||||||
assert(target.getInstrInfo().constantFitsInImmedField(V9::LDXFSR, Offset));
|
assert(target.getInstrInfo().constantFitsInImmedField(V9::LDXFSR, Offset));
|
||||||
|
unsigned fsrRegNum = getUnifiedRegNum(UltraSparcRegInfo::SpecialRegClassID,
|
||||||
|
SparcSpecialRegClass::fsr);
|
||||||
MI = BuildMI(V9::LDXFSR, 3).addMReg(SrcPtrReg).addSImm(Offset)
|
MI = BuildMI(V9::LDXFSR, 3).addMReg(SrcPtrReg).addSImm(Offset)
|
||||||
.addMReg(DestReg, MOTy::Def);
|
.addMReg(fsrRegNum, MOTy::UseAndDef);
|
||||||
break;
|
break;
|
||||||
|
}
|
||||||
default:
|
default:
|
||||||
assert(0 && "Unknown RegType in cpMem2RegMI");
|
assert(0 && "Unknown RegType in cpMem2RegMI");
|
||||||
}
|
}
|
||||||
@ -1462,7 +1437,7 @@ UltraSparcRegInfo::insertCallerSavingCode
|
|||||||
// Print the register assigned to a LR
|
// Print the register assigned to a LR
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
void UltraSparcRegInfo::printReg(const LiveRange *LR) {
|
void UltraSparcRegInfo::printReg(const LiveRange *LR) const {
|
||||||
unsigned RegClassID = LR->getRegClassID();
|
unsigned RegClassID = LR->getRegClassID();
|
||||||
std::cerr << " *Node " << (LR->getUserIGNode())->getIndex();
|
std::cerr << " *Node " << (LR->getUserIGNode())->getIndex();
|
||||||
|
|
||||||
@ -1475,15 +1450,13 @@ void UltraSparcRegInfo::printReg(const LiveRange *LR) {
|
|||||||
|
|
||||||
std::cerr << " colored with color "<< LR->getColor();
|
std::cerr << " colored with color "<< LR->getColor();
|
||||||
|
|
||||||
if (RegClassID == IntRegClassID) {
|
unsigned uRegName = getUnifiedRegNum(RegClassID, LR->getColor());
|
||||||
std::cerr<< " [" << SparcIntRegClass::getRegName(LR->getColor()) << "]\n";
|
|
||||||
|
|
||||||
} else if (RegClassID == FloatRegClassID) {
|
std::cerr << "[";
|
||||||
std::cerr << "[" << SparcFloatRegClass::getRegName(LR->getColor());
|
std::cerr<< getUnifiedRegName(uRegName);
|
||||||
if( LR->getType() == Type::DoubleTy)
|
if (RegClassID == FloatRegClassID && LR->getType() == Type::DoubleTy)
|
||||||
std::cerr << "+" << SparcFloatRegClass::getRegName(LR->getColor()+1);
|
std::cerr << "+" << getUnifiedRegName(uRegName+1);
|
||||||
std::cerr << "]\n";
|
std::cerr << "]\n";
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
@ -1559,7 +1532,7 @@ void UltraSparcRegInfo::OrderAddedInstrns(std::vector<MachineInstr*> &UnordVec,
|
|||||||
// last operand is the def (unless for a store which has no def reg)
|
// last operand is the def (unless for a store which has no def reg)
|
||||||
MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1);
|
MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1);
|
||||||
|
|
||||||
if (DefOp.opIsDef() &&
|
if ((DefOp.opIsDefOnly() || DefOp.opIsDefAndUse()) &&
|
||||||
DefOp.getType() == MachineOperand::MO_MachineRegister) {
|
DefOp.getType() == MachineOperand::MO_MachineRegister) {
|
||||||
|
|
||||||
// If the operand in DefInst is a def ...
|
// If the operand in DefInst is a def ...
|
||||||
@ -1576,7 +1549,7 @@ void UltraSparcRegInfo::OrderAddedInstrns(std::vector<MachineInstr*> &UnordVec,
|
|||||||
// for each inst (UseInst) that is below the DefInst do ...
|
// for each inst (UseInst) that is below the DefInst do ...
|
||||||
MachineOperand& UseOp = UseInst->getOperand(0);
|
MachineOperand& UseOp = UseInst->getOperand(0);
|
||||||
|
|
||||||
if (!UseOp.opIsDef() &&
|
if (!UseOp.opIsDefOnly() &&
|
||||||
UseOp.getType() == MachineOperand::MO_MachineRegister) {
|
UseOp.getType() == MachineOperand::MO_MachineRegister) {
|
||||||
|
|
||||||
// if use is a register ...
|
// if use is a register ...
|
||||||
@ -1637,7 +1610,7 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr*> &OrdVec,
|
|||||||
PhyRegAlloc &PRA) const {
|
PhyRegAlloc &PRA) const {
|
||||||
MachineOperand& UseOp = UnordInst->getOperand(0);
|
MachineOperand& UseOp = UnordInst->getOperand(0);
|
||||||
|
|
||||||
if (!UseOp.opIsDef() &&
|
if (!UseOp.opIsDefOnly() &&
|
||||||
UseOp.getType() == MachineOperand::MO_MachineRegister) {
|
UseOp.getType() == MachineOperand::MO_MachineRegister) {
|
||||||
|
|
||||||
// for the use of UnordInst, see whether there is a defining instr
|
// for the use of UnordInst, see whether there is a defining instr
|
||||||
@ -1653,7 +1626,7 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr*> &OrdVec,
|
|||||||
MachineOperand& DefOp =
|
MachineOperand& DefOp =
|
||||||
OrdInst->getOperand(OrdInst->getNumOperands()-1);
|
OrdInst->getOperand(OrdInst->getNumOperands()-1);
|
||||||
|
|
||||||
if( DefOp.opIsDef() &&
|
if( (DefOp.opIsDefOnly() || DefOp.opIsDefAndUse()) &&
|
||||||
DefOp.getType() == MachineOperand::MO_MachineRegister) {
|
DefOp.getType() == MachineOperand::MO_MachineRegister) {
|
||||||
|
|
||||||
//std::cerr << "\nDefining Ord Inst: " << *OrdInst;
|
//std::cerr << "\nDefining Ord Inst: " << *OrdInst;
|
||||||
@ -1686,7 +1659,8 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr*> &OrdVec,
|
|||||||
// Load directly into DReg (%oy)
|
// Load directly into DReg (%oy)
|
||||||
MachineOperand& DOp=
|
MachineOperand& DOp=
|
||||||
(UnordInst->getOperand(UnordInst->getNumOperands()-1));
|
(UnordInst->getOperand(UnordInst->getNumOperands()-1));
|
||||||
assert(DOp.opIsDef() && "Last operand is not the def");
|
assert((DOp.opIsDefOnly() || DefOp.opIsDefAndUse()) &&
|
||||||
|
"Last operand is not the def");
|
||||||
const int DReg = DOp.getMachineRegNum();
|
const int DReg = DOp.getMachineRegNum();
|
||||||
|
|
||||||
cpMem2RegMI(OrdVec, getFramePointer(), StackOff, DReg, RegType);
|
cpMem2RegMI(OrdVec, getFramePointer(), StackOff, DReg, RegType);
|
||||||
|
Loading…
Reference in New Issue
Block a user