Vikram S. Adve 78a4f23a8e Added special register class containing (for now) %fsr.
Fixed spilling of %fcc[0-3] which are part of %fsr.
Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6339 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 00:02:22 +00:00
2003-05-26 23:41:13 +00:00
2003-05-25 16:52:41 +00:00
2003-05-25 16:52:41 +00:00
Description
LLVM backend for 6502
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