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https://github.com/c64scene-ar/llvm-6502.git
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Integer comparison tests for CellSPU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48152 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Scott Michel
parent
08bfe26f5a
commit
78c47fa50b
@ -41,14 +41,14 @@ namespace {
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bool
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isI64IntS10Immediate(ConstantSDNode *CN)
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{
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return isS10Constant(CN->getValue());
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return isS10Constant(CN->getSignExtended());
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}
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//! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
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bool
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isI32IntS10Immediate(ConstantSDNode *CN)
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{
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return isS10Constant((int) CN->getValue());
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return isS10Constant(CN->getSignExtended());
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}
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#if 0
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@ -244,21 +244,21 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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setOperationAction(ISD::CTLZ , MVT::i32, Legal);
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// SPU has a version of select
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setOperationAction(ISD::SELECT, MVT::i1, Expand);
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setOperationAction(ISD::SELECT, MVT::i8, Expand);
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setOperationAction(ISD::SELECT, MVT::i1, Promote);
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setOperationAction(ISD::SELECT, MVT::i8, Legal);
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setOperationAction(ISD::SELECT, MVT::i16, Legal);
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setOperationAction(ISD::SELECT, MVT::i32, Legal);
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setOperationAction(ISD::SELECT, MVT::i64, Expand);
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setOperationAction(ISD::SELECT, MVT::f32, Expand);
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setOperationAction(ISD::SELECT, MVT::f64, Expand);
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setOperationAction(ISD::SETCC, MVT::i1, Expand);
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setOperationAction(ISD::SETCC, MVT::i8, Expand);
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setOperationAction(ISD::SETCC, MVT::i16, Legal);
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setOperationAction(ISD::SETCC, MVT::i32, Legal);
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setOperationAction(ISD::SETCC, MVT::i64, Expand);
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setOperationAction(ISD::SETCC, MVT::f32, Expand);
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setOperationAction(ISD::SETCC, MVT::f64, Expand);
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setOperationAction(ISD::SETCC, MVT::i1, Promote);
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setOperationAction(ISD::SETCC, MVT::i8, Legal);
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setOperationAction(ISD::SETCC, MVT::i16, Legal);
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setOperationAction(ISD::SETCC, MVT::i32, Legal);
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setOperationAction(ISD::SETCC, MVT::i64, Expand);
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setOperationAction(ISD::SETCC, MVT::f32, Expand);
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setOperationAction(ISD::SETCC, MVT::f64, Expand);
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// Zero extension and sign extension for i64 have to be
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// custom legalized
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@ -380,7 +380,6 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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setOperationAction(ISD::XOR, MVT::v16i8, Custom);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
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setSetCCResultType(MVT::i32);
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setShiftAmountType(MVT::i32);
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setSetCCResultContents(ZeroOrOneSetCCResult);
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@ -449,6 +448,11 @@ SPUTargetLowering::getTargetNodeName(unsigned Opcode) const
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return ((i != node_names.end()) ? i->second : 0);
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}
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MVT::ValueType
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SPUTargetLowering::getSetCCResultType(const SDOperand &Op) const {
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return Op.getValueType();
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}
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//===----------------------------------------------------------------------===//
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// Calling convention code:
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//===----------------------------------------------------------------------===//
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@ -104,7 +104,7 @@ namespace llvm {
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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/// getSetCCResultType - Return the ValueType for ISD::SETCC
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MVT::ValueType getSetCCResultType(const SDOperand &) const;
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virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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@ -1392,7 +1392,7 @@ def XORHIr16:
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[(set R16C:$rT, (xor R16C:$rA, i16ImmSExt10:$val))]>;
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def XORIv4i32:
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RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
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RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm_i32:$val),
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"xori\t$rT, $rA, $val", IntegerOp,
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[(set (v4i32 VECREG:$rT), (xor (v4i32 VECREG:$rA),
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v4i32SExt10Imm:$val))]>;
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@ -1515,7 +1515,7 @@ def : SPUselbPat<v2i64, SELBv2i64>;
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class SelectConditional<RegisterClass rclass, SPUInstr inst>:
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Pat<(select rclass:$rCond, rclass:$rTrue, rclass:$rFalse),
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(inst rclass:$rCond, rclass:$rFalse, rclass:$rTrue)>;
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(inst rclass:$rFalse, rclass:$rTrue, rclass:$rCond)>;
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def : SelectConditional<R32C, SELBr32>;
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def : SelectConditional<R16C, SELBr16>;
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@ -2875,12 +2875,33 @@ defm CLGTHI : CmpLGtrHalfwordImm;
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defm CLGT : CmpLGtrWord;
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defm CLGTI : CmpLGtrWordImm;
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// For SETCC primitives not supported above (setlt, setle, setge, etc.)
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// define a pattern to generate the right code, as a binary operator
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// (in a manner of speaking.)
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//
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// N.B.: This only matches the setcc set of conditionals. Special pattern
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// matching is used for select conditionals.
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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class SETCCNegCond<PatFrag cond, RegisterClass rclass, dag pattern>:
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Pat<(cond rclass:$rA, rclass:$rB), pattern>;
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class SETCCNegCondReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
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SPUInstr xorinst, SPUInstr cmpare>:
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Pat<(cond rclass:$rA, rclass:$rB),
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(xorinst (cmpare rclass:$rA, rclass:$rB), (inttype -1))>;
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class SETCCNegCondImm<PatFrag cond, RegisterClass rclass, ValueType inttype,
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PatLeaf immpred, SPUInstr xorinst, SPUInstr cmpare>:
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Pat<(cond rclass:$rA, (inttype immpred:$imm)),
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(xorinst (cmpare rclass:$rA, (inttype immpred:$imm)), (inttype -1))>;
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def : SETCCNegCondReg<setne, R8C, i8, XORBIr8, CEQBr8>;
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def : SETCCNegCondImm<setne, R8C, i8, immSExt8, XORBIr8, CEQBIr8>;
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def : SETCCNegCondReg<setne, R16C, i16, XORHIr16, CEQHr16>;
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def : SETCCNegCondImm<setne, R16C, i16, i16ImmSExt10, XORHIr16, CEQHIr16>;
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def : SETCCNegCondReg<setne, R32C, i32, XORIr32, CEQr32>;
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def : SETCCNegCondImm<setne, R32C, i32, i32ImmSExt10, XORIr32, CEQIr32>;
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class SETCCBinOpReg<PatFrag cond, RegisterClass rclass,
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SPUInstr binop, SPUInstr cmpOp1, SPUInstr cmpOp2>:
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@ -2895,64 +2916,146 @@ class SETCCBinOpImm<PatFrag cond, RegisterClass rclass, PatLeaf immpred,
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(binop (cmpOp1 rclass:$rA, (immtype immpred:$imm)),
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(cmpOp2 rclass:$rA, (immtype immpred:$imm)))>;
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def CGTEQBr8: SETCCBinOpReg<setge, R8C, ORr8, CGTBr8, CEQBr8>;
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def CGTEQBIr8: SETCCBinOpImm<setge, R8C, immSExt8, i8, ORr8, CGTBIr8, CEQBIr8>;
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def CLTBr8: SETCCBinOpReg<setlt, R8C, NORr8, CGTBr8, CEQBr8>;
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def CLTBIr8: SETCCBinOpImm<setlt, R8C, immSExt8, i8, NORr8, CGTBIr8, CEQBIr8>;
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def CLTEQr8: Pat<(setle R8C:$rA, R8C:$rB),
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(XORBIr8 (CGTBr8 R8C:$rA, R8C:$rB), 0xff)>;
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def CLTEQIr8: Pat<(setle R8C:$rA, immU8:$imm),
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(XORBIr8 (CGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
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def : SETCCBinOpReg<setge, R8C, ORr8, CGTBr8, CEQBr8>;
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def : SETCCBinOpImm<setge, R8C, immSExt8, i8, ORr8, CGTBIr8, CEQBIr8>;
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def : SETCCBinOpReg<setlt, R8C, NORr8, CGTBr8, CEQBr8>;
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def : SETCCBinOpImm<setlt, R8C, immSExt8, i8, NORr8, CGTBIr8, CEQBIr8>;
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def : Pat<(setle R8C:$rA, R8C:$rB),
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(XORBIr8 (CGTBr8 R8C:$rA, R8C:$rB), 0xff)>;
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def : Pat<(setle R8C:$rA, immU8:$imm),
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(XORBIr8 (CGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
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def CGTEQHr16: SETCCBinOpReg<setge, R16C, ORr16, CGTHr16, CEQHr16>;
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def CGTEQHIr16: SETCCBinOpImm<setge, R16C, i16ImmUns10, i16,
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ORr16, CGTHIr16, CEQHIr16>;
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def CLTHr16: SETCCBinOpReg<setlt, R16C, NORr16, CGTHr16, CEQHr16>;
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def CLTHIr16: SETCCBinOpImm<setlt, R16C, i16ImmSExt10, i16, NORr16, CGTHIr16, CEQHIr16>;
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def CLTEQr16: Pat<(setle R16C:$rA, R16C:$rB),
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(XORHIr16 (CGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
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def CLTEQIr16: Pat<(setle R16C:$rA, i16ImmSExt10:$imm),
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(XORHIr16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
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def : SETCCBinOpReg<setge, R16C, ORr16, CGTHr16, CEQHr16>;
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def : SETCCBinOpImm<setge, R16C, i16ImmSExt10, i16,
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ORr16, CGTHIr16, CEQHIr16>;
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def : SETCCBinOpReg<setlt, R16C, NORr16, CGTHr16, CEQHr16>;
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def : SETCCBinOpImm<setlt, R16C, i16ImmSExt10, i16, NORr16, CGTHIr16, CEQHIr16>;
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def : Pat<(setle R16C:$rA, R16C:$rB),
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(XORHIr16 (CGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
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def : Pat<(setle R16C:$rA, i16ImmSExt10:$imm),
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(XORHIr16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
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def CGTEQHr32: SETCCBinOpReg<setge, R32C, ORr32, CGTr32, CEQr32>;
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def CGTEQHIr32: SETCCBinOpImm<setge, R32C, i32ImmSExt10, i32,
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ORr32, CGTIr32, CEQIr32>;
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def CLTr32: SETCCBinOpReg<setlt, R32C, NORr32, CGTr32, CEQr32>;
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def CLTIr32: SETCCBinOpImm<setlt, R32C, i32ImmSExt10, i32, NORr32, CGTIr32, CEQIr32>;
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def CLTEQr32: Pat<(setle R32C:$rA, R32C:$rB),
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(XORIr32 (CGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
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def CLTEQIr32: Pat<(setle R32C:$rA, i32ImmSExt10:$imm),
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(XORIr32 (CGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
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def : SETCCBinOpReg<setge, R32C, ORr32, CGTr32, CEQr32>;
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def : SETCCBinOpImm<setge, R32C, i32ImmSExt10, i32,
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ORr32, CGTIr32, CEQIr32>;
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def : SETCCBinOpReg<setlt, R32C, NORr32, CGTr32, CEQr32>;
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def : SETCCBinOpImm<setlt, R32C, i32ImmSExt10, i32, NORr32, CGTIr32, CEQIr32>;
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def : Pat<(setle R32C:$rA, R32C:$rB),
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(XORIr32 (CGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
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def : Pat<(setle R32C:$rA, i32ImmSExt10:$imm),
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(XORIr32 (CGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
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def CLGTEQBr8: SETCCBinOpReg<setuge, R8C, ORr8, CLGTBr8, CEQBr8>;
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def CLGTEQBIr8: SETCCBinOpImm<setuge, R8C, immSExt8, i8, ORr8, CLGTBIr8, CEQBIr8>;
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def CLLTBr8: SETCCBinOpReg<setult, R8C, NORr8, CLGTBr8, CEQBr8>;
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def CLLTBIr8: SETCCBinOpImm<setult, R8C, immSExt8, i8, NORr8, CLGTBIr8, CEQBIr8>;
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def CLLTEQr8: Pat<(setule R8C:$rA, R8C:$rB),
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(XORBIr8 (CLGTBr8 R8C:$rA, R8C:$rB), 0xff)>;
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def CLLTEQIr8: Pat<(setule R8C:$rA, immU8:$imm),
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(XORBIr8 (CLGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
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def : SETCCBinOpReg<setuge, R8C, ORr8, CLGTBr8, CEQBr8>;
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def : SETCCBinOpImm<setuge, R8C, immSExt8, i8, ORr8, CLGTBIr8, CEQBIr8>;
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def : SETCCBinOpReg<setult, R8C, NORr8, CLGTBr8, CEQBr8>;
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def : SETCCBinOpImm<setult, R8C, immSExt8, i8, NORr8, CLGTBIr8, CEQBIr8>;
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def : Pat<(setule R8C:$rA, R8C:$rB),
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(XORBIr8 (CLGTBr8 R8C:$rA, R8C:$rB), 0xff)>;
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def : Pat<(setule R8C:$rA, immU8:$imm),
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(XORBIr8 (CLGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
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def CLGTEQHr16: SETCCBinOpReg<setuge, R16C, ORr16, CLGTHr16, CEQHr16>;
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def CLGTEQHIr16: SETCCBinOpImm<setuge, R16C, i16ImmUns10, i16,
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ORr16, CLGTHIr16, CEQHIr16>;
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def CLLTHr16: SETCCBinOpReg<setult, R16C, NORr16, CLGTHr16, CEQHr16>;
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def CLLTHIr16: SETCCBinOpImm<setult, R16C, immSExt8, i16, NORr16, CLGTHIr16, CEQHIr16>;
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def CLLTEQr16: Pat<(setule R16C:$rA, R16C:$rB),
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(XORHIr16 (CLGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
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def CLLTEQIr16: Pat<(setule R16C:$rA, i16ImmUns10:$imm),
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(XORHIr16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
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def : SETCCBinOpReg<setuge, R16C, ORr16, CLGTHr16, CEQHr16>;
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def : SETCCBinOpImm<setuge, R16C, i16ImmSExt10, i16,
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ORr16, CLGTHIr16, CEQHIr16>;
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def : SETCCBinOpReg<setult, R16C, NORr16, CLGTHr16, CEQHr16>;
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def : SETCCBinOpImm<setult, R16C, i16ImmSExt10, i16, NORr16,
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CLGTHIr16, CEQHIr16>;
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def : Pat<(setule R16C:$rA, R16C:$rB),
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(XORHIr16 (CLGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
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def : Pat<(setule R16C:$rA, i16ImmUns10:$imm),
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(XORHIr16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
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def : SETCCBinOpReg<setuge, R32C, ORr32, CLGTr32, CEQr32>;
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def : SETCCBinOpImm<setuge, R32C, i32ImmUns10, i32,
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ORr32, CLGTIr32, CEQIr32>;
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def : SETCCBinOpReg<setult, R32C, NORr32, CLGTr32, CEQr32>;
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def : SETCCBinOpImm<setult, R32C, immSExt8, i32, NORr32, CLGTIr32, CEQIr32>;
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def : Pat<(setule R32C:$rA, R32C:$rB),
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(XORIr32 (CLGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
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def : Pat<(setule R32C:$rA, i32ImmSExt10:$imm),
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(XORIr32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
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def CLGTEQHr32: SETCCBinOpReg<setuge, R32C, ORr32, CLGTr32, CEQr32>;
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def CLGTEQHIr32: SETCCBinOpImm<setuge, R32C, i32ImmUns10, i32,
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ORr32, CLGTIr32, CEQIr32>;
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def CLLTr32: SETCCBinOpReg<setult, R32C, NORr32, CLGTr32, CEQr32>;
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def CLLTIr32: SETCCBinOpImm<setult, R32C, immSExt8, i32, NORr32, CLGTIr32, CEQIr32>;
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def CLLTEQr32: Pat<(setule R32C:$rA, R32C:$rB),
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(XORIr32 (CLGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
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def CLLTEQIr32: Pat<(setule R32C:$rA, i32ImmSExt10:$imm),
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(XORIr32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// select conditional patterns:
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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class SELECTNegCondReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
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SPUInstr selinstr, SPUInstr cmpare>:
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Pat<(select (inttype (cond rclass:$rA, rclass:$rB)),
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rclass:$rTrue, rclass:$rFalse),
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(selinstr rclass:$rTrue, rclass:$rFalse,
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(cmpare rclass:$rA, rclass:$rB))>;
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class SELECTNegCondImm<PatFrag cond, RegisterClass rclass, ValueType inttype,
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PatLeaf immpred, SPUInstr selinstr, SPUInstr cmpare>:
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Pat<(select (inttype (cond rclass:$rA, immpred:$imm)),
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rclass:$rTrue, rclass:$rFalse),
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(selinstr rclass:$rTrue, rclass:$rFalse,
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(cmpare rclass:$rA, immpred:$imm))>;
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def : SELECTNegCondReg<setne, R8C, i8, SELBr8, CEQBr8>;
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def : SELECTNegCondImm<setne, R8C, i8, immSExt8, SELBr8, CEQBIr8>;
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def : SELECTNegCondReg<setle, R8C, i8, SELBr8, CGTBr8>;
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def : SELECTNegCondImm<setle, R8C, i8, immSExt8, SELBr8, CGTBr8>;
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def : SELECTNegCondReg<setule, R8C, i8, SELBr8, CLGTBr8>;
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def : SELECTNegCondImm<setule, R8C, i8, immU8, SELBr8, CLGTBIr8>;
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def : SELECTNegCondReg<setne, R16C, i16, SELBr16, CEQHr16>;
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def : SELECTNegCondImm<setne, R16C, i16, i16ImmSExt10, SELBr16, CEQHIr16>;
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def : SELECTNegCondReg<setle, R16C, i16, SELBr16, CGTHr16>;
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def : SELECTNegCondImm<setle, R16C, i16, i16ImmSExt10, SELBr16, CGTHIr16>;
|
||||
def : SELECTNegCondReg<setule, R16C, i16, SELBr16, CLGTHr16>;
|
||||
def : SELECTNegCondImm<setule, R16C, i16, i16ImmSExt10, SELBr16, CLGTHIr16>;
|
||||
|
||||
def : SELECTNegCondReg<setne, R32C, i32, SELBr32, CEQr32>;
|
||||
def : SELECTNegCondImm<setne, R32C, i32, i32ImmSExt10, SELBr32, CEQIr32>;
|
||||
def : SELECTNegCondReg<setle, R32C, i32, SELBr32, CGTr32>;
|
||||
def : SELECTNegCondImm<setle, R32C, i32, i32ImmSExt10, SELBr32, CGTIr32>;
|
||||
def : SELECTNegCondReg<setule, R32C, i32, SELBr32, CLGTr32>;
|
||||
def : SELECTNegCondImm<setule, R32C, i32, i32ImmSExt10, SELBr32, CLGTIr32>;
|
||||
|
||||
class SELECTBinOpReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
|
||||
SPUInstr selinstr, SPUInstr binop, SPUInstr cmpOp1,
|
||||
SPUInstr cmpOp2>:
|
||||
Pat<(select (inttype (cond rclass:$rA, rclass:$rB)),
|
||||
rclass:$rFalse, rclass:$rTrue),
|
||||
(selinstr rclass:$rTrue, rclass:$rFalse,
|
||||
(binop (cmpOp1 rclass:$rA, rclass:$rB),
|
||||
(cmpOp2 rclass:$rA, rclass:$rB)))>;
|
||||
|
||||
class SELECTBinOpImm<PatFrag cond, RegisterClass rclass, PatLeaf immpred,
|
||||
ValueType inttype,
|
||||
SPUInstr selinstr, SPUInstr binop, SPUInstr cmpOp1,
|
||||
SPUInstr cmpOp2>:
|
||||
Pat<(select (inttype (cond rclass:$rA, (inttype immpred:$imm))),
|
||||
rclass:$rTrue, rclass:$rFalse),
|
||||
(selinstr rclass:$rFalse, rclass:$rTrue,
|
||||
(binop (cmpOp1 rclass:$rA, (inttype immpred:$imm)),
|
||||
(cmpOp2 rclass:$rA, (inttype immpred:$imm))))>;
|
||||
|
||||
def : SELECTBinOpReg<setge, R8C, i8, SELBr8, ORr8, CGTBr8, CEQBr8>;
|
||||
def : SELECTBinOpImm<setge, R8C, immSExt8, i8,
|
||||
SELBr8, ORr8, CGTBIr8, CEQBIr8>;
|
||||
|
||||
def : SELECTBinOpReg<setge, R16C, i16, SELBr16, ORr16, CGTHr16, CEQHr16>;
|
||||
def : SELECTBinOpImm<setge, R16C, i16ImmSExt10, i16,
|
||||
SELBr16, ORr16, CGTHIr16, CEQHIr16>;
|
||||
|
||||
def : SELECTBinOpReg<setge, R32C, i32, SELBr32, ORr32, CGTr32, CEQr32>;
|
||||
def : SELECTBinOpImm<setge, R32C, i32ImmSExt10, i32,
|
||||
SELBr32, ORr32, CGTIr32, CEQIr32>;
|
||||
|
||||
def : SELECTBinOpReg<setuge, R8C, i8, SELBr8, ORr8, CLGTBr8, CEQBr8>;
|
||||
def : SELECTBinOpImm<setuge, R8C, immSExt8, i8,
|
||||
SELBr8, ORr8, CLGTBIr8, CEQBIr8>;
|
||||
|
||||
def : SELECTBinOpReg<setuge, R16C, i16, SELBr16, ORr16, CLGTHr16, CEQHr16>;
|
||||
def : SELECTBinOpImm<setuge, R16C, i16ImmUns10, i16,
|
||||
SELBr16, ORr16, CLGTHIr16, CEQHIr16>;
|
||||
|
||||
def : SELECTBinOpReg<setuge, R32C, i32, SELBr32, ORr32, CLGTr32, CEQr32>;
|
||||
def : SELECTBinOpImm<setuge, R32C, i32ImmUns10, i32,
|
||||
SELBr32, ORr32, CLGTIr32, CEQIr32>;
|
||||
|
||||
//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
|
||||
|
||||
|
||||
340
test/CodeGen/CellSPU/icmp16.ll
Normal file
340
test/CodeGen/CellSPU/icmp16.ll
Normal file
@ -0,0 +1,340 @@
|
||||
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
|
||||
|
||||
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
|
||||
target triple = "spu"
|
||||
|
||||
; $3 = %arg1, $4 = %arg2, $5 = %val1, $6 = %val2
|
||||
; $3 = %arg1, $4 = %val1, $5 = %val2
|
||||
;
|
||||
; For "positive" comparisons:
|
||||
; selb $3, $6, $5, <i1>
|
||||
; selb $3, $5, $4, <i1>
|
||||
;
|
||||
; For "negative" comparisons, i.e., those where the result of the comparison
|
||||
; must be inverted (setne, for example):
|
||||
; selb $3, $5, $6, <i1>
|
||||
; selb $3, $4, $5, <i1>
|
||||
|
||||
; i16 integer comparisons:
|
||||
define i16 @icmp_eq_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp eq i16 %arg1, %arg2
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_eq_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp eq i16 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
define i16 @icmp_eq_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp eq i16 %arg1, 511
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i16 @icmp_eq_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp eq i16 %arg1, -512
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i16 @icmp_eq_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp eq i16 %arg1, -1
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i16 @icmp_eq_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp eq i16 %arg1, 32768
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i16 @icmp_ne_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ne i16 %arg1, %arg2
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_ne_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ne i16 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
define i16 @icmp_ne_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ne i16 %arg1, 511
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i16 @icmp_ne_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ne i16 %arg1, -512
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i16 @icmp_ne_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ne i16 %arg1, -1
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i16 @icmp_ne_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ne i16 %arg1, 32768
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i16 @icmp_ugt_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ugt i16 %arg1, %arg2
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_ugt_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ugt i16 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
define i16 @icmp_ugt_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ugt i16 %arg1, 511
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i16 @icmp_ugt_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ugt i16 %arg1, 65534
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i16 @icmp_ugt_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ugt i16 %arg1, 65024
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i16 @icmp_ugt_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ugt i16 %arg1, 32768
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i16 @icmp_uge_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp uge i16 %arg1, %arg2
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_uge_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp uge i16 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
;; Note: icmp uge i16 %arg1, <immed> can always be transformed into
|
||||
;; icmp ugt i16 %arg1, <immed>-1
|
||||
;;
|
||||
;; Consequently, even though the patterns exist to match, it's unlikely
|
||||
;; they'll ever be generated.
|
||||
|
||||
define i16 @icmp_ult_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ult i16 %arg1, %arg2
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_ult_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ult i16 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
define i16 @icmp_ult_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ult i16 %arg1, 511
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i16 @icmp_ult_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ult i16 %arg1, 65534
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i16 @icmp_ult_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ult i16 %arg1, 65024
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i16 @icmp_ult_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ult i16 %arg1, 32768
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i16 @icmp_ule_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ule i16 %arg1, %arg2
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_ule_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ule i16 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
;; Note: icmp ule i16 %arg1, <immed> can always be transformed into
|
||||
;; icmp ult i16 %arg1, <immed>+1
|
||||
;;
|
||||
;; Consequently, even though the patterns exist to match, it's unlikely
|
||||
;; they'll ever be generated.
|
||||
|
||||
define i16 @icmp_sgt_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sgt i16 %arg1, %arg2
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_sgt_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sgt i16 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
define i16 @icmp_sgt_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sgt i16 %arg1, 511
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i16 @icmp_sgt_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sgt i16 %arg1, -1
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i16 @icmp_sgt_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sgt i16 %arg1, -512
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i16 @icmp_sgt_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sgt i16 %arg1, 32768
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i16 @icmp_sge_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sge i16 %arg1, %arg2
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_sge_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sge i16 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
;; Note: icmp sge i16 %arg1, <immed> can always be transformed into
|
||||
;; icmp sgt i16 %arg1, <immed>-1
|
||||
;;
|
||||
;; Consequently, even though the patterns exist to match, it's unlikely
|
||||
;; they'll ever be generated.
|
||||
|
||||
define i16 @icmp_slt_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp slt i16 %arg1, %arg2
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_slt_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp slt i16 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
define i16 @icmp_slt_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp slt i16 %arg1, 511
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i16 @icmp_slt_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp slt i16 %arg1, -512
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i16 @icmp_slt_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp slt i16 %arg1, -1
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i16 @icmp_slt_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp slt i16 %arg1, 32768
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i16 @icmp_sle_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sle i16 %arg1, %arg2
|
||||
%B = select i1 %A, i16 %val1, i16 %val2
|
||||
ret i16 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_sle_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sle i16 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
;; Note: icmp sle i16 %arg1, <immed> can always be transformed into
|
||||
;; icmp slt i16 %arg1, <immed>+1
|
||||
;;
|
||||
;; Consequently, even though the patterns exist to match, it's unlikely
|
||||
;; they'll ever be generated.
|
||||
|
||||
340
test/CodeGen/CellSPU/icmp32.ll
Normal file
340
test/CodeGen/CellSPU/icmp32.ll
Normal file
@ -0,0 +1,340 @@
|
||||
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
|
||||
|
||||
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
|
||||
target triple = "spu"
|
||||
|
||||
; $3 = %arg1, $4 = %arg2, $5 = %val1, $6 = %val2
|
||||
; $3 = %arg1, $4 = %val1, $5 = %val2
|
||||
;
|
||||
; For "positive" comparisons:
|
||||
; selb $3, $6, $5, <i1>
|
||||
; selb $3, $5, $4, <i1>
|
||||
;
|
||||
; For "negative" comparisons, i.e., those where the result of the comparison
|
||||
; must be inverted (setne, for example):
|
||||
; selb $3, $5, $6, <i1>
|
||||
; selb $3, $4, $5, <i1>
|
||||
|
||||
; i32 integer comparisons:
|
||||
define i32 @icmp_eq_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp eq i32 %arg1, %arg2
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_eq_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp eq i32 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
define i32 @icmp_eq_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp eq i32 %arg1, 511
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @icmp_eq_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp eq i32 %arg1, -512
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @icmp_eq_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp eq i32 %arg1, -1
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @icmp_eq_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp eq i32 %arg1, 32768
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @icmp_ne_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ne i32 %arg1, %arg2
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_ne_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ne i32 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
define i32 @icmp_ne_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ne i32 %arg1, 511
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @icmp_ne_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ne i32 %arg1, -512
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @icmp_ne_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ne i32 %arg1, -1
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @icmp_ne_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ne i32 %arg1, 32768
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @icmp_ugt_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ugt i32 %arg1, %arg2
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_ugt_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ugt i32 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
define i32 @icmp_ugt_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ugt i32 %arg1, 511
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @icmp_ugt_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ugt i32 %arg1, 4294966784
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @icmp_ugt_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ugt i32 %arg1, 4294967293
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @icmp_ugt_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ugt i32 %arg1, 32768
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @icmp_uge_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp uge i32 %arg1, %arg2
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_uge_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp uge i32 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
;; Note: icmp uge i32 %arg1, <immed> can always be transformed into
|
||||
;; icmp ugt i32 %arg1, <immed>-1
|
||||
;;
|
||||
;; Consequently, even though the patterns exist to match, it's unlikely
|
||||
;; they'll ever be generated.
|
||||
|
||||
define i32 @icmp_ult_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ult i32 %arg1, %arg2
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_ult_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ult i32 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
define i32 @icmp_ult_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ult i32 %arg1, 511
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @icmp_ult_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ult i32 %arg1, 4294966784
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @icmp_ult_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ult i32 %arg1, 4294967293
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @icmp_ult_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ult i32 %arg1, 32768
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @icmp_ule_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ule i32 %arg1, %arg2
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_ule_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ule i32 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
;; Note: icmp ule i32 %arg1, <immed> can always be transformed into
|
||||
;; icmp ult i32 %arg1, <immed>+1
|
||||
;;
|
||||
;; Consequently, even though the patterns exist to match, it's unlikely
|
||||
;; they'll ever be generated.
|
||||
|
||||
define i32 @icmp_sgt_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sgt i32 %arg1, %arg2
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_sgt_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sgt i32 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
define i32 @icmp_sgt_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sgt i32 %arg1, 511
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @icmp_sgt_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sgt i32 %arg1, 4294966784
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @icmp_sgt_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sgt i32 %arg1, 4294967293
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @icmp_sgt_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sgt i32 %arg1, 32768
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @icmp_sge_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sge i32 %arg1, %arg2
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_sge_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sge i32 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
;; Note: icmp sge i32 %arg1, <immed> can always be transformed into
|
||||
;; icmp sgt i32 %arg1, <immed>-1
|
||||
;;
|
||||
;; Consequently, even though the patterns exist to match, it's unlikely
|
||||
;; they'll ever be generated.
|
||||
|
||||
define i32 @icmp_slt_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp slt i32 %arg1, %arg2
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_slt_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp slt i32 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
define i32 @icmp_slt_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp slt i32 %arg1, 511
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @icmp_slt_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp slt i32 %arg1, -512
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @icmp_slt_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp slt i32 %arg1, -1
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @icmp_slt_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp slt i32 %arg1, 32768
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i32 @icmp_sle_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sle i32 %arg1, %arg2
|
||||
%B = select i1 %A, i32 %val1, i32 %val2
|
||||
ret i32 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_sle_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sle i32 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
;; Note: icmp sle i32 %arg1, <immed> can always be transformed into
|
||||
;; icmp slt i32 %arg1, <immed>+1
|
||||
;;
|
||||
;; Consequently, even though the patterns exist to match, it's unlikely
|
||||
;; they'll ever be generated.
|
||||
|
||||
277
test/CodeGen/CellSPU/icmp8.ll
Normal file
277
test/CodeGen/CellSPU/icmp8.ll
Normal file
@ -0,0 +1,277 @@
|
||||
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
|
||||
|
||||
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
|
||||
target triple = "spu"
|
||||
|
||||
; $3 = %arg1, $4 = %arg2, $5 = %val1, $6 = %val2
|
||||
; $3 = %arg1, $4 = %val1, $5 = %val2
|
||||
;
|
||||
; For "positive" comparisons:
|
||||
; selb $3, $6, $5, <i1>
|
||||
; selb $3, $5, $4, <i1>
|
||||
;
|
||||
; For "negative" comparisons, i.e., those where the result of the comparison
|
||||
; must be inverted (setne, for example):
|
||||
; selb $3, $5, $6, <i1>
|
||||
; selb $3, $4, $5, <i1>
|
||||
|
||||
; i8 integer comparisons:
|
||||
define i8 @icmp_eq_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp eq i8 %arg1, %arg2
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_eq_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp eq i8 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
define i8 @icmp_eq_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp eq i8 %arg1, 127
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i8 @icmp_eq_immed02_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp eq i8 %arg1, -128
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i8 @icmp_eq_immed03_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp eq i8 %arg1, -1
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i8 @icmp_ne_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ne i8 %arg1, %arg2
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_ne_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ne i8 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
define i8 @icmp_ne_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ne i8 %arg1, 127
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i8 @icmp_ne_immed02_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ne i8 %arg1, -128
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i8 @icmp_ne_immed03_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ne i8 %arg1, -1
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i8 @icmp_ugt_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ugt i8 %arg1, %arg2
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_ugt_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ugt i8 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
define i8 @icmp_ugt_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ugt i8 %arg1, 126
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i8 @icmp_uge_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp uge i8 %arg1, %arg2
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_uge_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp uge i8 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
;; Note: icmp uge i8 %arg1, <immed> can always be transformed into
|
||||
;; icmp ugt i8 %arg1, <immed>-1
|
||||
;;
|
||||
;; Consequently, even though the patterns exist to match, it's unlikely
|
||||
;; they'll ever be generated.
|
||||
|
||||
define i8 @icmp_ult_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ult i8 %arg1, %arg2
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_ult_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ult i8 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
define i8 @icmp_ult_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ult i8 %arg1, 253
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i8 @icmp_ult_immed02_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ult i8 %arg1, 129
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i8 @icmp_ule_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ule i8 %arg1, %arg2
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_ule_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp ule i8 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
;; Note: icmp ule i8 %arg1, <immed> can always be transformed into
|
||||
;; icmp ult i8 %arg1, <immed>+1
|
||||
;;
|
||||
;; Consequently, even though the patterns exist to match, it's unlikely
|
||||
;; they'll ever be generated.
|
||||
|
||||
define i8 @icmp_sgt_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sgt i8 %arg1, %arg2
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_sgt_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sgt i8 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
define i8 @icmp_sgt_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sgt i8 %arg1, 127
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i8 @icmp_sgt_immed02_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sgt i8 %arg1, -1
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i8 @icmp_sgt_immed03_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sgt i8 %arg1, -128
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i8 @icmp_sge_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sge i8 %arg1, %arg2
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_sge_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sge i8 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
;; Note: icmp sge i8 %arg1, <immed> can always be transformed into
|
||||
;; icmp sgt i8 %arg1, <immed>-1
|
||||
;;
|
||||
;; Consequently, even though the patterns exist to match, it's unlikely
|
||||
;; they'll ever be generated.
|
||||
|
||||
define i8 @icmp_slt_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp slt i8 %arg1, %arg2
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_slt_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp slt i8 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
define i8 @icmp_slt_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp slt i8 %arg1, 127
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i8 @icmp_slt_immed02_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp slt i8 %arg1, -128
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i8 @icmp_slt_immed03_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp slt i8 %arg1, -1
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i8 @icmp_sle_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sle i8 %arg1, %arg2
|
||||
%B = select i1 %A, i8 %val1, i8 %val2
|
||||
ret i8 %B
|
||||
}
|
||||
|
||||
define i1 @icmp_sle_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
|
||||
entry:
|
||||
%A = icmp sle i8 %arg1, %arg2
|
||||
ret i1 %A
|
||||
}
|
||||
|
||||
;; Note: icmp sle i8 %arg1, <immed> can always be transformed into
|
||||
;; icmp slt i8 %arg1, <immed>+1
|
||||
;;
|
||||
;; Consequently, even though the patterns exist to match, it's unlikely
|
||||
;; they'll ever be generated.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user