mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-25 00:29:20 +00:00
Make FGR64RegisterClass available if target is Mips64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140397 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
b1dcff0fe3
commit
792016bc22
@ -84,6 +84,7 @@ MipsTargetLowering::
|
|||||||
MipsTargetLowering(MipsTargetMachine &TM)
|
MipsTargetLowering(MipsTargetMachine &TM)
|
||||||
: TargetLowering(TM, new MipsTargetObjectFile()) {
|
: TargetLowering(TM, new MipsTargetObjectFile()) {
|
||||||
Subtarget = &TM.getSubtarget<MipsSubtarget>();
|
Subtarget = &TM.getSubtarget<MipsSubtarget>();
|
||||||
|
bool HasMips64 = Subtarget->hasMips64();
|
||||||
|
|
||||||
// Mips does not have i1 type, so use i32 for
|
// Mips does not have i1 type, so use i32 for
|
||||||
// setcc operations results (slt, sgt, ...).
|
// setcc operations results (slt, sgt, ...).
|
||||||
@ -95,8 +96,12 @@ MipsTargetLowering(MipsTargetMachine &TM)
|
|||||||
addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
|
addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
|
||||||
|
|
||||||
// When dealing with single precision only, use libcalls
|
// When dealing with single precision only, use libcalls
|
||||||
if (!Subtarget->isSingleFloat())
|
if (!Subtarget->isSingleFloat()) {
|
||||||
|
if (HasMips64)
|
||||||
|
addRegisterClass(MVT::f64, Mips::FGR64RegisterClass);
|
||||||
|
else
|
||||||
addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
|
addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
|
||||||
|
}
|
||||||
|
|
||||||
// Load extented operations for i1 types must be promoted
|
// Load extented operations for i1 types must be promoted
|
||||||
setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
|
setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
|
||||||
|
Loading…
Reference in New Issue
Block a user