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Make FGR64RegisterClass available if target is Mips64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140397 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -84,6 +84,7 @@ MipsTargetLowering::
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MipsTargetLowering(MipsTargetMachine &TM)
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MipsTargetLowering(MipsTargetMachine &TM)
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: TargetLowering(TM, new MipsTargetObjectFile()) {
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: TargetLowering(TM, new MipsTargetObjectFile()) {
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Subtarget = &TM.getSubtarget<MipsSubtarget>();
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Subtarget = &TM.getSubtarget<MipsSubtarget>();
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bool HasMips64 = Subtarget->hasMips64();
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// Mips does not have i1 type, so use i32 for
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// Mips does not have i1 type, so use i32 for
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// setcc operations results (slt, sgt, ...).
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// setcc operations results (slt, sgt, ...).
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@ -95,8 +96,12 @@ MipsTargetLowering(MipsTargetMachine &TM)
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addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
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addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
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// When dealing with single precision only, use libcalls
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// When dealing with single precision only, use libcalls
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if (!Subtarget->isSingleFloat())
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if (!Subtarget->isSingleFloat()) {
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if (HasMips64)
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addRegisterClass(MVT::f64, Mips::FGR64RegisterClass);
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else
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addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
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addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
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}
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// Load extented operations for i1 types must be promoted
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// Load extented operations for i1 types must be promoted
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setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
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