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Add a option which would move ld/st multiple pass before post-alloc scheduling.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83145 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-09-30 08:53:01 +00:00
parent 629adde699
commit 792e1f6df9
2 changed files with 17 additions and 1 deletions
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17
lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -22,6 +22,10 @@
#include "llvm/Target/TargetRegistry.h"
using namespace llvm;
static cl::opt<bool>
LdStBeforeSched("ldstopti-before-sched2", cl::Hidden,
cl::desc("Move ld / st multiple pass before postalloc scheduling"));
static const MCAsmInfo *createMCAsmInfo(const Target &T,
const StringRef &TT) {
Triple TheTriple(TT);
@ -101,11 +105,22 @@ bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
return true;
}
bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
// FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
if (LdStBeforeSched)
PM.add(createARMLoadStoreOptimizationPass());
return true;
}
bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
// FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) {
PM.add(createARMLoadStoreOptimizationPass());
if (!LdStBeforeSched)
PM.add(createARMLoadStoreOptimizationPass());
PM.add(createIfConverterPass());
}

1
lib/Target/ARM/ARMTargetMachine.h
View File

@ -50,6 +50,7 @@ public:
// Pass Pipeline Configuration
virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
MachineCodeEmitter &MCE);