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Instcombine was transforming:

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%shr = lshr i64 %key, 3
  %0 = load i64* %val, align 8
  %sub = add i64 %0, -1
  %and = and i64 %sub, %shr
  ret i64 %and

to:
  %shr = lshr i64 %key, 3
  %0 = load i64* %val, align 8
  %sub = add i64 %0, 2305843009213693951
  %and = and i64 %sub, %shr
  ret i64 %and

The demanded bit optimization is actually a pessimization because add -1 would
be codegen'ed as a sub 1. Teach the demanded constant shrinking optimization
to check for negated constant to make sure it is actually reducing the width
of the constant.

rdar://11793464


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160101 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2012-07-12 01:45:35 +00:00
parent e96ce46b4d
commit 79590b8edf
2 changed files with 25 additions and 0 deletions
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7
lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
View File

@ -40,6 +40,13 @@ static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo,
// This instruction is producing bits that are not demanded. Shrink the RHS.
Demanded &= OpC->getValue();
if (I->getOpcode() == Instruction::Add) {
// However, if the instruction is an add then the constant may be negated
// when the opcode is changed to sub. Check if the transformation is really
// shrinking the constant.
if (Demanded.abs().getActiveBits() > OpC->getValue().abs().getActiveBits())
return false;
}
I->setOperand(OpNo, ConstantInt::get(OpC->getType(), Demanded));
return true;
}

18
test/Transforms/InstCombine/2012-07-11-AddSubDemandedBits.ll Normal file
View File

@ -0,0 +1,18 @@
; RUN: opt < %s -instcombine -S | FileCheck %s
; When shrinking demanded constant operand of an add instruction, keep in
; mind the opcode can be changed to sub and the constant negated. Make sure
; the shrinking the constant would actually reduce the width.
; rdar://11793464
define i64 @t(i64 %key, i64* %val) nounwind {
entry:
; CHECK: @t
; CHECK-NOT: add i64 %0, 2305843009213693951
; CHECK: add i64 %0, -1
%shr = lshr i64 %key, 3
%0 = load i64* %val, align 8
%sub = sub i64 %0, 1
%and = and i64 %sub, %shr
ret i64 %and
}