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Fix decoding of ARM-mode STRH.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137499 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-08-12 20:02:50 +00:00
parent c513309224
commit 79628e92e1
3 changed files with 6 additions and 0 deletions
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1
lib/Target/ARM/ARMInstrFormats.td
View File

@ -664,6 +664,7 @@ class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
let Inst{11-8} = addr{7-4}; // imm7_4/zero
let Inst{7-4} = op;
let Inst{3-0} = addr{3-0}; // imm3_0/Rm
let DecoderMethod = "DecodeAddrMode3Instruction";
}
// Pre-indexed stores

2
lib/Target/ARM/ARMInstrInfo.td
View File

@ -2365,6 +2365,7 @@ def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
let Inst{11-8} = addr{7-4}; // imm7_4/zero
let Inst{3-0} = addr{3-0}; // imm3_0/Rm
let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
let DecoderMethod = "DecodeAddrMode3Instruction";
}
def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
@ -2381,6 +2382,7 @@ def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
let Inst{19-16} = addr;
let Inst{11-8} = offset{7-4}; // imm7_4/zero
let Inst{3-0} = offset{3-0}; // imm3_0/Rm
let DecoderMethod = "DecodeAddrMode3Instruction";
}
let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {

3
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -1090,6 +1090,9 @@ static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
case ARM::STRD:
case ARM::STRD_PRE:
case ARM::STRD_POST:
case ARM::STRH:
case ARM::STRH_PRE:
case ARM::STRH_POST:
if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
return false;
break;