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ARM: further correct .fpu directive handling
If the original FPU specification involved a restricted VFP unit (d16), ensure that we reset the functionality when we encounter a new FPU type. In particular, if the user specified vfpv3-d16, but switched to a VFPv3 (which has 32 double precision registers), we would fail to reset the D16 feature, and treat it as being equivalent to vfpv3-d16. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227603 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -9197,11 +9197,12 @@ static const struct {
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} FPUs[] = {
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{ARM::VFP, ARM::FeatureVFP2, ARM::FeatureNEON},
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{ARM::VFPV2, ARM::FeatureVFP2, ARM::FeatureNEON},
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{ARM::VFPV3, ARM::FeatureVFP2 | ARM::FeatureVFP3, ARM::FeatureNEON},
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{ARM::VFPV3, ARM::FeatureVFP2 | ARM::FeatureVFP3,
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ARM::FeatureNEON | ARM::FeatureD16},
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{ARM::VFPV3_D16, ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureD16,
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ARM::FeatureNEON},
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{ARM::VFPV4, ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4,
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ARM::FeatureNEON},
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ARM::FeatureNEON | ARM::FeatureD16},
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{ARM::VFPV4_D16,
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ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 | ARM::FeatureD16,
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ARM::FeatureNEON},
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@ -9210,19 +9211,20 @@ static const struct {
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ARM::FeatureNEON | ARM::FeatureCrypto},
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{ARM::FP_ARMV8, ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
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ARM::FeatureFPARMv8,
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ARM::FeatureNEON | ARM::FeatureCrypto},
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{ARM::NEON, ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureNEON, 0},
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ARM::FeatureNEON | ARM::FeatureCrypto | ARM::FeatureD16},
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{ARM::NEON, ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureNEON,
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ARM::FeatureD16},
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{ARM::NEON_VFPV4,
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ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 | ARM::FeatureNEON,
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0},
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ARM::FeatureD16},
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{ARM::NEON_FP_ARMV8,
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ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
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ARM::FeatureFPARMv8 | ARM::FeatureNEON,
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ARM::FeatureCrypto},
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ARM::FeatureCrypto | ARM::FeatureD16},
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{ARM::CRYPTO_NEON_FP_ARMV8,
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ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
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ARM::FeatureFPARMv8 | ARM::FeatureNEON | ARM::FeatureCrypto,
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0},
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ARM::FeatureD16},
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{ARM::SOFTVFP, 0, 0},
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};
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37
test/MC/ARM/pr22395-2.s
Normal file
37
test/MC/ARM/pr22395-2.s
Normal file
@ -0,0 +1,37 @@
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@ RUN: llvm-mc -triple armv4t-eabi -mattr +d16 -filetype asm -o - %s 2>&1 | FileCheck %s
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.text
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.thumb
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.p2align 2
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.fpu vfpv3
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vldmia r0, {d16-d31}
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@ CHECK: vldmia r0, {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31}
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@ CHECK-NOT: error: register expected
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.fpu vfpv4
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vldmia r0, {d16-d31}
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@ CHECK: vldmia r0, {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31}
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@ CHECK-NOT: error: register expected
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.fpu neon
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vldmia r0, {d16-d31}
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@ CHECK: vldmia r0, {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31}
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@ CHECK-NOT: error: register expected
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.fpu neon-vfpv4
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vldmia r0, {d16-d31}
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@ CHECK: vldmia r0, {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31}
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@ CHECK-NOT: error: register expected
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.fpu neon-fp-armv8
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vldmia r0, {d16-d31}
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@ CHECK: vldmia r0, {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31}
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@ CHECK-NOT: error: register expected
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.fpu crypto-neon-fp-armv8
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vldmia r0, {d16-d31}
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@ CHECK: vldmia r0, {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31}
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@ CHECK-NOT: error: register expected
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