mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 19:29:31 +00:00
treat conditional branches the same way as conditional moves (giving them
an operand that contains the condcode), making things significantly simpler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25840 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
6788faa06a
commit
7a4d2913ea
@ -82,40 +82,6 @@ namespace llvm {
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};
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}
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static unsigned SPARCCondCodeToBranchInstr(V8CC::CondCodes CC) {
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switch (CC) {
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default: assert(0 && "Unknown condition code");
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case V8CC::ICC_NE: return V8::BNE;
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case V8CC::ICC_E: return V8::BE;
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case V8CC::ICC_G: return V8::BG;
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case V8CC::ICC_LE: return V8::BLE;
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case V8CC::ICC_GE: return V8::BGE;
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case V8CC::ICC_L: return V8::BL;
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case V8CC::ICC_GU: return V8::BGU;
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case V8CC::ICC_LEU: return V8::BLEU;
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case V8CC::ICC_CC: return V8::BCC;
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case V8CC::ICC_CS: return V8::BCS;
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case V8CC::ICC_POS: return V8::BPOS;
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case V8CC::ICC_NEG: return V8::BNEG;
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case V8CC::ICC_VC: return V8::BVC;
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case V8CC::ICC_VS: return V8::BVS;
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case V8CC::FCC_U: return V8::FBU;
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case V8CC::FCC_G: return V8::FBG;
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case V8CC::FCC_UG: return V8::FBUG;
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case V8CC::FCC_L: return V8::FBL;
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case V8CC::FCC_UL: return V8::FBUL;
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case V8CC::FCC_LG: return V8::FBLG;
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case V8CC::FCC_NE: return V8::FBNE;
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case V8CC::FCC_E: return V8::FBE;
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case V8CC::FCC_UE: return V8::FBUE;
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case V8CC::FCC_GE: return V8::FBGE;
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case V8CC::FCC_UGE: return V8::FBUGE;
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case V8CC::FCC_LE: return V8::FBLE;
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case V8CC::FCC_ULE: return V8::FBULE;
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case V8CC::FCC_O: return V8::FBO;
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}
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}
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static const char *SPARCCondCodeToString(V8CC::CondCodes CC) {
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switch (CC) {
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default: assert(0 && "Unknown condition code");
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@ -817,19 +817,22 @@ MachineBasicBlock *
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SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *BB) {
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unsigned BROpcode;
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unsigned CC;
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// Figure out the conditional branch opcode to use for this select_cc.
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switch (MI->getOpcode()) {
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default: assert(0 && "Unknown SELECT_CC!");
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case V8::SELECT_CC_Int_ICC:
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case V8::SELECT_CC_FP_ICC:
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case V8::SELECT_CC_DFP_ICC:
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BROpcode = V8::BCOND;
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case V8::SELECT_CC_Int_FCC:
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case V8::SELECT_CC_FP_FCC:
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case V8::SELECT_CC_DFP_FCC:
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V8CC::CondCodes CC = (V8CC::CondCodes)MI->getOperand(3).getImmedValue();
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BROpcode = SPARCCondCodeToBranchInstr(CC);
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BROpcode = V8::FBCOND;
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break;
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}
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CC = (V8CC::CondCodes)MI->getOperand(3).getImmedValue();
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// To "insert" a SELECT_CC instruction, we actually have to insert the diamond
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// control-flow pattern. The incoming instruction knows the destination vreg
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@ -847,7 +850,7 @@ SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *thisMBB = BB;
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MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
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BuildMI(BB, BROpcode, 1).addMBB(sinkMBB);
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BuildMI(BB, BROpcode, 2).addMBB(sinkMBB).addImm(CC);
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MachineFunction *F = BB->getParent();
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F->getBasicBlockList().insert(It, copy0MBB);
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F->getBasicBlockList().insert(It, sinkMBB);
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@ -136,9 +136,7 @@ def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag,
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// Note that these values must be kept in sync with the V8CC::CondCode enum
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// values.
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class ICC_VAL<int N> : PatLeaf<(i32 N)> {
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int ICCVal = N;
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}
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class ICC_VAL<int N> : PatLeaf<(i32 N)>;
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def ICC_NE : ICC_VAL< 9>; // Not Equal
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def ICC_E : ICC_VAL< 1>; // Equal
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def ICC_G : ICC_VAL<10>; // Greater
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@ -154,9 +152,7 @@ def ICC_NEG : ICC_VAL< 6>; // Negative
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def ICC_VC : ICC_VAL<15>; // Overflow Clear
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def ICC_VS : ICC_VAL< 7>; // Overflow Set
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class FCC_VAL<int N> : PatLeaf<(i32 N)> {
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int FCCVal = N;
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}
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class FCC_VAL<int N> : PatLeaf<(i32 N)>;
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def FCC_U : FCC_VAL<23>; // Unordered
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def FCC_G : FCC_VAL<22>; // Greater
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def FCC_UG : FCC_VAL<21>; // Unordered or Greater
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@ -550,49 +546,11 @@ let isBarrier = 1 in
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def BA : BranchV8<0b1000, (ops brtarget:$dst),
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"ba $dst",
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[(br bb:$dst)]>;
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def BNE : BranchV8<0b1001, (ops brtarget:$dst),
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"bne $dst",
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[(V8bricc bb:$dst, ICC_NE, ICC)]>;
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def BE : BranchV8<0b0001, (ops brtarget:$dst),
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"be $dst",
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[(V8bricc bb:$dst, ICC_E, ICC)]>;
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def BG : BranchV8<0b1010, (ops brtarget:$dst),
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"bg $dst",
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[(V8bricc bb:$dst, ICC_G, ICC)]>;
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def BLE : BranchV8<0b0010, (ops brtarget:$dst),
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"ble $dst",
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[(V8bricc bb:$dst, ICC_LE, ICC)]>;
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def BGE : BranchV8<0b1011, (ops brtarget:$dst),
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"bge $dst",
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[(V8bricc bb:$dst, ICC_GE, ICC)]>;
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def BL : BranchV8<0b0011, (ops brtarget:$dst),
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"bl $dst",
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[(V8bricc bb:$dst, ICC_L, ICC)]>;
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def BGU : BranchV8<0b1100, (ops brtarget:$dst),
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"bgu $dst",
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[(V8bricc bb:$dst, ICC_GU, ICC)]>;
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def BLEU : BranchV8<0b0100, (ops brtarget:$dst),
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"bleu $dst",
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[(V8bricc bb:$dst, ICC_LEU, ICC)]>;
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def BCC : BranchV8<0b1101, (ops brtarget:$dst),
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"bcc $dst",
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[(V8bricc bb:$dst, ICC_CC, ICC)]>;
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def BCS : BranchV8<0b0101, (ops brtarget:$dst),
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"bcs $dst",
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[(V8bricc bb:$dst, ICC_CS, ICC)]>;
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def BPOS : BranchV8<0b1110, (ops brtarget:$dst),
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"bpos $dst",
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[(V8bricc bb:$dst, ICC_POS, ICC)]>;
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def BNEG : BranchV8<0b0110, (ops brtarget:$dst),
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"bneg $dst",
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[(V8bricc bb:$dst, ICC_NEG, ICC)]>;
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def BVC : BranchV8<0b1111, (ops brtarget:$dst),
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"bvc $dst",
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[(V8bricc bb:$dst, ICC_VC, ICC)]>;
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def BVS : BranchV8<0b0111, (ops brtarget:$dst),
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"bvs $dst",
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[(V8bricc bb:$dst, ICC_VS, ICC)]>;
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// FIXME: the encoding for the JIT should look at the condition field.
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def BCOND : BranchV8<0, (ops brtarget:$dst, V8CC:$cc),
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"b$cc $dst",
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[(V8bricc bb:$dst, imm:$cc, ICC)]>;
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// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
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@ -606,49 +564,10 @@ class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
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let noResults = 1;
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}
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def FBU : FPBranchV8<0b0111, (ops brtarget:$dst),
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"fbu $dst",
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[(V8brfcc bb:$dst, FCC_U, FCC)]>;
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def FBG : FPBranchV8<0b0110, (ops brtarget:$dst),
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"fbg $dst",
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[(V8brfcc bb:$dst, FCC_G, FCC)]>;
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def FBUG : FPBranchV8<0b0101, (ops brtarget:$dst),
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"fbug $dst",
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[(V8brfcc bb:$dst, FCC_UG, FCC)]>;
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def FBL : FPBranchV8<0b0100, (ops brtarget:$dst),
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"fbl $dst",
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[(V8brfcc bb:$dst, FCC_L, FCC)]>;
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def FBUL : FPBranchV8<0b0011, (ops brtarget:$dst),
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"fbul $dst",
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[(V8brfcc bb:$dst, FCC_UL, FCC)]>;
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def FBLG : FPBranchV8<0b0010, (ops brtarget:$dst),
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"fblg $dst",
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[(V8brfcc bb:$dst, FCC_LG, FCC)]>;
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def FBNE : FPBranchV8<0b0001, (ops brtarget:$dst),
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"fbne $dst",
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[(V8brfcc bb:$dst, FCC_NE, FCC)]>;
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def FBE : FPBranchV8<0b1001, (ops brtarget:$dst),
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"fbe $dst",
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[(V8brfcc bb:$dst, FCC_E, FCC)]>;
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def FBUE : FPBranchV8<0b1010, (ops brtarget:$dst),
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"fbue $dst",
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[(V8brfcc bb:$dst, FCC_UE, FCC)]>;
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def FBGE : FPBranchV8<0b1011, (ops brtarget:$dst),
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"fbge $dst",
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[(V8brfcc bb:$dst, FCC_GE, FCC)]>;
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def FBUGE: FPBranchV8<0b1100, (ops brtarget:$dst),
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"fbuge $dst",
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[(V8brfcc bb:$dst, FCC_UGE, FCC)]>;
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def FBLE : FPBranchV8<0b1101, (ops brtarget:$dst),
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"fble $dst",
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[(V8brfcc bb:$dst, FCC_LE, FCC)]>;
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def FBULE: FPBranchV8<0b1110, (ops brtarget:$dst),
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"fbule $dst",
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[(V8brfcc bb:$dst, FCC_ULE, FCC)]>;
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def FBO : FPBranchV8<0b1111, (ops brtarget:$dst),
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"fbo $dst",
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[(V8brfcc bb:$dst, FCC_O, FCC)]>;
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// FIXME: the encoding for the JIT should look at the condition field.
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def FBCOND : FPBranchV8<0, (ops brtarget:$dst, V8CC:$cc),
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"f$cc $dst",
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[(V8brfcc bb:$dst, imm:$cc, FCC)]>;
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// Section B.24 - Call and Link Instruction, p. 125
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@ -82,40 +82,6 @@ namespace llvm {
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};
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}
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static unsigned SPARCCondCodeToBranchInstr(V8CC::CondCodes CC) {
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switch (CC) {
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default: assert(0 && "Unknown condition code");
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case V8CC::ICC_NE: return V8::BNE;
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case V8CC::ICC_E: return V8::BE;
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case V8CC::ICC_G: return V8::BG;
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case V8CC::ICC_LE: return V8::BLE;
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case V8CC::ICC_GE: return V8::BGE;
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case V8CC::ICC_L: return V8::BL;
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case V8CC::ICC_GU: return V8::BGU;
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case V8CC::ICC_LEU: return V8::BLEU;
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case V8CC::ICC_CC: return V8::BCC;
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case V8CC::ICC_CS: return V8::BCS;
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case V8CC::ICC_POS: return V8::BPOS;
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case V8CC::ICC_NEG: return V8::BNEG;
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case V8CC::ICC_VC: return V8::BVC;
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case V8CC::ICC_VS: return V8::BVS;
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case V8CC::FCC_U: return V8::FBU;
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case V8CC::FCC_G: return V8::FBG;
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case V8CC::FCC_UG: return V8::FBUG;
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case V8CC::FCC_L: return V8::FBL;
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case V8CC::FCC_UL: return V8::FBUL;
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case V8CC::FCC_LG: return V8::FBLG;
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case V8CC::FCC_NE: return V8::FBNE;
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case V8CC::FCC_E: return V8::FBE;
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case V8CC::FCC_UE: return V8::FBUE;
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case V8CC::FCC_GE: return V8::FBGE;
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case V8CC::FCC_UGE: return V8::FBUGE;
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case V8CC::FCC_LE: return V8::FBLE;
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case V8CC::FCC_ULE: return V8::FBULE;
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case V8CC::FCC_O: return V8::FBO;
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}
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}
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static const char *SPARCCondCodeToString(V8CC::CondCodes CC) {
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switch (CC) {
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default: assert(0 && "Unknown condition code");
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@ -817,19 +817,22 @@ MachineBasicBlock *
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SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *BB) {
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unsigned BROpcode;
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unsigned CC;
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// Figure out the conditional branch opcode to use for this select_cc.
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switch (MI->getOpcode()) {
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default: assert(0 && "Unknown SELECT_CC!");
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case V8::SELECT_CC_Int_ICC:
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case V8::SELECT_CC_FP_ICC:
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case V8::SELECT_CC_DFP_ICC:
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BROpcode = V8::BCOND;
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case V8::SELECT_CC_Int_FCC:
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case V8::SELECT_CC_FP_FCC:
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case V8::SELECT_CC_DFP_FCC:
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V8CC::CondCodes CC = (V8CC::CondCodes)MI->getOperand(3).getImmedValue();
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BROpcode = SPARCCondCodeToBranchInstr(CC);
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BROpcode = V8::FBCOND;
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break;
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}
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CC = (V8CC::CondCodes)MI->getOperand(3).getImmedValue();
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// To "insert" a SELECT_CC instruction, we actually have to insert the diamond
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// control-flow pattern. The incoming instruction knows the destination vreg
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@ -847,7 +850,7 @@ SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *thisMBB = BB;
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MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
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BuildMI(BB, BROpcode, 1).addMBB(sinkMBB);
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BuildMI(BB, BROpcode, 2).addMBB(sinkMBB).addImm(CC);
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MachineFunction *F = BB->getParent();
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F->getBasicBlockList().insert(It, copy0MBB);
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F->getBasicBlockList().insert(It, sinkMBB);
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@ -136,9 +136,7 @@ def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag,
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// Note that these values must be kept in sync with the V8CC::CondCode enum
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// values.
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class ICC_VAL<int N> : PatLeaf<(i32 N)> {
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int ICCVal = N;
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}
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class ICC_VAL<int N> : PatLeaf<(i32 N)>;
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def ICC_NE : ICC_VAL< 9>; // Not Equal
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def ICC_E : ICC_VAL< 1>; // Equal
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def ICC_G : ICC_VAL<10>; // Greater
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@ -154,9 +152,7 @@ def ICC_NEG : ICC_VAL< 6>; // Negative
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def ICC_VC : ICC_VAL<15>; // Overflow Clear
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def ICC_VS : ICC_VAL< 7>; // Overflow Set
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class FCC_VAL<int N> : PatLeaf<(i32 N)> {
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int FCCVal = N;
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}
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class FCC_VAL<int N> : PatLeaf<(i32 N)>;
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def FCC_U : FCC_VAL<23>; // Unordered
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def FCC_G : FCC_VAL<22>; // Greater
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def FCC_UG : FCC_VAL<21>; // Unordered or Greater
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@ -550,49 +546,11 @@ let isBarrier = 1 in
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def BA : BranchV8<0b1000, (ops brtarget:$dst),
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"ba $dst",
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[(br bb:$dst)]>;
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def BNE : BranchV8<0b1001, (ops brtarget:$dst),
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"bne $dst",
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[(V8bricc bb:$dst, ICC_NE, ICC)]>;
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def BE : BranchV8<0b0001, (ops brtarget:$dst),
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"be $dst",
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[(V8bricc bb:$dst, ICC_E, ICC)]>;
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def BG : BranchV8<0b1010, (ops brtarget:$dst),
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"bg $dst",
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[(V8bricc bb:$dst, ICC_G, ICC)]>;
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def BLE : BranchV8<0b0010, (ops brtarget:$dst),
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"ble $dst",
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[(V8bricc bb:$dst, ICC_LE, ICC)]>;
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def BGE : BranchV8<0b1011, (ops brtarget:$dst),
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"bge $dst",
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[(V8bricc bb:$dst, ICC_GE, ICC)]>;
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def BL : BranchV8<0b0011, (ops brtarget:$dst),
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"bl $dst",
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[(V8bricc bb:$dst, ICC_L, ICC)]>;
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def BGU : BranchV8<0b1100, (ops brtarget:$dst),
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"bgu $dst",
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[(V8bricc bb:$dst, ICC_GU, ICC)]>;
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def BLEU : BranchV8<0b0100, (ops brtarget:$dst),
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"bleu $dst",
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[(V8bricc bb:$dst, ICC_LEU, ICC)]>;
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def BCC : BranchV8<0b1101, (ops brtarget:$dst),
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"bcc $dst",
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[(V8bricc bb:$dst, ICC_CC, ICC)]>;
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def BCS : BranchV8<0b0101, (ops brtarget:$dst),
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"bcs $dst",
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[(V8bricc bb:$dst, ICC_CS, ICC)]>;
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def BPOS : BranchV8<0b1110, (ops brtarget:$dst),
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"bpos $dst",
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[(V8bricc bb:$dst, ICC_POS, ICC)]>;
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def BNEG : BranchV8<0b0110, (ops brtarget:$dst),
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"bneg $dst",
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[(V8bricc bb:$dst, ICC_NEG, ICC)]>;
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def BVC : BranchV8<0b1111, (ops brtarget:$dst),
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"bvc $dst",
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[(V8bricc bb:$dst, ICC_VC, ICC)]>;
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def BVS : BranchV8<0b0111, (ops brtarget:$dst),
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"bvs $dst",
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[(V8bricc bb:$dst, ICC_VS, ICC)]>;
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// FIXME: the encoding for the JIT should look at the condition field.
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def BCOND : BranchV8<0, (ops brtarget:$dst, V8CC:$cc),
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"b$cc $dst",
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[(V8bricc bb:$dst, imm:$cc, ICC)]>;
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// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
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@ -606,49 +564,10 @@ class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
|
||||
let noResults = 1;
|
||||
}
|
||||
|
||||
def FBU : FPBranchV8<0b0111, (ops brtarget:$dst),
|
||||
"fbu $dst",
|
||||
[(V8brfcc bb:$dst, FCC_U, FCC)]>;
|
||||
def FBG : FPBranchV8<0b0110, (ops brtarget:$dst),
|
||||
"fbg $dst",
|
||||
[(V8brfcc bb:$dst, FCC_G, FCC)]>;
|
||||
def FBUG : FPBranchV8<0b0101, (ops brtarget:$dst),
|
||||
"fbug $dst",
|
||||
[(V8brfcc bb:$dst, FCC_UG, FCC)]>;
|
||||
def FBL : FPBranchV8<0b0100, (ops brtarget:$dst),
|
||||
"fbl $dst",
|
||||
[(V8brfcc bb:$dst, FCC_L, FCC)]>;
|
||||
def FBUL : FPBranchV8<0b0011, (ops brtarget:$dst),
|
||||
"fbul $dst",
|
||||
[(V8brfcc bb:$dst, FCC_UL, FCC)]>;
|
||||
def FBLG : FPBranchV8<0b0010, (ops brtarget:$dst),
|
||||
"fblg $dst",
|
||||
[(V8brfcc bb:$dst, FCC_LG, FCC)]>;
|
||||
def FBNE : FPBranchV8<0b0001, (ops brtarget:$dst),
|
||||
"fbne $dst",
|
||||
[(V8brfcc bb:$dst, FCC_NE, FCC)]>;
|
||||
def FBE : FPBranchV8<0b1001, (ops brtarget:$dst),
|
||||
"fbe $dst",
|
||||
[(V8brfcc bb:$dst, FCC_E, FCC)]>;
|
||||
def FBUE : FPBranchV8<0b1010, (ops brtarget:$dst),
|
||||
"fbue $dst",
|
||||
[(V8brfcc bb:$dst, FCC_UE, FCC)]>;
|
||||
def FBGE : FPBranchV8<0b1011, (ops brtarget:$dst),
|
||||
"fbge $dst",
|
||||
[(V8brfcc bb:$dst, FCC_GE, FCC)]>;
|
||||
def FBUGE: FPBranchV8<0b1100, (ops brtarget:$dst),
|
||||
"fbuge $dst",
|
||||
[(V8brfcc bb:$dst, FCC_UGE, FCC)]>;
|
||||
def FBLE : FPBranchV8<0b1101, (ops brtarget:$dst),
|
||||
"fble $dst",
|
||||
[(V8brfcc bb:$dst, FCC_LE, FCC)]>;
|
||||
def FBULE: FPBranchV8<0b1110, (ops brtarget:$dst),
|
||||
"fbule $dst",
|
||||
[(V8brfcc bb:$dst, FCC_ULE, FCC)]>;
|
||||
def FBO : FPBranchV8<0b1111, (ops brtarget:$dst),
|
||||
"fbo $dst",
|
||||
[(V8brfcc bb:$dst, FCC_O, FCC)]>;
|
||||
|
||||
// FIXME: the encoding for the JIT should look at the condition field.
|
||||
def FBCOND : FPBranchV8<0, (ops brtarget:$dst, V8CC:$cc),
|
||||
"f$cc $dst",
|
||||
[(V8brfcc bb:$dst, imm:$cc, FCC)]>;
|
||||
|
||||
|
||||
// Section B.24 - Call and Link Instruction, p. 125
|
||||
|
||||
Loading…
Reference in New Issue
Block a user