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Initial support for allocation condition registers

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21246 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2005-04-12 07:04:16 +00:00
parent af2e3e0859
commit 7af0248af4
5 changed files with 67 additions and 13 deletions
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2
lib/Target/PowerPC/PPC32RegisterInfo.td
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@ -37,4 +37,4 @@ def FPRC : RegisterClass<f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
def CRRC : RegisterClass<i32, 32, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>;
def CRRC : RegisterClass<i32, 32, [CR0, CR1, CR5, CR6, CR7, CR2, CR3, CR4]>;

48
lib/Target/PowerPC/PPCInstrFormats.td
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@ -236,13 +236,6 @@ class XForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
dag OL, string asmstr>
: XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr>;
class XForm_5<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
dag OL, string asmstr>
: XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
let A = 0;
let B = 0;
}
class XForm_6<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
dag OL, string asmstr>
: XForm_base_r3xo_swapped<opcode, xo, rc, ppc64, vmx, OL, asmstr>;
@ -343,13 +336,27 @@ class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo,
let BH = 0;
}
class XLForm_3<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
bits<3> BF;
bits<3> BFA;
let Inst{6-8} = BF;
let Inst{9-10} = 0;
let Inst{11-13} = BFA;
let Inst{14-15} = 0;
let Inst{16-20} = 0;
let Inst{21-30} = xo;
let Inst{31} = 0;
}
// 1.7.8 XFX-Form
class XFXForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
bits<5> ST;
bits<5> RT;
bits<10> SPR;
let Inst{6-10} = ST;
let Inst{6-10} = RT;
let Inst{11-20} = SPR;
let Inst{21-30} = xo;
let Inst{31} = 0;
@ -361,6 +368,29 @@ class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, bit ppc64,
let SPR = spr;
}
class XFXForm_3<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
bits<5> RT;
let Inst{6-10} = RT;
let Inst{11-20} = 0;
let Inst{21-30} = xo;
let Inst{31} = 0;
}
class XFXForm_5<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
bits<8> FXM;
bits<5> ST;
let Inst{6-10} = ST;
let Inst{11} = 0;
let Inst{12-19} = FXM;
let Inst{20} = 0;
let Inst{21-30} = xo;
let Inst{31} = 0;
}
class XFXForm_7<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
dag OL, string asmstr>
: XFXForm_1<opcode, xo, ppc64, vmx, OL, asmstr>;

8
lib/Target/PowerPC/PPCInstrInfo.cpp
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@ -65,6 +65,14 @@ bool PPC32InstrInfo::isMoveInstr(const MachineInstr& MI,
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
} else if (oc == PPC::MCRF) { // mcrf cr1, cr2
assert(MI.getNumOperands() == 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
"invalid PPC MCRF instruction");
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
}
return false;
}

7
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -221,7 +221,6 @@ def LWZX : XForm_1<31, 23, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
def LDX : XForm_1<31, 21, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
"ldx $dst, $base, $index">;
}
def MFCR : XForm_5<31, 19, 0, 0, (ops GPRC:$dst), "mfcr $dst">;
def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"and $rA, $rS, $rB">;
let Defs = [CR0] in
@ -341,6 +340,8 @@ def CRNOR : XLForm_1<19, 33, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
"crnor $D, $A, $B">;
def CROR : XLForm_1<19, 449, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
"cror $D, $A, $B">;
def MCRF : XLForm_3<19, 0, 0, 0, (ops CRRC:$BF, CRRC:$BFA),
"mfcr $BF, $BFA">;
// XFX-Form instructions. Instructions that deal with SPRs
//
@ -349,10 +350,12 @@ def CROR : XLForm_1<19, 449, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
// which means the SPR value needs to be multiplied by a factor of 32.
def MFCTR : XFXForm_1_ext<31, 339, 288, 0, 0, (ops GPRC:$rT), "mfctr $rT">;
def MFLR : XFXForm_1_ext<31, 339, 256, 0, 0, (ops GPRC:$rT), "mflr $rT">;
def MFCR : XFXForm_3<31, 19, 0, 0, (ops GPRC:$rT), "mfcr $rT">;
def MTCRF : XFXForm_5<31, 144, 0, 0, (ops CRRC:$FXM, GPRC:$rS),
"mtcrf $FXM, $rS">;
def MTCTR : XFXForm_7_ext<31, 467, 288, 0, 0, (ops GPRC:$rS), "mtctr $rS">;
def MTLR : XFXForm_7_ext<31, 467, 256, 0, 0, (ops GPRC:$rS), "mtlr $rS">;
// XS-Form instructions. Just 'sradi'
//
def SRADI : XSForm_1<31, 413, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),

15
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -69,6 +69,11 @@ static unsigned getIdx(const TargetRegisterClass *RC) {
case 4: return 3;
case 8: return 4;
}
} else if (RC == PPC32::CRRCRegisterClass) {
switch (RC->getSize()) {
default: assert(0 && "Invalid data size!");
case 4: return 2;
}
}
std::cerr << "Invalid register class to getIdx()!\n";
abort();
@ -85,6 +90,9 @@ PPC32RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
if (SrcReg == PPC::LR) {
BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11).addReg(PPC::LR);
addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
} else if (PPC32::CRRCRegisterClass == getClass(SrcReg)) {
BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
} else {
addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(SrcReg),FrameIdx);
}
@ -101,6 +109,9 @@ PPC32RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
if (DestReg == PPC::LR) {
addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
} else if (PPC32::CRRCRegisterClass == getClass(DestReg)) {
addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
} else {
addFrameReference(BuildMI(MBB, MI, OC, 2, DestReg), FrameIdx);
}
@ -116,7 +127,9 @@ void PPC32RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
} else if (RC == PPC32::FPRCRegisterClass) {
BuildMI(MBB, MI, PPC::FMR, 1, DestReg).addReg(SrcReg);
} else {
} else if (RC == PPC32::CRRCRegisterClass) {
BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
} else {
std::cerr << "Attempt to copy register that is not GPR or FPR";
abort();
}