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Do not use the inefficient, fixed function, CBW, CDQ, ... instructions

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6844 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2003-06-22 03:31:18 +00:00
parent 680a7c2d1a
commit 7b52c036f4
2 changed files with 8 additions and 4 deletions
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6
lib/Target/X86/InstSelectSimple.cpp
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@ -1179,7 +1179,7 @@ void ISel::visitDivRem(BinaryOperator &I) {
static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
static const unsigned ExtOpcode[]={ X86::CBW , X86::CWD , X86::CDQ };
static const unsigned SarOpcode[]={ X86::SARir8, X86::SARir16, X86::SARir32 };
static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 };
static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
@ -1197,7 +1197,9 @@ void ISel::visitDivRem(BinaryOperator &I) {
if (isSigned) {
// Emit a sign extension instruction...
BuildMI(BB, ExtOpcode[Class], 0);
unsigned ShiftResult = makeAnotherReg(I.getType());
BuildMI(BB, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31);
BuildMI(BB, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
} else {
// If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);

6
lib/Target/X86/X86ISelSimple.cpp
View File

@ -1179,7 +1179,7 @@ void ISel::visitDivRem(BinaryOperator &I) {
static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
static const unsigned ExtOpcode[]={ X86::CBW , X86::CWD , X86::CDQ };
static const unsigned SarOpcode[]={ X86::SARir8, X86::SARir16, X86::SARir32 };
static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 };
static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
@ -1197,7 +1197,9 @@ void ISel::visitDivRem(BinaryOperator &I) {
if (isSigned) {
// Emit a sign extension instruction...
BuildMI(BB, ExtOpcode[Class], 0);
unsigned ShiftResult = makeAnotherReg(I.getType());
BuildMI(BB, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31);
BuildMI(BB, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
} else {
// If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);