Document the subtarget features better, make sure that 64-bit mode, 64-bit

support, and 64-bit register use are all consistent with each other.

Add a new "IsPPC" feature, to distinguish ppc32 vs ppc64 targets, use this
to configure TargetData differently.  This not makes ppc64 blow up on lots
of stuff :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28825 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPCSubtarget.cpp

@@ -16,6 +16,7 @@
 #include "llvm/Module.h"
 #include "llvm/Support/CommandLine.h"
 #include "PPCGenSubtarget.inc"
+#include <iostream>
 
 using namespace llvm;
 PPCTargetEnum llvm::PPCTarget = TargetDefault;
@@ -75,6 +76,7 @@ PPCSubtarget::PPCSubtarget(const Module &M, const std::string &FS, bool is64Bit)
   , IsGigaProcessor(false)
   , Has64BitSupport(false)
   , Use64BitRegs(false)
+  , IsPPC64(is64Bit)
   , HasAltivec(false)
   , HasFSQRT(false)
   , HasSTFIWX(false)
@@ -90,6 +92,25 @@ PPCSubtarget::PPCSubtarget(const Module &M, const std::string &FS, bool is64Bit)
   // Parse features string.
   ParseSubtargetFeatures(FS, CPU);
 
+  // If we are generating code for ppc64, verify that options make sense.
+  if (is64Bit) {
+    if (!has64BitSupport()) {
+      std::cerr << "PPC: Generation of 64-bit code for a 32-bit processor "
+                   "requested.  Ignoring 32-bit processor feature.\n";
+      Has64BitSupport = true;
+      // Silently force 64-bit register use on ppc64.
+      Use64BitRegs = true;
+    }
+  }
+  
+  // If the user requested use of 64-bit regs, but the cpu selected doesn't
+  // support it, warn and ignore.
+  if (use64BitRegs() && !has64BitSupport()) {
+    std::cerr << "PPC: 64-bit registers requested on CPU without support.  "
+                 "Disabling 64-bit register use.\n";
+    Use64BitRegs = false;
+  }
+  
   // Set the boolean corresponding to the current target triple, or the default
   // if one cannot be determined, to true.
   const std::string& TT = M.getTargetTriple();

lib/Target/PowerPC/PPCSubtarget.h

@@ -35,6 +35,7 @@ protected:
   bool IsGigaProcessor;
   bool Has64BitSupport;
   bool Use64BitRegs;
+  bool IsPPC64;
   bool HasAltivec;
   bool HasFSQRT;
   bool HasSTFIWX;
@@ -58,21 +59,35 @@ public:
   /// getInstrItins - Return the instruction itineraies based on subtarget 
   /// selection.
   const InstrItineraryData getInstrItineraryData() const { return InstrItins; }
-  
+
+  /// getTargetDataString - Return the pointer size and type alignment
+  /// properties of this subtarget.
   const char *getTargetDataString() const {
-    // FIXME: Make is64Bit be for the processor, not the target.
-    return true ? "E-p:32:32-d:32-l:32" : "E-p:64:64-d:32-l:32";
+    return isPPC64() ? "E-p:64:64-d:32-l:32" : "E-p:32:32-d:32-l:32";
   }
 
+  /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
+  ///
+  bool isPPC64() const { return IsPPC64; }
+  
+  /// has64BitSupport - Return true if the selected CPU supports 64-bit
+  /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
+  bool has64BitSupport() const { return Has64BitSupport; }
+  
+  /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
+  /// registers in 32-bit mode when possible.  This can only true if
+  /// has64BitSupport() returns true.
+  bool use64BitRegs() const { return Use64BitRegs; }
+  
+  
+  // Specific obvious features.
   bool hasFSQRT() const { return HasFSQRT; }
   bool hasSTFIWX() const { return HasSTFIWX; }
-  bool use64BitRegs() const { return Use64BitRegs; }
   bool hasAltivec() const { return HasAltivec; }
+  bool isGigaProcessor() const { return IsGigaProcessor; }
   
   bool isAIX() const { return IsAIX; }
   bool isDarwin() const { return IsDarwin; }
-  bool has64BitSupport() const { return Has64BitSupport; }
-  bool isGigaProcessor() const { return IsGigaProcessor; }
 };
 } // End llvm namespace