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Shift amounts are always 32-bits, even in 64-bit mode. This fixes

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CodeGen/PowerPC/2006-09-28-shift_64.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30652 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-09-28 20:48:45 +00:00
parent f120bec233
commit 7c395ad06f
1 changed files with 6 additions and 6 deletions
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12
lib/Target/PowerPC/PPCInstr64Bit.td
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@ -168,15 +168,15 @@ def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, G8RC:$rA, s16imm:$imm),
def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, G8RC:$src1, u16imm:$src2), def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, G8RC:$src1, u16imm:$src2),
"cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB),
"sld $rA, $rS, $rB", IntRotateD, "sld $rA, $rS, $rB", IntRotateD,
[(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64; [(set G8RC:$rA, (shl G8RC:$rS, GPRC:$rB))]>, isPPC64;
def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB),
"srd $rA, $rS, $rB", IntRotateD, "srd $rA, $rS, $rB", IntRotateD,
[(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64; [(set G8RC:$rA, (srl G8RC:$rS, GPRC:$rB))]>, isPPC64;
def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB),
"srad $rA, $rS, $rB", IntRotateD, "srad $rA, $rS, $rB", IntRotateD,
[(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64; [(set G8RC:$rA, (sra G8RC:$rS, GPRC:$rB))]>, isPPC64;
def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS), def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS),
"extsw $rA, $rS", IntGeneral, "extsw $rA, $rS", IntGeneral,
[(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64; [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;