6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-19 04:29:21 +00:00
Code Issues Projects Releases Wiki Activity

partial implementation of the ARM Addressing Mode 1

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30252 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2006-09-11 17:25:40 +00:00
parent 3fc68ccd83
commit 7cca7c5317
5 changed files with 74 additions and 37 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -54,6 +54,8 @@ namespace {
return "ARM Assembly Printer";
}
void printAddrMode1(const MachineInstr *MI, int opNum);
void printMemRegImm(const MachineInstr *MI, int opNum,
const char *Modifier = NULL) {
const MachineOperand &MO1 = MI->getOperand(opNum);
@ -155,6 +157,17 @@ bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
return false;
}
void ARMAsmPrinter::printAddrMode1(const MachineInstr *MI, int opNum) {
const MachineOperand &MO1 = MI->getOperand(opNum);
if(MO1.isImmediate()) {
printOperand(MI, opNum);
} else {
assert(MO1.isRegister());
printOperand(MI, opNum);
}
}
void ARMAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
const MachineOperand &MO = MI->getOperand (opNum);
const MRegisterInfo &RI = *TM.getRegisterInfo();

21
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -386,7 +386,7 @@ static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
SDOperand ARMCC = DAG.getConstant(DAGCCToARMCC(CC), MVT::i32);
SDOperand Cmp = DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS);
return DAG.getNode(ARMISD::SELECT, MVT::i32, FalseVal, TrueVal, ARMCC, Cmp);
return DAG.getNode(ARMISD::SELECT, MVT::i32, TrueVal, FalseVal, ARMCC, Cmp);
}
static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
@ -445,6 +445,7 @@ public:
SDNode *Select(SDOperand Op);
virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base);
bool SelectAddrMode1(SDOperand N, SDOperand &Arg);
// Include the pieces autogenerated from the target description.
#include "ARMGenDAGISel.inc"
@ -478,6 +479,24 @@ static bool isInt12Immediate(SDOperand Op, short &Imm) {
return isInt12Immediate(Op.Val, Imm);
}
bool ARMDAGToDAGISel::SelectAddrMode1(SDOperand N,
SDOperand &Arg) {
switch(N.getOpcode()) {
case ISD::CopyFromReg:
Arg = N;
return true;
case ISD::Constant: {
//TODO:check that we have a valid constant
int32_t t = cast<ConstantSDNode>(N)->getValue();
Arg = CurDAG->getTargetConstant(t, MVT::i32);
return true;
}
default:
std::cerr << "OpCode = " << N.getOpcode() << "\n";
assert(0);
}
}
//register plus/minus 12 bit offset
bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand N, SDOperand &Offset,
SDOperand &Base) {

14
lib/Target/ARM/ARMInstrInfo.cpp
View File

@ -33,15 +33,15 @@ bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg) const {
MachineOpCode oc = MI.getOpcode();
switch (oc) {
default:
return false;
case ARM::movrr:
case ARM::MOV:
assert(MI.getNumOperands() == 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
"Invalid ARM MOV instruction");
SrcReg = MI.getOperand(1).getReg();;
DstReg = MI.getOperand(0).getReg();;
return true;
if (MI.getOperand(1).isRegister()) {
SrcReg = MI.getOperand(1).getReg();
DstReg = MI.getOperand(0).getReg();
return true;
}
}
return false;
}

55
lib/Target/ARM/ARMInstrInfo.td
View File

@ -13,6 +13,12 @@
//===----------------------------------------------------------------------===//
// Address operands
def op_addr_mode1 : Operand<iPTR> {
let PrintMethod = "printAddrMode1";
let NumMIOperands = 1;
let MIOperandInfo = (ops ptr_rc);
}
def memri : Operand<iPTR> {
let PrintMethod = "printMemRegImm";
let NumMIOperands = 2;
@ -20,6 +26,9 @@ def memri : Operand<iPTR> {
}
// Define ARM specific addressing mode.
//Addressing Mode 1: data processing operands
def addr_mode1 : ComplexPattern<iPTR, 1, "SelectAddrMode1", [imm]>;
//register plus/minus 12 bit offset
def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex]>;
//register plus scaled register
@ -89,15 +98,12 @@ def str : InstARM<(ops IntRegs:$src, memri:$addr),
"str $src, $addr",
[(store IntRegs:$src, iaddr:$addr)]>;
def movrr : InstARM<(ops IntRegs:$dst, IntRegs:$src),
"mov $dst, $src", []>;
def MOV : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
"mov $dst, $src", [(set IntRegs:$dst, addr_mode1:$src)]>;
def movri : InstARM<(ops IntRegs:$dst, i32imm:$src),
"mov $dst, $src", [(set IntRegs:$dst, imm:$src)]>;
def addri : InstARM<(ops IntRegs:$dst, IntRegs:$a, i32imm:$b),
def ADD : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
"add $dst, $a, $b",
[(set IntRegs:$dst, (add IntRegs:$a, imm:$b))]>;
[(set IntRegs:$dst, (add IntRegs:$a, addr_mode1:$b))]>;
// "LEA" forms of add
def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
@ -105,14 +111,13 @@ def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
[(set IntRegs:$dst, iaddr:$addr)]>;
def subri : InstARM<(ops IntRegs:$dst, IntRegs:$a, i32imm:$b),
def SUB : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
"sub $dst, $a, $b",
[(set IntRegs:$dst, (sub IntRegs:$a, imm:$b))]>;
def andrr : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
"and $dst, $a, $b",
[(set IntRegs:$dst, (and IntRegs:$a, IntRegs:$b))]>;
[(set IntRegs:$dst, (sub IntRegs:$a, addr_mode1:$b))]>;
def AND : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
"and $dst, $a, $b",
[(set IntRegs:$dst, (and IntRegs:$a, addr_mode1:$b))]>;
// All arm data processing instructions have a shift. Maybe we don't have
// to implement this
@ -124,20 +129,20 @@ def SRA : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
"mov $dst, $a, asr $b",
[(set IntRegs:$dst, (sra IntRegs:$a, IntRegs:$b))]>;
def EOR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
"eor $dst, $a, $b",
[(set IntRegs:$dst, (xor IntRegs:$a, addr_mode1:$b))]>;
def eor_rr : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
"eor $dst, $a, $b",
[(set IntRegs:$dst, (xor IntRegs:$a, IntRegs:$b))]>;
def orr_rr : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
"orr $dst, $a, $b",
[(set IntRegs:$dst, (or IntRegs:$a, IntRegs:$b))]>;
def ORR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
"orr $dst, $a, $b",
[(set IntRegs:$dst, (or IntRegs:$a, addr_mode1:$b))]>;
let isTwoAddress = 1 in {
def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false, IntRegs:$true, CCOp:$cc),
def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false,
op_addr_mode1:$true, CCOp:$cc),
"mov$cc $dst, $true",
[(set IntRegs:$dst, (armselect IntRegs:$true, IntRegs:$false, imm:$cc))]>;
[(set IntRegs:$dst, (armselect addr_mode1:$true,
IntRegs:$false, imm:$cc))]>;
}
def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
@ -148,6 +153,6 @@ def b : InstARM<(ops brtarget:$dst),
"b $dst",
[(br bb:$dst)]>;
def cmp : InstARM<(ops IntRegs:$a, IntRegs:$b),
def cmp : InstARM<(ops IntRegs:$a, op_addr_mode1:$b),
"cmp $a, $b",
[(armcmp IntRegs:$a, IntRegs:$b)]>;
[(armcmp IntRegs:$a, addr_mode1:$b)]>;

8
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -48,7 +48,7 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const {
assert (RC == ARM::IntRegsRegisterClass);
BuildMI(MBB, I, ARM::movrr, 1, DestReg).addReg(SrcReg);
BuildMI(MBB, I, ARM::MOV, 1, DestReg).addReg(SrcReg);
}
MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,
@ -114,7 +114,7 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
// Insert a set of r12 with the full address
// r12 = r13 + offset
MachineBasicBlock *MBB2 = MI.getParent();
BuildMI(*MBB2, II, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
BuildMI(*MBB2, II, ARM::ADD, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
// Replace the FrameIndex with r12
MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12, false);
@ -140,7 +140,7 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
MFI->setStackSize(NumBytes);
//sub sp, sp, #NumBytes
BuildMI(MBB, MBBI, ARM::subri, 2, ARM::R13).addReg(ARM::R13).addImm(NumBytes);
BuildMI(MBB, MBBI, ARM::SUB, 2, ARM::R13).addReg(ARM::R13).addImm(NumBytes);
}
void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
@ -153,7 +153,7 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
int NumBytes = (int) MFI->getStackSize();
//add sp, sp, #NumBytes
BuildMI(MBB, MBBI, ARM::addri, 2, ARM::R13).addReg(ARM::R13).addImm(NumBytes);
BuildMI(MBB, MBBI, ARM::ADD, 2, ARM::R13).addReg(ARM::R13).addImm(NumBytes);
}
unsigned ARMRegisterInfo::getRARegister() const {