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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 04:29:21 +00:00
partial implementation of the ARM Addressing Mode 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30252 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -54,6 +54,8 @@ namespace {
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return "ARM Assembly Printer";
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}
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void printAddrMode1(const MachineInstr *MI, int opNum);
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void printMemRegImm(const MachineInstr *MI, int opNum,
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const char *Modifier = NULL) {
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const MachineOperand &MO1 = MI->getOperand(opNum);
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@ -155,6 +157,17 @@ bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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return false;
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}
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void ARMAsmPrinter::printAddrMode1(const MachineInstr *MI, int opNum) {
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const MachineOperand &MO1 = MI->getOperand(opNum);
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if(MO1.isImmediate()) {
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printOperand(MI, opNum);
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} else {
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assert(MO1.isRegister());
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printOperand(MI, opNum);
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}
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}
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void ARMAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
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const MachineOperand &MO = MI->getOperand (opNum);
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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@ -386,7 +386,7 @@ static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
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SDOperand ARMCC = DAG.getConstant(DAGCCToARMCC(CC), MVT::i32);
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SDOperand Cmp = DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS);
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return DAG.getNode(ARMISD::SELECT, MVT::i32, FalseVal, TrueVal, ARMCC, Cmp);
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return DAG.getNode(ARMISD::SELECT, MVT::i32, TrueVal, FalseVal, ARMCC, Cmp);
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}
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static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
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@ -445,6 +445,7 @@ public:
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SDNode *Select(SDOperand Op);
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base);
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bool SelectAddrMode1(SDOperand N, SDOperand &Arg);
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// Include the pieces autogenerated from the target description.
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#include "ARMGenDAGISel.inc"
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@ -478,6 +479,24 @@ static bool isInt12Immediate(SDOperand Op, short &Imm) {
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return isInt12Immediate(Op.Val, Imm);
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}
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bool ARMDAGToDAGISel::SelectAddrMode1(SDOperand N,
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SDOperand &Arg) {
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switch(N.getOpcode()) {
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case ISD::CopyFromReg:
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Arg = N;
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return true;
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case ISD::Constant: {
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//TODO:check that we have a valid constant
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int32_t t = cast<ConstantSDNode>(N)->getValue();
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Arg = CurDAG->getTargetConstant(t, MVT::i32);
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return true;
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}
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default:
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std::cerr << "OpCode = " << N.getOpcode() << "\n";
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assert(0);
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}
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}
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//register plus/minus 12 bit offset
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bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand N, SDOperand &Offset,
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SDOperand &Base) {
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@ -33,15 +33,15 @@ bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg) const {
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MachineOpCode oc = MI.getOpcode();
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switch (oc) {
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default:
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return false;
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case ARM::movrr:
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case ARM::MOV:
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assert(MI.getNumOperands() == 2 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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"Invalid ARM MOV instruction");
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SrcReg = MI.getOperand(1).getReg();;
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DstReg = MI.getOperand(0).getReg();;
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return true;
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if (MI.getOperand(1).isRegister()) {
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SrcReg = MI.getOperand(1).getReg();
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DstReg = MI.getOperand(0).getReg();
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return true;
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}
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}
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return false;
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}
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@ -13,6 +13,12 @@
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//===----------------------------------------------------------------------===//
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// Address operands
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def op_addr_mode1 : Operand<iPTR> {
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let PrintMethod = "printAddrMode1";
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let NumMIOperands = 1;
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let MIOperandInfo = (ops ptr_rc);
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}
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def memri : Operand<iPTR> {
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let PrintMethod = "printMemRegImm";
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let NumMIOperands = 2;
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@ -20,6 +26,9 @@ def memri : Operand<iPTR> {
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}
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// Define ARM specific addressing mode.
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//Addressing Mode 1: data processing operands
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def addr_mode1 : ComplexPattern<iPTR, 1, "SelectAddrMode1", [imm]>;
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//register plus/minus 12 bit offset
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def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex]>;
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//register plus scaled register
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@ -89,15 +98,12 @@ def str : InstARM<(ops IntRegs:$src, memri:$addr),
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"str $src, $addr",
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[(store IntRegs:$src, iaddr:$addr)]>;
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def movrr : InstARM<(ops IntRegs:$dst, IntRegs:$src),
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"mov $dst, $src", []>;
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def MOV : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
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"mov $dst, $src", [(set IntRegs:$dst, addr_mode1:$src)]>;
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def movri : InstARM<(ops IntRegs:$dst, i32imm:$src),
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"mov $dst, $src", [(set IntRegs:$dst, imm:$src)]>;
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def addri : InstARM<(ops IntRegs:$dst, IntRegs:$a, i32imm:$b),
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def ADD : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
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"add $dst, $a, $b",
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[(set IntRegs:$dst, (add IntRegs:$a, imm:$b))]>;
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[(set IntRegs:$dst, (add IntRegs:$a, addr_mode1:$b))]>;
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// "LEA" forms of add
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def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
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@ -105,14 +111,13 @@ def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
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[(set IntRegs:$dst, iaddr:$addr)]>;
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def subri : InstARM<(ops IntRegs:$dst, IntRegs:$a, i32imm:$b),
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def SUB : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
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"sub $dst, $a, $b",
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[(set IntRegs:$dst, (sub IntRegs:$a, imm:$b))]>;
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def andrr : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
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"and $dst, $a, $b",
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[(set IntRegs:$dst, (and IntRegs:$a, IntRegs:$b))]>;
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[(set IntRegs:$dst, (sub IntRegs:$a, addr_mode1:$b))]>;
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def AND : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
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"and $dst, $a, $b",
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[(set IntRegs:$dst, (and IntRegs:$a, addr_mode1:$b))]>;
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// All arm data processing instructions have a shift. Maybe we don't have
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// to implement this
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@ -124,20 +129,20 @@ def SRA : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
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"mov $dst, $a, asr $b",
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[(set IntRegs:$dst, (sra IntRegs:$a, IntRegs:$b))]>;
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def EOR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
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"eor $dst, $a, $b",
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[(set IntRegs:$dst, (xor IntRegs:$a, addr_mode1:$b))]>;
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def eor_rr : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
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"eor $dst, $a, $b",
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[(set IntRegs:$dst, (xor IntRegs:$a, IntRegs:$b))]>;
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def orr_rr : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
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"orr $dst, $a, $b",
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[(set IntRegs:$dst, (or IntRegs:$a, IntRegs:$b))]>;
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def ORR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
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"orr $dst, $a, $b",
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[(set IntRegs:$dst, (or IntRegs:$a, addr_mode1:$b))]>;
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let isTwoAddress = 1 in {
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def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false, IntRegs:$true, CCOp:$cc),
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def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false,
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op_addr_mode1:$true, CCOp:$cc),
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"mov$cc $dst, $true",
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[(set IntRegs:$dst, (armselect IntRegs:$true, IntRegs:$false, imm:$cc))]>;
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[(set IntRegs:$dst, (armselect addr_mode1:$true,
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IntRegs:$false, imm:$cc))]>;
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}
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def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
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@ -148,6 +153,6 @@ def b : InstARM<(ops brtarget:$dst),
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"b $dst",
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[(br bb:$dst)]>;
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def cmp : InstARM<(ops IntRegs:$a, IntRegs:$b),
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def cmp : InstARM<(ops IntRegs:$a, op_addr_mode1:$b),
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"cmp $a, $b",
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[(armcmp IntRegs:$a, IntRegs:$b)]>;
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[(armcmp IntRegs:$a, addr_mode1:$b)]>;
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@ -48,7 +48,7 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const {
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assert (RC == ARM::IntRegsRegisterClass);
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BuildMI(MBB, I, ARM::movrr, 1, DestReg).addReg(SrcReg);
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BuildMI(MBB, I, ARM::MOV, 1, DestReg).addReg(SrcReg);
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}
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MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,
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@ -114,7 +114,7 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
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// Insert a set of r12 with the full address
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// r12 = r13 + offset
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MachineBasicBlock *MBB2 = MI.getParent();
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BuildMI(*MBB2, II, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
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BuildMI(*MBB2, II, ARM::ADD, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
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// Replace the FrameIndex with r12
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MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12, false);
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@ -140,7 +140,7 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
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MFI->setStackSize(NumBytes);
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//sub sp, sp, #NumBytes
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BuildMI(MBB, MBBI, ARM::subri, 2, ARM::R13).addReg(ARM::R13).addImm(NumBytes);
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BuildMI(MBB, MBBI, ARM::SUB, 2, ARM::R13).addReg(ARM::R13).addImm(NumBytes);
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}
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void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
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@ -153,7 +153,7 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
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int NumBytes = (int) MFI->getStackSize();
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//add sp, sp, #NumBytes
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BuildMI(MBB, MBBI, ARM::addri, 2, ARM::R13).addReg(ARM::R13).addImm(NumBytes);
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BuildMI(MBB, MBBI, ARM::ADD, 2, ARM::R13).addReg(ARM::R13).addImm(NumBytes);
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}
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unsigned ARMRegisterInfo::getRARegister() const {
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