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https://github.com/c64scene-ar/llvm-6502.git
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Div, Rem int/unsigned int
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165783 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler
parent
6df933e371
commit
7d90d4d709
@ -58,12 +58,22 @@ void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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unsigned Opc = 0, ZeroReg = 0;
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unsigned Opc = 0;
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if (Mips::CPU16RegsRegClass.contains(DestReg) &&
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Mips::CPURegsRegClass.contains(SrcReg))
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Opc = Mips::MoveR3216;
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else if (Mips::CPURegsRegClass.contains(DestReg) &&
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Mips::CPU16RegsRegClass.contains(SrcReg))
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Opc = Mips::Move32R16;
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else if ((SrcReg == Mips::HI) &&
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(Mips::CPU16RegsRegClass.contains(DestReg)))
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Opc = Mips::Mfhi16, SrcReg = 0;
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else if ((SrcReg == Mips::LO) &&
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(Mips::CPU16RegsRegClass.contains(DestReg)))
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Opc = Mips::Mflo16, SrcReg = 0;
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if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
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if (Mips::CPURegsRegClass.contains(SrcReg))
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Opc = Mips::Move32R16;
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}
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assert(Opc && "Cannot copy registers");
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@ -72,9 +82,6 @@ void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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if (DestReg)
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MIB.addReg(DestReg, RegState::Define);
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if (ZeroReg)
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MIB.addReg(ZeroReg);
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if (SrcReg)
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MIB.addReg(SrcReg, getKillRegState(KillSrc));
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}
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@ -118,6 +118,14 @@ class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
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FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rx, $ry"), [], itin> {
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}
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//
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// maybe refactor but need a $zero as a dummy first parameter
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//
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class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> :
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FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
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class FRR16_M_ins<bits<5> f, string asmstr,
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InstrItinClass itin> :
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FRR16<f, (outs CPU16Regs:$rx), (ins),
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@ -196,6 +204,24 @@ def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
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// To do a bitwise logical AND.
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def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
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//
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// Format: DIV rx, ry MIPS16e
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// Purpose: Divide Word
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// To divide 32-bit signed integers.
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//
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def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> {
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let Defs = [HI, LO];
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}
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//
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// Format: DIVU rx, ry MIPS16e
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// Purpose: Divide Unsigned Word
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// To divide 32-bit unsigned integers.
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//
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def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
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let Defs = [HI, LO];
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}
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//
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// Format: JR ra MIPS16e
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@ -551,5 +577,20 @@ def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
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// Small immediates
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def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
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//
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// MipsDivRem
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//
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def: Mips16Pat
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<(MipsDivRem CPU16Regs:$rx, CPU16Regs:$ry),
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(DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
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//
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// MipsDivRemU
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//
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def: Mips16Pat
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<(MipsDivRemU CPU16Regs:$rx, CPU16Regs:$ry),
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(DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
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def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
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(AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
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18
test/CodeGen/Mips/div.ll
Normal file
18
test/CodeGen/Mips/div.ll
Normal file
@ -0,0 +1,18 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@iiii = global i32 100, align 4
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@jjjj = global i32 -4, align 4
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@kkkk = common global i32 0, align 4
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define void @test() nounwind {
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entry:
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%0 = load i32* @iiii, align 4
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%1 = load i32* @jjjj, align 4
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%div = sdiv i32 %0, %1
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; 16: div $zero, ${{[0-9]+}}, ${{[0-9]+}}
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; 16: mflo ${{[0-9]+}}
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store i32 %div, i32* @kkkk, align 4
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ret void
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}
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21
test/CodeGen/Mips/div_rem.ll
Normal file
21
test/CodeGen/Mips/div_rem.ll
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@ -0,0 +1,21 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@iiii = global i32 103, align 4
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@jjjj = global i32 -4, align 4
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@kkkk = common global i32 0, align 4
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@llll = common global i32 0, align 4
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define void @test() nounwind {
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entry:
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%0 = load i32* @iiii, align 4
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%1 = load i32* @jjjj, align 4
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%div = sdiv i32 %0, %1
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store i32 %div, i32* @kkkk, align 4
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%rem = srem i32 %0, %1
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; 16: div $zero, ${{[0-9]+}}, ${{[0-9]+}}
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; 16: mflo ${{[0-9]+}}
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; 16: mfhi ${{[0-9]+}}
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store i32 %rem, i32* @llll, align 4
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ret void
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}
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18
test/CodeGen/Mips/divu.ll
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18
test/CodeGen/Mips/divu.ll
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@ -0,0 +1,18 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@iiii = global i32 100, align 4
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@jjjj = global i32 4, align 4
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@kkkk = common global i32 0, align 4
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define void @test() nounwind {
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entry:
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%0 = load i32* @iiii, align 4
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%1 = load i32* @jjjj, align 4
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%div = udiv i32 %0, %1
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; 16: divu $zero, ${{[0-9]+}}, ${{[0-9]+}}
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; 16: mflo ${{[0-9]+}}
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store i32 %div, i32* @kkkk, align 4
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ret void
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}
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23
test/CodeGen/Mips/divu_remu.ll
Normal file
23
test/CodeGen/Mips/divu_remu.ll
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@ -0,0 +1,23 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@iiii = global i32 103, align 4
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@jjjj = global i32 4, align 4
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@kkkk = common global i32 0, align 4
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@llll = common global i32 0, align 4
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define void @test() nounwind {
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entry:
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%0 = load i32* @iiii, align 4
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%1 = load i32* @jjjj, align 4
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%div = udiv i32 %0, %1
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store i32 %div, i32* @kkkk, align 4
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%rem = urem i32 %0, %1
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; 16: divu $zero, ${{[0-9]+}}, ${{[0-9]+}}
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; 16: mflo ${{[0-9]+}}
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; 16: mfhi ${{[0-9]+}}
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store i32 %rem, i32* @llll, align 4
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ret void
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}
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19
test/CodeGen/Mips/rem.ll
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19
test/CodeGen/Mips/rem.ll
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@ -0,0 +1,19 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@iiii = global i32 103, align 4
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@jjjj = global i32 -4, align 4
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@kkkk = common global i32 0, align 4
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define void @test() nounwind {
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entry:
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%0 = load i32* @iiii, align 4
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%1 = load i32* @jjjj, align 4
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%rem = srem i32 %0, %1
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; 16: div $zero, ${{[0-9]+}}, ${{[0-9]+}}
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; 16: mfhi ${{[0-9]+}}
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store i32 %rem, i32* @kkkk, align 4
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ret void
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}
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18
test/CodeGen/Mips/remu.ll
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18
test/CodeGen/Mips/remu.ll
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@ -0,0 +1,18 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@iiii = global i32 103, align 4
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@jjjj = global i32 4, align 4
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@kkkk = common global i32 0, align 4
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@.str = private unnamed_addr constant [15 x i8] c"%u = %u %% %u\0A\00", align 1
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define void @test() nounwind {
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entry:
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%0 = load i32* @iiii, align 4
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%1 = load i32* @jjjj, align 4
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%rem = urem i32 %0, %1
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; 16: divu $zero, ${{[0-9]+}}, ${{[0-9]+}}
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; 16: mfhi ${{[0-9]+}}
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store i32 %rem, i32* @kkkk, align 4
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ret void
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}
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