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Div, Rem int/unsigned int

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165783 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler
2012-10-12 02:01:09 +00:00
parent 6df933e371
commit 7d90d4d709
8 changed files with 173 additions and 8 deletions
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23
lib/Target/Mips/Mips16InstrInfo.cpp
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@@ -58,12 +58,22 @@ void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const {
unsigned Opc = 0, ZeroReg = 0;
unsigned Opc = 0;
if (Mips::CPU16RegsRegClass.contains(DestReg) &&
Mips::CPURegsRegClass.contains(SrcReg))
Opc = Mips::MoveR3216;
else if (Mips::CPURegsRegClass.contains(DestReg) &&
Mips::CPU16RegsRegClass.contains(SrcReg))
Opc = Mips::Move32R16;
else if ((SrcReg == Mips::HI) &&
(Mips::CPU16RegsRegClass.contains(DestReg)))
Opc = Mips::Mfhi16, SrcReg = 0;
else if ((SrcReg == Mips::LO) &&
(Mips::CPU16RegsRegClass.contains(DestReg)))
Opc = Mips::Mflo16, SrcReg = 0;
if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
if (Mips::CPURegsRegClass.contains(SrcReg))
Opc = Mips::Move32R16;
}
assert(Opc && "Cannot copy registers");
@@ -72,9 +82,6 @@ void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
if (DestReg)
MIB.addReg(DestReg, RegState::Define);
if (ZeroReg)
MIB.addReg(ZeroReg);
if (SrcReg)
MIB.addReg(SrcReg, getKillRegState(KillSrc));
}