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[mips] Enable code generation for MIPS-III.
Summary: This commit enables the MIPS-III target and adds support for code generation of SELECT nodes. We have to use pseudo-instructions with custom inserters for these nodes as MIPS-III CPUs do not have conditional-move instructions. Depends on D6212 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6464 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224128 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vasileios Kalintiris
parent
a4f5a5525d
commit
7db2065236
@ -284,13 +284,19 @@ let usesCustomInserter = 1 in {
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}
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def PseudoSELECT_I : Select_Pseudo<GPR32Opnd>;
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def PseudoSELECT_I64 : Select_Pseudo<GPR64Opnd>;
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def PseudoSELECT_S : Select_Pseudo<FGR32Opnd>;
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def PseudoSELECT_D32 : Select_Pseudo<AFGR64Opnd>;
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def PseudoSELECT_D32 : Select_Pseudo<AFGR64Opnd>, FGR_32;
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def PseudoSELECT_D64 : Select_Pseudo<FGR64Opnd>, FGR_64;
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def PseudoSELECTFP_T_I : SelectFP_Pseudo_T<GPR32Opnd>;
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def PseudoSELECTFP_T_I64 : SelectFP_Pseudo_T<GPR64Opnd>;
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def PseudoSELECTFP_T_S : SelectFP_Pseudo_T<FGR32Opnd>;
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def PseudoSELECTFP_T_D32 : SelectFP_Pseudo_T<AFGR64Opnd>;
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def PseudoSELECTFP_T_D32 : SelectFP_Pseudo_T<AFGR64Opnd>, FGR_32;
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def PseudoSELECTFP_T_D64 : SelectFP_Pseudo_T<FGR64Opnd>, FGR_64;
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def PseudoSELECTFP_F_I : SelectFP_Pseudo_F<GPR32Opnd>;
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def PseudoSELECTFP_F_I64 : SelectFP_Pseudo_F<GPR64Opnd>;
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def PseudoSELECTFP_F_S : SelectFP_Pseudo_F<FGR32Opnd>;
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def PseudoSELECTFP_F_D32 : SelectFP_Pseudo_F<AFGR64Opnd>;
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def PseudoSELECTFP_F_D32 : SelectFP_Pseudo_F<AFGR64Opnd>, FGR_32;
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def PseudoSELECTFP_F_D64 : SelectFP_Pseudo_F<FGR64Opnd>, FGR_64;
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@ -947,16 +947,22 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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return emitSEL_D(MI, BB);
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case Mips::PseudoSELECT_I:
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case Mips::PseudoSELECT_I64:
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case Mips::PseudoSELECT_S:
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case Mips::PseudoSELECT_D32:
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case Mips::PseudoSELECT_D64:
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return emitPseudoSELECT(MI, BB, false, Mips::BNE);
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case Mips::PseudoSELECTFP_F_I:
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case Mips::PseudoSELECTFP_F_I64:
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case Mips::PseudoSELECTFP_F_S:
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case Mips::PseudoSELECTFP_F_D32:
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case Mips::PseudoSELECTFP_F_D64:
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return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
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case Mips::PseudoSELECTFP_T_I:
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case Mips::PseudoSELECTFP_T_I64:
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case Mips::PseudoSELECTFP_T_S:
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case Mips::PseudoSELECTFP_T_D32:
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case Mips::PseudoSELECTFP_T_D64:
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return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
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}
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}
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@ -129,14 +129,10 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
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if (MipsArchVersion == MipsDefault)
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MipsArchVersion = Mips32;
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// Don't even attempt to generate code for MIPS-I, MIPS-III and MIPS-V.
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// They have not been tested and currently exist for the integrated
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// assembler only.
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// Don't even attempt to generate code for MIPS-I and MIPS-V. They have not
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// been tested and currently exist for the integrated assembler only.
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if (MipsArchVersion == Mips1)
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report_fatal_error("Code generation for MIPS-I is not implemented", false);
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if (MipsArchVersion == Mips3)
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report_fatal_error("Code generation for MIPS-III is not implemented",
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false);
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if (MipsArchVersion == Mips5)
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report_fatal_error("Code generation for MIPS-V is not implemented", false);
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@ -1,5 +1,5 @@
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; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=M2
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; RUN: -check-prefix=ALL -check-prefix=M2 -check-prefix=M2-M3
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; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV \
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; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R1
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@ -8,6 +8,8 @@
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; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2
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; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32
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; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3
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; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
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; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
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@ -22,13 +24,13 @@ define signext i1 @tst_select_i1_i1(i1 signext %s,
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entry:
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; ALL-LABEL: tst_select_i1_i1:
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; M2: andi $[[T0:[0-9]+]], $4, 1
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; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M2: nop
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; M2: move $5, $6
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; M2: $[[BB0]]:
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; M2: jr $ra
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; M2: move $2, $5
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; M2-M3: andi $[[T0:[0-9]+]], $4, 1
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; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M2-M3: nop
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; M2-M3: move $5, $6
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; M2-M3: $[[BB0]]:
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; M2-M3: jr $ra
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; M2-M3: move $2, $5
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; CMOV: andi $[[T0:[0-9]+]], $4, 1
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; CMOV: movn $6, $5, $[[T0]]
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@ -47,13 +49,13 @@ define signext i8 @tst_select_i1_i8(i1 signext %s,
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entry:
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; ALL-LABEL: tst_select_i1_i8:
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; M2: andi $[[T0:[0-9]+]], $4, 1
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; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M2: nop
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; M2: move $5, $6
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; M2: $[[BB0]]:
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; M2: jr $ra
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; M2: move $2, $5
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; M2-M3: andi $[[T0:[0-9]+]], $4, 1
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; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M2-M3: nop
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; M2-M3: move $5, $6
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; M2-M3: $[[BB0]]:
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; M2-M3: jr $ra
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; M2-M3: move $2, $5
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; CMOV: andi $[[T0:[0-9]+]], $4, 1
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; CMOV: movn $6, $5, $[[T0]]
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@ -72,13 +74,13 @@ define signext i32 @tst_select_i1_i32(i1 signext %s,
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entry:
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; ALL-LABEL: tst_select_i1_i32:
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; M2: andi $[[T0:[0-9]+]], $4, 1
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; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M2: nop
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; M2: move $5, $6
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; M2: $[[BB0]]:
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; M2: jr $ra
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; M2: move $2, $5
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; M2-M3: andi $[[T0:[0-9]+]], $4, 1
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; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M2-M3: nop
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; M2-M3: move $5, $6
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; M2-M3: $[[BB0]]:
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; M2-M3: jr $ra
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; M2-M3: move $2, $5
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; CMOV: andi $[[T0:[0-9]+]], $4, 1
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; CMOV: movn $6, $5, $[[T0]]
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@ -127,6 +129,14 @@ entry:
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; SEL-32: seleqz $[[T6:[0-9]+]], $[[T5]], $[[T0]]
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; SEL-32: or $3, $[[T4]], $[[T6]]
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; M3: andi $[[T0:[0-9]+]], $4, 1
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; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M3: nop
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; M3: move $5, $6
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; M3: $[[BB0]]:
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; M3: jr $ra
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; M3: move $2, $5
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; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
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; CMOV-64: movn $6, $5, $[[T0]]
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; CMOV-64: move $2, $6
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@ -145,14 +155,16 @@ define float @tst_select_i1_float(i1 signext %s, float %x, float %y) {
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entry:
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; ALL-LABEL: tst_select_i1_float:
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; M2: andi $[[T0:[0-9]+]], $4, 1
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; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M2: nop
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; M2-M3: andi $[[T0:[0-9]+]], $4, 1
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; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M2-M3: nop
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; M2: jr $ra
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; M2: mtc1 $6, $f0
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; M2: $[[BB0]]:
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; M2: jr $ra
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; M3: mov.s $f13, $f14
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; M2-M3: $[[BB0]]:
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; M2-M3: jr $ra
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; M2: mtc1 $5, $f0
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; M3: mov.s $f0, $f13
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; CMOV-32: mtc1 $6, $f0
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; CMOV-32: mtc1 $5, $f1
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@ -179,13 +191,14 @@ define float @tst_select_i1_float_reordered(float %x, float %y,
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entry:
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; ALL-LABEL: tst_select_i1_float_reordered:
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; M2: andi $[[T0:[0-9]+]], $6, 1
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; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M2: nop
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; M2-M3: andi $[[T0:[0-9]+]], $6, 1
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; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M2-M3: nop
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; M2: mov.s $f12, $f14
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; M2: $[[BB0]]:
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; M2: jr $ra
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; M2: mov.s $f0, $f12
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; M3: mov.s $f12, $f13
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; M2-M3: $[[BB0]]:
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; M2-M3: jr $ra
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; M2-M3: mov.s $f0, $f12
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; CMOV-32: andi $[[T0:[0-9]+]], $6, 1
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; CMOV-32: movn.s $f14, $f12, $[[T0]]
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@ -232,6 +245,14 @@ entry:
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; SEL-32: mtc1 $4, $f0
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; SEL-32: sel.d $f0, $[[F1]], $[[F0]]
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; M3: andi $[[T0:[0-9]+]], $4, 1
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; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M3: nop
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; M3: mov.d $f13, $f14
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; M3: $[[BB0]]:
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; M3: jr $ra
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; M3: mov.d $f0, $f13
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; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
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; CMOV-64: movn.d $f14, $f13, $[[T0]]
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; CMOV-64: mov.d $f0, $f14
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@ -265,6 +286,14 @@ entry:
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; SEL-32: mtc1 $[[T0]], $f0
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; SEL-32: sel.d $f0, $f14, $f12
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; M3: andi $[[T0:[0-9]+]], $6, 1
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; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M3: nop
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; M3: mov.d $f12, $f13
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; M3: $[[BB0]]:
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; M3: jr $ra
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; M3: mov.d $f0, $f12
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; CMOV-64: andi $[[T0:[0-9]+]], $6, 1
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; CMOV-64: movn.d $f13, $f12, $[[T0]]
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; CMOV-64: mov.d $f0, $f13
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@ -280,12 +309,14 @@ entry:
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; ALL-LABEL: tst_select_fcmp_olt_float:
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; M2: c.olt.s $f12, $f14
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; M2: bc1t $[[BB0:BB[0-9_]+]]
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; M2: nop
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; M3: c.olt.s $f12, $f13
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; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
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; M2-M3: nop
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; M2: mov.s $f12, $f14
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; M2: $[[BB0]]:
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; M2: jr $ra
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; M2: mov.s $f0, $f12
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; M3: mov.s $f12, $f13
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; M2-M3: $[[BB0]]:
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; M2-M3: jr $ra
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; M2-M3: mov.s $f0, $f12
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; CMOV-32: c.olt.s $f12, $f14
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; CMOV-32: movt.s $f14, $f12, $fcc0
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@ -310,12 +341,14 @@ entry:
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; ALL-LABEL: tst_select_fcmp_ole_float:
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; M2: c.ole.s $f12, $f14
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; M2: bc1t $[[BB0:BB[0-9_]+]]
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; M2: nop
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; M3: c.ole.s $f12, $f13
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; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
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; M2-M3: nop
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; M2: mov.s $f12, $f14
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; M2: $[[BB0]]:
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; M2: jr $ra
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; M2: mov.s $f0, $f12
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; M3: mov.s $f12, $f13
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; M2-M3: $[[BB0]]:
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; M2-M3: jr $ra
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; M2-M3: mov.s $f0, $f12
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; CMOV-32: c.ole.s $f12, $f14
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; CMOV-32: movt.s $f14, $f12, $fcc0
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@ -340,12 +373,14 @@ entry:
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; ALL-LABEL: tst_select_fcmp_ogt_float:
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; M2: c.ule.s $f12, $f14
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; M2: bc1f $[[BB0:BB[0-9_]+]]
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; M2: nop
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; M3: c.ule.s $f12, $f13
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; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
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; M2-M3: nop
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; M2: mov.s $f12, $f14
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; M2: $[[BB0]]:
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; M2: jr $ra
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; M2: mov.s $f0, $f12
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; M3: mov.s $f12, $f13
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; M2-M3: $[[BB0]]:
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; M2-M3: jr $ra
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; M2-M3: mov.s $f0, $f12
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; CMOV-32: c.ule.s $f12, $f14
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; CMOV-32: movf.s $f14, $f12, $fcc0
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@ -370,12 +405,14 @@ entry:
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; ALL-LABEL: tst_select_fcmp_oge_float:
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; M2: c.ult.s $f12, $f14
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; M2: bc1f $[[BB0:BB[0-9_]+]]
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; M2: nop
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; M3: c.ult.s $f12, $f13
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; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
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; M2-M3: nop
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; M2: mov.s $f12, $f14
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; M2: $[[BB0]]:
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; M2: jr $ra
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; M2: mov.s $f0, $f12
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; M3: mov.s $f12, $f13
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; M2-M3: $[[BB0]]:
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; M2-M3: jr $ra
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; M2-M3: mov.s $f0, $f12
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; CMOV-32: c.ult.s $f12, $f14
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; CMOV-32: movf.s $f14, $f12, $fcc0
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@ -400,12 +437,14 @@ entry:
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; ALL-LABEL: tst_select_fcmp_oeq_float:
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; M2: c.eq.s $f12, $f14
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; M2: bc1t $[[BB0:BB[0-9_]+]]
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; M2: nop
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; M3: c.eq.s $f12, $f13
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; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
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; M2-M3: nop
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; M2: mov.s $f12, $f14
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; M2: $[[BB0]]:
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; M2: jr $ra
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; M2: mov.s $f0, $f12
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; M3: mov.s $f12, $f13
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; M2-M3: $[[BB0]]:
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; M2-M3: jr $ra
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; M2-M3: mov.s $f0, $f12
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; CMOV-32: c.eq.s $f12, $f14
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; CMOV-32: movt.s $f14, $f12, $fcc0
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@ -430,12 +469,14 @@ entry:
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; ALL-LABEL: tst_select_fcmp_one_float:
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; M2: c.ueq.s $f12, $f14
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; M2: bc1f $[[BB0:BB[0-9_]+]]
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; M2: nop
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; M3: c.ueq.s $f12, $f13
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; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
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; M2-M3: nop
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; M2: mov.s $f12, $f14
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; M2: $[[BB0]]:
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; M2: jr $ra
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; M2: mov.s $f0, $f12
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; M3: mov.s $f12, $f13
|
||||
; M2-M3: $[[BB0]]:
|
||||
; M2-M3: jr $ra
|
||||
; M2-M3: mov.s $f0, $f12
|
||||
|
||||
; CMOV-32: c.ueq.s $f12, $f14
|
||||
; CMOV-32: movf.s $f14, $f12, $fcc0
|
||||
@ -467,12 +508,14 @@ entry:
|
||||
; ALL-LABEL: tst_select_fcmp_olt_double:
|
||||
|
||||
; M2: c.olt.d $f12, $f14
|
||||
; M2: bc1t $[[BB0:BB[0-9_]+]]
|
||||
; M2: nop
|
||||
; M3: c.olt.d $f12, $f13
|
||||
; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
|
||||
; M2-M3: nop
|
||||
; M2: mov.d $f12, $f14
|
||||
; M2: $[[BB0]]:
|
||||
; M2: jr $ra
|
||||
; M2: mov.d $f0, $f12
|
||||
; M3: mov.d $f12, $f13
|
||||
; M2-M3: $[[BB0]]:
|
||||
; M2-M3: jr $ra
|
||||
; M2-M3: mov.d $f0, $f12
|
||||
|
||||
; CMOV-32: c.olt.d $f12, $f14
|
||||
; CMOV-32: movt.d $f14, $f12, $fcc0
|
||||
@ -497,12 +540,14 @@ entry:
|
||||
; ALL-LABEL: tst_select_fcmp_ole_double:
|
||||
|
||||
; M2: c.ole.d $f12, $f14
|
||||
; M2: bc1t $[[BB0:BB[0-9_]+]]
|
||||
; M2: nop
|
||||
; M3: c.ole.d $f12, $f13
|
||||
; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
|
||||
; M2-M3: nop
|
||||
; M2: mov.d $f12, $f14
|
||||
; M2: $[[BB0]]:
|
||||
; M2: jr $ra
|
||||
; M2: mov.d $f0, $f12
|
||||
; M3: mov.d $f12, $f13
|
||||
; M2-M3: $[[BB0]]:
|
||||
; M2-M3: jr $ra
|
||||
; M2-M3: mov.d $f0, $f12
|
||||
|
||||
; CMOV-32: c.ole.d $f12, $f14
|
||||
; CMOV-32: movt.d $f14, $f12, $fcc0
|
||||
@ -527,12 +572,14 @@ entry:
|
||||
; ALL-LABEL: tst_select_fcmp_ogt_double:
|
||||
|
||||
; M2: c.ule.d $f12, $f14
|
||||
; M2: bc1f $[[BB0:BB[0-9_]+]]
|
||||
; M2: nop
|
||||
; M3: c.ule.d $f12, $f13
|
||||
; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
|
||||
; M2-M3: nop
|
||||
; M2: mov.d $f12, $f14
|
||||
; M2: $[[BB0]]:
|
||||
; M2: jr $ra
|
||||
; M2: mov.d $f0, $f12
|
||||
; M3: mov.d $f12, $f13
|
||||
; M2-M3: $[[BB0]]:
|
||||
; M2-M3: jr $ra
|
||||
; M2-M3: mov.d $f0, $f12
|
||||
|
||||
; CMOV-32: c.ule.d $f12, $f14
|
||||
; CMOV-32: movf.d $f14, $f12, $fcc0
|
||||
@ -557,12 +604,14 @@ entry:
|
||||
; ALL-LABEL: tst_select_fcmp_oge_double:
|
||||
|
||||
; M2: c.ult.d $f12, $f14
|
||||
; M2: bc1f $[[BB0:BB[0-9_]+]]
|
||||
; M2: nop
|
||||
; M3: c.ult.d $f12, $f13
|
||||
; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
|
||||
; M2-M3: nop
|
||||
; M2: mov.d $f12, $f14
|
||||
; M2: $[[BB0]]:
|
||||
; M2: jr $ra
|
||||
; M2: mov.d $f0, $f12
|
||||
; M3: mov.d $f12, $f13
|
||||
; M2-M3: $[[BB0]]:
|
||||
; M2-M3: jr $ra
|
||||
; M2-M3: mov.d $f0, $f12
|
||||
|
||||
; CMOV-32: c.ult.d $f12, $f14
|
||||
; CMOV-32: movf.d $f14, $f12, $fcc0
|
||||
@ -587,12 +636,14 @@ entry:
|
||||
; ALL-LABEL: tst_select_fcmp_oeq_double:
|
||||
|
||||
; M2: c.eq.d $f12, $f14
|
||||
; M2: bc1t $[[BB0:BB[0-9_]+]]
|
||||
; M2: nop
|
||||
; M3: c.eq.d $f12, $f13
|
||||
; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
|
||||
; M2-M3: nop
|
||||
; M2: mov.d $f12, $f14
|
||||
; M2: $[[BB0]]:
|
||||
; M2: jr $ra
|
||||
; M2: mov.d $f0, $f12
|
||||
; M3: mov.d $f12, $f13
|
||||
; M2-M3: $[[BB0]]:
|
||||
; M2-M3: jr $ra
|
||||
; M2-M3: mov.d $f0, $f12
|
||||
|
||||
; CMOV-32: c.eq.d $f12, $f14
|
||||
; CMOV-32: movt.d $f14, $f12, $fcc0
|
||||
@ -617,12 +668,14 @@ entry:
|
||||
; ALL-LABEL: tst_select_fcmp_one_double:
|
||||
|
||||
; M2: c.ueq.d $f12, $f14
|
||||
; M2: bc1f $[[BB0:BB[0-9_]+]]
|
||||
; M2: nop
|
||||
; M3: c.ueq.d $f12, $f13
|
||||
; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
|
||||
; M2-M3: nop
|
||||
; M2: mov.d $f12, $f14
|
||||
; M2: $[[BB0]]:
|
||||
; M2: jr $ra
|
||||
; M2: mov.d $f0, $f12
|
||||
; M3: mov.d $f12, $f13
|
||||
; M2-M3: $[[BB0]]:
|
||||
; M2-M3: jr $ra
|
||||
; M2-M3: mov.d $f0, $f12
|
||||
|
||||
; CMOV-32: c.ueq.d $f12, $f14
|
||||
; CMOV-32: movf.d $f14, $f12, $fcc0
|
||||
|
||||
Loading…
Reference in New Issue
Block a user