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Expand VMOVQQQQ pseudo instructions.

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Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed.  Our register allocator must be awesome!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137551 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2011-08-13 05:14:55 +00:00
parent 53b2b73643
commit 7dcd04abe0
2 changed files with 59 additions and 0 deletions
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46
lib/Target/ARM/ARMExpandPseudoInsts.cpp
View File

@ -998,6 +998,52 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
return true;
}
case ARM::VMOVQQQQ: {
unsigned DstReg = MI.getOperand(0).getReg();
bool DstIsDead = MI.getOperand(0).isDead();
unsigned Dst0 = TRI->getSubReg(DstReg, ARM::qsub_0);
unsigned Dst1 = TRI->getSubReg(DstReg, ARM::qsub_1);
unsigned Dst2 = TRI->getSubReg(DstReg, ARM::qsub_2);
unsigned Dst3 = TRI->getSubReg(DstReg, ARM::qsub_3);
unsigned SrcReg = MI.getOperand(1).getReg();
bool SrcIsKill = MI.getOperand(1).isKill();
unsigned Src0 = TRI->getSubReg(SrcReg, ARM::qsub_0);
unsigned Src1 = TRI->getSubReg(SrcReg, ARM::qsub_1);
unsigned Src2 = TRI->getSubReg(SrcReg, ARM::qsub_2);
unsigned Src3 = TRI->getSubReg(SrcReg, ARM::qsub_3);
MachineInstrBuilder Mov0 =
AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(ARM::VORRq))
.addReg(Dst0,
RegState::Define | getDeadRegState(DstIsDead))
.addReg(Src0, getKillRegState(SrcIsKill))
.addReg(Src0, getKillRegState(SrcIsKill)));
MachineInstrBuilder Mov1 =
AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(ARM::VORRq))
.addReg(Dst1,
RegState::Define | getDeadRegState(DstIsDead))
.addReg(Src1, getKillRegState(SrcIsKill))
.addReg(Src1, getKillRegState(SrcIsKill)));
MachineInstrBuilder Mov2 =
AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(ARM::VORRq))
.addReg(Dst2,
RegState::Define | getDeadRegState(DstIsDead))
.addReg(Src2, getKillRegState(SrcIsKill))
.addReg(Src2, getKillRegState(SrcIsKill)));
MachineInstrBuilder Mov3 =
AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(ARM::VORRq))
.addReg(Dst3,
RegState::Define | getDeadRegState(DstIsDead))
.addReg(Src3, getKillRegState(SrcIsKill))
.addReg(Src3, getKillRegState(SrcIsKill)));
TransferImpOps(MI, Mov0, Mov3);
MI.eraseFromParent();
return true;
}
case ARM::VLDMQIA: {
unsigned NewOpc = ARM::VLDMDIA;
MachineInstrBuilder MIB =

13
test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll Normal file
View File

@ -0,0 +1,13 @@
; RUN: llc %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 -O0
; The following test is supposed to produce a VMOVQQQQ pseudo instruction.
; Make sure that it gets expanded; otherwise, the compile fails when trying
; to print the pseudo-instruction.
define void @test_vmovqqqq_pseudo() nounwind ssp {
entry:
%vld3_lane = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> zeroinitializer, i32 7, i32 2)
store { <8 x i16>, <8 x i16>, <8 x i16> } %vld3_lane, { <8 x i16>, <8 x i16>, <8 x i16> }* undef
ret void
}
declare { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly