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Make sure aeskeygenassist uses an unsigned immediate field.
Fixes rdar://8017638 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104617 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -786,9 +786,9 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_aesni_aesdeclast : GCCBuiltin<"__builtin_ia32_aesdeclast128">,
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
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[IntrNoMem]>;
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def int_x86_aesni_aeskeygenassist :
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def int_x86_aesni_aeskeygenassist :
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GCCBuiltin<"__builtin_ia32_aeskeygenassist128">,
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty],
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i8_ty],
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[IntrNoMem]>;
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}
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@ -117,17 +117,17 @@ def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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return cast<LoadSDNode>(N)->getAlignment() >= 16;
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}]>;
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def alignedloadfsf32 : PatFrag<(ops node:$ptr),
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def alignedloadfsf32 : PatFrag<(ops node:$ptr),
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(f32 (alignedload node:$ptr))>;
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def alignedloadfsf64 : PatFrag<(ops node:$ptr),
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def alignedloadfsf64 : PatFrag<(ops node:$ptr),
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(f64 (alignedload node:$ptr))>;
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def alignedloadv4f32 : PatFrag<(ops node:$ptr),
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def alignedloadv4f32 : PatFrag<(ops node:$ptr),
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(v4f32 (alignedload node:$ptr))>;
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def alignedloadv2f64 : PatFrag<(ops node:$ptr),
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def alignedloadv2f64 : PatFrag<(ops node:$ptr),
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(v2f64 (alignedload node:$ptr))>;
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def alignedloadv4i32 : PatFrag<(ops node:$ptr),
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def alignedloadv4i32 : PatFrag<(ops node:$ptr),
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(v4i32 (alignedload node:$ptr))>;
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def alignedloadv2i64 : PatFrag<(ops node:$ptr),
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def alignedloadv2i64 : PatFrag<(ops node:$ptr),
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(v2i64 (alignedload node:$ptr))>;
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// Like 'load', but uses special alignment checks suitable for use in
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@ -518,25 +518,25 @@ def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
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def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
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"ucomiss\t{$src2, $src1|$src1, $src2}",
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[(set EFLAGS, (X86cmp FR32:$src1, (loadf32 addr:$src2)))]>;
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def COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
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"comiss\t{$src2, $src1|$src1, $src2}", []>;
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def COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
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"comiss\t{$src2, $src1|$src1, $src2}", []>;
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} // Defs = [EFLAGS]
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// Aliases to match intrinsics which expect XMM operand(s).
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let Constraints = "$src1 = $dst" in {
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def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
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(outs VR128:$dst),
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(outs VR128:$dst),
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(ins VR128:$src1, VR128:$src, SSECC:$cc),
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"cmp${cc}ss\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse_cmp_ss
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[(set VR128:$dst, (int_x86_sse_cmp_ss
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VR128:$src1,
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VR128:$src, imm:$cc))]>;
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def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
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(outs VR128:$dst),
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(outs VR128:$dst),
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(ins VR128:$src1, f32mem:$src, SSECC:$cc),
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"cmp${cc}ss\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
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@ -1312,13 +1312,13 @@ def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
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// Aliases to match intrinsics which expect XMM operand(s).
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let Constraints = "$src1 = $dst" in {
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def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
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(outs VR128:$dst),
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(outs VR128:$dst),
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(ins VR128:$src1, VR128:$src, SSECC:$cc),
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"cmp${cc}sd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
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VR128:$src, imm:$cc))]>;
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def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
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(outs VR128:$dst),
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(outs VR128:$dst),
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(ins VR128:$src1, f64mem:$src, SSECC:$cc),
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"cmp${cc}sd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
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@ -1656,7 +1656,7 @@ def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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[(set VR128:$dst,
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(int_x86_sse2_cvttps2dq VR128:$src))]>,
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XS, Requires<[HasSSE2]>;
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def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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@ -1981,24 +1981,24 @@ let Constraints = "$src1 = $dst" in {
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multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
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bit Commutable = 0> {
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def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
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def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
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let isCommutable = Commutable;
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}
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def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
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def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (IntId VR128:$src1,
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(bitconvert (memopv2i64
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(bitconvert (memopv2i64
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addr:$src2))))]>;
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}
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multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
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string OpcodeStr,
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Intrinsic IntId, Intrinsic IntId2> {
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def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
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def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
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@ -2007,7 +2007,7 @@ multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (IntId VR128:$src1,
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(bitconvert (memopv2i64 addr:$src2))))]>;
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def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
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def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
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(ins VR128:$src1, i32i8imm:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
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@ -2016,13 +2016,13 @@ multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
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/// PDI_binop_rm - Simple SSE2 binary operator.
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multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType OpVT, bit Commutable = 0> {
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def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
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def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
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let isCommutable = Commutable;
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}
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def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
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def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (OpVT (OpNode VR128:$src1,
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@ -2908,7 +2908,7 @@ defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
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defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
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int_x86_ssse3_pmul_hr_sw,
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int_x86_ssse3_pmul_hr_sw_128, 1>;
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defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
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int_x86_ssse3_pshuf_b,
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int_x86_ssse3_pshuf_b_128>;
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@ -3469,14 +3469,14 @@ let Constraints = "$src1 = $dst" in {
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let Constraints = "$src1 = $dst" in {
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multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType OpVT, bit Commutable = 0> {
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def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
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def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
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OpSize {
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let isCommutable = Commutable;
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}
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def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
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def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (OpNode VR128:$src1,
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@ -3954,15 +3954,15 @@ let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
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def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src3, i8imm:$src5),
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"#PCMPESTRM128rr PSEUDO!",
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[(set VR128:$dst,
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(int_x86_sse42_pcmpestrm128
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[(set VR128:$dst,
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(int_x86_sse42_pcmpestrm128
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VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
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def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src3, i8imm:$src5),
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"#PCMPESTRM128rm PSEUDO!",
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[(set VR128:$dst, (int_x86_sse42_pcmpestrm128
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VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
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[(set VR128:$dst, (int_x86_sse42_pcmpestrm128
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VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
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OpSize;
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}
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@ -3977,7 +3977,7 @@ def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
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let Defs = [ECX, EFLAGS] in {
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multiclass SS42AI_pcmpistri<Intrinsic IntId128> {
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def rr : SS42AI<0x63, MRMSrcReg, (outs),
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def rr : SS42AI<0x63, MRMSrcReg, (outs),
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(ins VR128:$src1, VR128:$src2, i8imm:$src3),
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"pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
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[(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
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@ -4008,7 +4008,7 @@ let Uses = [EAX, EDX] in {
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def rm : SS42AI<0x61, MRMSrcMem, (outs),
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(ins VR128:$src1, i128mem:$src3, i8imm:$src5),
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"pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
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[(set ECX,
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[(set ECX,
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(IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
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(implicit EFLAGS)]>, OpSize;
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}
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@ -4086,16 +4086,15 @@ def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
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OpSize;
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def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, i32i8imm:$src2),
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(ins VR128:$src1, i8imm:$src2),
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"aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst,
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(int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
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OpSize;
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def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
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(ins i128mem:$src1, i32i8imm:$src2),
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(ins i128mem:$src1, i8imm:$src2),
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"aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst,
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(int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
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imm:$src2))]>,
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OpSize;
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@ -9962,11 +9962,16 @@
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// CHECK: encoding: [0x66,0x0f,0x3a,0xdf,0x14,0x82,0x7d]
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aeskeygenassist $125, (%edx,%eax,4), %xmm2
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// rdar://8017638
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// CHECK: aeskeygenassist $128, %xmm1, %xmm2
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// CHECK: encoding: [0x66,0x0f,0x3a,0xdf,0x14,0x82,0x80]
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aeskeygenassist $128, %xmm1, %xmm2
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// rdar://7840289
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// CHECK: pshufb CPI1_0(%rip), %xmm1
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// CHECK: encoding: [0x66,0x0f,0x38,0x00,0x0d,A,A,A,A]
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// CHECK: fixup A - offset: 5, value: CPI1_0-4
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pshufb CPI1_0(%rip), %xmm1
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pshufb CPI1_0(%rip), %xmm1
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// rdar://7910087
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// CHECK: bsfw %bx, %bx
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@ -10018,7 +10023,7 @@ pshufb CPI1_0(%rip), %xmm1
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// radr://7914715
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// CHECK: fcoml 3735928559(%ebx,%ecx,8)
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// CHECK: encoding: [0xdc,0x94,0xcb,0xef,0xbe,0xad,0xde]
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fcoml 3735928559(%ebx,%ecx,8)
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fcoml 3735928559(%ebx,%ecx,8)
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// CHECK: fcoms 32493
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// CHECK: encoding: [0xd8,0x15,0xed,0x7e,0x00,0x00]
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