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Change fp to sint legalization on x86-32 to do 2 x i32

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loads instead of 1 x i64 loads.  This doesn't change any functionality yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43068 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2007-10-17 06:17:29 +00:00
parent 2ff75ee9ab
commit 7ef1a4bf04
1 changed files with 12 additions and 2 deletions
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14
lib/Target/X86/X86ISelLowering.cpp
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@ -3952,8 +3952,18 @@ SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
SDOperand Ops[] = { Chain, Value, StackSlot };
SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
// Load the result.
return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
// Load the result. If this is an i64 load on an x86-32 host, expand the
// load.
if (Op.getValueType() != MVT::i64 || Subtarget->is64Bit())
return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
SDOperand Lo = DAG.getLoad(MVT::i32, FIST, StackSlot, NULL, 0);
StackSlot = DAG.getNode(ISD::ADD, StackSlot.getValueType(), StackSlot,
DAG.getConstant(StackSlot.getValueType(), 4));
SDOperand Hi = DAG.getLoad(MVT::i32, FIST, StackSlot, NULL, 0);
return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
}
SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {