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fp to int and back conversion sequences
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19944 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -412,6 +412,7 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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{
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assert (N.getOperand(0).getValueType() == MVT::i64 && "only quads can be loaded from");
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Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
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Tmp2 = MakeReg(MVT::f64);
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//The hard way:
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// Spill the integer to memory and reload it from there.
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@ -419,12 +420,10 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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MachineFunction *F = BB->getParent();
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int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, Size);
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//STL LDS
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//STQ LDT
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Opc = DestType == MVT::f64 ? Alpha::STQ : Alpha::STL;
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BuildMI(BB, Opc, 2).addReg(Tmp1).addFrameIndex(FrameIdx).addReg(Alpha::F31);
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Opc = DestType == MVT::f64 ? Alpha::LDT : Alpha::LDS;
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BuildMI(BB, Opc, 1, Result).addFrameIndex(FrameIdx).addReg(Alpha::F31);
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BuildMI(BB, Alpha::STQ, 3).addReg(Tmp1).addFrameIndex(FrameIdx).addReg(Alpha::F31);
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BuildMI(BB, Alpha::LDT, 2, Tmp2).addFrameIndex(FrameIdx).addReg(Alpha::F31);
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Opc = DestType == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS;
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BuildMI(BB, Opc, 1, Result).addReg(Tmp2);
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//The easy way: doesn't work
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// //so these instructions are not supported on ev56
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@ -965,13 +964,34 @@ unsigned ISel::SelectExpr(SDOperand N) {
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return Result;
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// // case ISD::UINT_TO_FP:
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// case ISD::FP_TO_SINT:
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// assert (N.getValueType() == MVT::f64 && "Only can convert for doubles");
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// Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
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// Tmp2 = MakeReg(SrcTy);
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// BuildMI(BB, CVTTQ, 1, Tmp2).addReg(Tmp1);
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// BuildMI(BB, FTOIT, 1, Result).addReg(Tmp2);
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// return result;
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case ISD::FP_TO_SINT:
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{
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assert (DestType == MVT::i64 && "only quads can be loaded to");
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MVT::ValueType SrcType = N.getOperand(0).getValueType();
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Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
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//The hard way:
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// Spill the integer to memory and reload it from there.
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unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
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MachineFunction *F = BB->getParent();
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int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, 8);
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//CVTTQ STT LDQ
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//CVTST CVTTQ STT LDQ
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if (SrcType == MVT::f32)
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{
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Tmp2 = MakeReg(MVT::f64);
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BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Tmp1);
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Tmp1 = Tmp2;
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}
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Tmp2 = MakeReg(MVT::f64);
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BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Tmp1);
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BuildMI(BB, Alpha::STT, 3).addReg(Tmp2).addFrameIndex(FrameIdx).addReg(Alpha::F31);
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BuildMI(BB, Alpha::LDQ, 2, Result).addFrameIndex(FrameIdx).addReg(Alpha::F31);
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return Result;
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}
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// // case ISD::FP_TO_UINT:
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@ -331,7 +331,7 @@ def ITOFT : FPForm<0x14, 0x024, (ops FPRC:$RC, GPRC:$RA), "itoft $RA,$RC">; //In
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def CVTQS : FPForm<0x16, 0x0BC, (ops FPRC:$RC, FPRC:$RA), "cvtqs $RA,$RC">; //Convert quadword to S_floating
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def CVTQT : FPForm<0x16, 0x0BE, (ops FPRC:$RC, FPRC:$RA), "cvtqt $RA,$RC">; //Convert quadword to T_floating
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def CVTST : FPForm<0x16, 0x2AC, (ops FPRC:$RC, FPRC:$RA), "cvtst $RA,$RC">; //Convert S_floating to T_floating
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//CVTTQ F-P 16.0AF Convert T_floating to quadword
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def CVTTQ : FPForm<0x16, 0x0AF, (ops FPRC:$RC, FPRC:$RA), "cvttq $RA,$RC">; //Convert T_floating to quadword
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def CVTTS : FPForm<0x16, 0x2AC, (ops FPRC:$RC, FPRC:$RA), "cvtts $RA,$RC">; //Convert T_floating to S_floating
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//S_floating : IEEE Single
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