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* Lowercase the register names

Browse Source 
* Parenthesize assert() expressions correctly
* Fix spacing around for() and if() statements


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14384 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman
2004-06-24 23:51:00 +00:00
parent 64aed54684
commit 7f484a5fff
3 changed files with 33 additions and 33 deletions
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22
lib/Target/PowerPC/PPC32AsmPrinter.cpp
View File

@@ -426,8 +426,8 @@ void Printer::printOp(const MachineOperand &MO,
} }
// FALLTHROUGH // FALLTHROUGH
case MachineOperand::MO_MachineRegister: case MachineOperand::MO_MachineRegister:
O << RI.get(MO.getReg()).Name; O << LowercaseString(RI.get(MO.getReg()).Name);
return; return;
case MachineOperand::MO_SignExtendedImmed: case MachineOperand::MO_SignExtendedImmed:
case MachineOperand::MO_UnextendedImmed: case MachineOperand::MO_UnextendedImmed:
@@ -511,15 +511,15 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
unsigned int ArgCount = Desc.TSFlags & PPC32II::ArgCountMask; unsigned int ArgCount = Desc.TSFlags & PPC32II::ArgCountMask;
unsigned int ArgType[5]; unsigned int ArgType[5];
ArgType[0] = (Desc.TSFlags>>PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask; ArgType[0] = (Desc.TSFlags >> PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask;
ArgType[1] = (Desc.TSFlags>>PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask; ArgType[1] = (Desc.TSFlags >> PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask;
ArgType[2] = (Desc.TSFlags>>PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask; ArgType[2] = (Desc.TSFlags >> PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask;
ArgType[3] = (Desc.TSFlags>>PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask; ArgType[3] = (Desc.TSFlags >> PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask;
ArgType[4] = (Desc.TSFlags>>PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask; ArgType[4] = (Desc.TSFlags >> PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask;
assert((Desc.TSFlags & PPC32II::VMX == 0) && assert(((Desc.TSFlags & PPC32II::VMX) == 0) &&
"Instruction requires VMX support"); "Instruction requires VMX support");
assert((Desc.TSFlags & PPC32II::PPC64 == 0) && assert(((Desc.TSFlags & PPC32II::PPC64) == 0) &&
"Instruction requires 64 bit support"); "Instruction requires 64 bit support");
//assert ( ValidOpcodes(MI, ArgType) && "Instruction has invalid inputs"); //assert ( ValidOpcodes(MI, ArgType) && "Instruction has invalid inputs");
++EmittedInsts; ++EmittedInsts;
@@ -566,7 +566,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
printOp(MI->getOperand(2)); printOp(MI->getOperand(2));
O << ")\n"; O << ")\n";
} else { } else {
for(i = 0; i< ArgCount; i++) { for (i = 0; i < ArgCount; ++i) {
if (ArgType[i] == PPC32II::Gpr0 && if (ArgType[i] == PPC32II::Gpr0 &&
MI->getOperand(i).getReg() == PPC32::R0) MI->getOperand(i).getReg() == PPC32::R0)
O << "0"; O << "0";
@@ -574,7 +574,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
//std::cout << "DEBUG " << (*(TM.getRegisterInfo())).get(MI->getOperand(i).getReg()).Name << "\n"; //std::cout << "DEBUG " << (*(TM.getRegisterInfo())).get(MI->getOperand(i).getReg()).Name << "\n";
printOp(MI->getOperand(i)); printOp(MI->getOperand(i));
} }
if( ArgCount - 1 == i) if (ArgCount - 1 == i)
O << "\n"; O << "\n";
else else
O << ", "; O << ", ";

22
lib/Target/PowerPC/PPCAsmPrinter.cpp
View File

@@ -426,8 +426,8 @@ void Printer::printOp(const MachineOperand &MO,
} }
// FALLTHROUGH // FALLTHROUGH
case MachineOperand::MO_MachineRegister: case MachineOperand::MO_MachineRegister:
O << RI.get(MO.getReg()).Name; O << LowercaseString(RI.get(MO.getReg()).Name);
return; return;
case MachineOperand::MO_SignExtendedImmed: case MachineOperand::MO_SignExtendedImmed:
case MachineOperand::MO_UnextendedImmed: case MachineOperand::MO_UnextendedImmed:
@@ -511,15 +511,15 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
unsigned int ArgCount = Desc.TSFlags & PPC32II::ArgCountMask; unsigned int ArgCount = Desc.TSFlags & PPC32II::ArgCountMask;
unsigned int ArgType[5]; unsigned int ArgType[5];
ArgType[0] = (Desc.TSFlags>>PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask; ArgType[0] = (Desc.TSFlags >> PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask;
ArgType[1] = (Desc.TSFlags>>PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask; ArgType[1] = (Desc.TSFlags >> PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask;
ArgType[2] = (Desc.TSFlags>>PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask; ArgType[2] = (Desc.TSFlags >> PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask;
ArgType[3] = (Desc.TSFlags>>PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask; ArgType[3] = (Desc.TSFlags >> PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask;
ArgType[4] = (Desc.TSFlags>>PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask; ArgType[4] = (Desc.TSFlags >> PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask;
assert((Desc.TSFlags & PPC32II::VMX == 0) && assert(((Desc.TSFlags & PPC32II::VMX) == 0) &&
"Instruction requires VMX support"); "Instruction requires VMX support");
assert((Desc.TSFlags & PPC32II::PPC64 == 0) && assert(((Desc.TSFlags & PPC32II::PPC64) == 0) &&
"Instruction requires 64 bit support"); "Instruction requires 64 bit support");
//assert ( ValidOpcodes(MI, ArgType) && "Instruction has invalid inputs"); //assert ( ValidOpcodes(MI, ArgType) && "Instruction has invalid inputs");
++EmittedInsts; ++EmittedInsts;
@@ -566,7 +566,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
printOp(MI->getOperand(2)); printOp(MI->getOperand(2));
O << ")\n"; O << ")\n";
} else { } else {
for(i = 0; i< ArgCount; i++) { for (i = 0; i < ArgCount; ++i) {
if (ArgType[i] == PPC32II::Gpr0 && if (ArgType[i] == PPC32II::Gpr0 &&
MI->getOperand(i).getReg() == PPC32::R0) MI->getOperand(i).getReg() == PPC32::R0)
O << "0"; O << "0";
@@ -574,7 +574,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
//std::cout << "DEBUG " << (*(TM.getRegisterInfo())).get(MI->getOperand(i).getReg()).Name << "\n"; //std::cout << "DEBUG " << (*(TM.getRegisterInfo())).get(MI->getOperand(i).getReg()).Name << "\n";
printOp(MI->getOperand(i)); printOp(MI->getOperand(i));
} }
if( ArgCount - 1 == i) if (ArgCount - 1 == i)
O << "\n"; O << "\n";
else else
O << ", "; O << ", ";

22
lib/Target/PowerPC/PowerPCAsmPrinter.cpp
View File

@@ -426,8 +426,8 @@ void Printer::printOp(const MachineOperand &MO,
} }
// FALLTHROUGH // FALLTHROUGH
case MachineOperand::MO_MachineRegister: case MachineOperand::MO_MachineRegister:
O << RI.get(MO.getReg()).Name; O << LowercaseString(RI.get(MO.getReg()).Name);
return; return;
case MachineOperand::MO_SignExtendedImmed: case MachineOperand::MO_SignExtendedImmed:
case MachineOperand::MO_UnextendedImmed: case MachineOperand::MO_UnextendedImmed:
@@ -511,15 +511,15 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
unsigned int ArgCount = Desc.TSFlags & PPC32II::ArgCountMask; unsigned int ArgCount = Desc.TSFlags & PPC32II::ArgCountMask;
unsigned int ArgType[5]; unsigned int ArgType[5];
ArgType[0] = (Desc.TSFlags>>PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask; ArgType[0] = (Desc.TSFlags >> PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask;
ArgType[1] = (Desc.TSFlags>>PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask; ArgType[1] = (Desc.TSFlags >> PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask;
ArgType[2] = (Desc.TSFlags>>PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask; ArgType[2] = (Desc.TSFlags >> PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask;
ArgType[3] = (Desc.TSFlags>>PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask; ArgType[3] = (Desc.TSFlags >> PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask;
ArgType[4] = (Desc.TSFlags>>PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask; ArgType[4] = (Desc.TSFlags >> PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask;
assert((Desc.TSFlags & PPC32II::VMX == 0) && assert(((Desc.TSFlags & PPC32II::VMX) == 0) &&
"Instruction requires VMX support"); "Instruction requires VMX support");
assert((Desc.TSFlags & PPC32II::PPC64 == 0) && assert(((Desc.TSFlags & PPC32II::PPC64) == 0) &&
"Instruction requires 64 bit support"); "Instruction requires 64 bit support");
//assert ( ValidOpcodes(MI, ArgType) && "Instruction has invalid inputs"); //assert ( ValidOpcodes(MI, ArgType) && "Instruction has invalid inputs");
++EmittedInsts; ++EmittedInsts;
@@ -566,7 +566,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
printOp(MI->getOperand(2)); printOp(MI->getOperand(2));
O << ")\n"; O << ")\n";
} else { } else {
for(i = 0; i< ArgCount; i++) { for (i = 0; i < ArgCount; ++i) {
if (ArgType[i] == PPC32II::Gpr0 && if (ArgType[i] == PPC32II::Gpr0 &&
MI->getOperand(i).getReg() == PPC32::R0) MI->getOperand(i).getReg() == PPC32::R0)
O << "0"; O << "0";
@@ -574,7 +574,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
//std::cout << "DEBUG " << (*(TM.getRegisterInfo())).get(MI->getOperand(i).getReg()).Name << "\n"; //std::cout << "DEBUG " << (*(TM.getRegisterInfo())).get(MI->getOperand(i).getReg()).Name << "\n";
printOp(MI->getOperand(i)); printOp(MI->getOperand(i));
} }
if( ArgCount - 1 == i) if (ArgCount - 1 == i)
O << "\n"; O << "\n";
else else
O << ", "; O << ", ";