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Make the verifier a little quieter on instructions that it's probably
(and likely) wrong about anyhow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119320 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -558,7 +558,9 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
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else if (MO->isImplicit())
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report("Explicit definition marked as implicit", MO, MONum);
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} else if (MONum < TI.getNumOperands()) {
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if (MO->isReg()) {
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// Don't check if it's a variadic instruction. See, e.g., LDM_RET in the arm
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// back end.
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if (MO->isReg() && MONum != TI.getNumOperands()-1) {
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if (MO->isDef())
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report("Explicit operand marked as def", MO, MONum);
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if (MO->isImplicit())
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