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ARM64: add extra scalar neg pattern & tests.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205208 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
2014-03-31 15:46:42 +00:00
parent b35ffdff16
commit 812a174ba4
2 changed files with 73 additions and 1 deletions
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3
lib/Target/ARM64/ARM64InstrInfo.td
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@@ -2563,7 +2563,8 @@ defm FCVTZU : SIMDTwoScalarSD< 1, 1, 0b11011, "fcvtzu">;
defm FRECPE : SIMDTwoScalarSD< 0, 1, 0b11101, "frecpe">; defm FRECPE : SIMDTwoScalarSD< 0, 1, 0b11101, "frecpe">;
defm FRECPX : SIMDTwoScalarSD< 0, 1, 0b11111, "frecpx">; defm FRECPX : SIMDTwoScalarSD< 0, 1, 0b11111, "frecpx">;
defm FRSQRTE : SIMDTwoScalarSD< 1, 1, 0b11101, "frsqrte">; defm FRSQRTE : SIMDTwoScalarSD< 1, 1, 0b11101, "frsqrte">;
defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg">; defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", ARM64sitof>; defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", ARM64sitof>;
defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_arm64_neon_sqabs>; defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_arm64_neon_sqabs>;
defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_arm64_neon_sqneg>; defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_arm64_neon_sqneg>;

71
test/CodeGen/ARM64/neg.ll Normal file
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@@ -0,0 +1,71 @@
; RUN: llc -mtriple=arm64-linux-gnu -o - %s | FileCheck %s
define i32 @test_neg_i32(i32 %in) {
; CHECK-LABEL: test_neg_i32:
; CHECK: neg w0, w0
%res = sub i32 0, %in
ret i32 %res
}
define i64 @test_neg_i64(i64 %in) {
; CHECK-LABEL: test_neg_i64:
; CHECK: neg x0, x0
%res = sub i64 0, %in
ret i64 %res
}
define <8 x i8> @test_neg_v8i8(<8 x i8> %in) {
; CHECK-LABEL: test_neg_v8i8:
; CHECK: neg v0.8b, v0.8b
%res = sub <8 x i8> zeroinitializer, %in
ret <8 x i8> %res
}
define <4 x i16> @test_neg_v4i16(<4 x i16> %in) {
; CHECK-LABEL: test_neg_v4i16:
; CHECK: neg v0.4h, v0.4h
%res = sub <4 x i16> zeroinitializer, %in
ret <4 x i16> %res
}
define <2 x i32> @test_neg_v2i32(<2 x i32> %in) {
; CHECK-LABEL: test_neg_v2i32:
; CHECK: neg v0.2s, v0.2s
%res = sub <2 x i32> zeroinitializer, %in
ret <2 x i32> %res
}
define <16 x i8> @test_neg_v16i8(<16 x i8> %in) {
; CHECK-LABEL: test_neg_v16i8:
; CHECK: neg v0.16b, v0.16b
%res = sub <16 x i8> zeroinitializer, %in
ret <16 x i8> %res
}
define <8 x i16> @test_neg_v8i16(<8 x i16> %in) {
; CHECK-LABEL: test_neg_v8i16:
; CHECK: neg v0.8h, v0.8h
%res = sub <8 x i16> zeroinitializer, %in
ret <8 x i16> %res
}
define <4 x i32> @test_neg_v4i32(<4 x i32> %in) {
; CHECK-LABEL: test_neg_v4i32:
; CHECK: neg v0.4s, v0.4s
%res = sub <4 x i32> zeroinitializer, %in
ret <4 x i32> %res
}
define <2 x i64> @test_neg_v2i64(<2 x i64> %in) {
; CHECK-LABEL: test_neg_v2i64:
; CHECK: neg v0.2d, v0.2d
%res = sub <2 x i64> zeroinitializer, %in
ret <2 x i64> %res
}
define <1 x i64> @test_neg_v1i64(<1 x i64> %in) {
; CHECK-LABEL: test_neg_v1i64:
; CHECK: neg d0, d0
%res = sub <1 x i64> zeroinitializer, %in
ret <1 x i64> %res
}