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Track IR ordering of SelectionDAG nodes 4/4.

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Unit test cases for -pre-RA-sched=source.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182706 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2013-05-25 03:26:51 +00:00
parent dd0fb018a7
commit 81349a7435
3 changed files with 49 additions and 0 deletions
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21
test/CodeGen/ARM/crash-greedy-v6.ll
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@ -1,4 +1,5 @@
; RUN: llc -disable-fp-elim -relocation-model=pic < %s
; RUN: llc -disable-fp-elim -relocation-model=pic -pre-RA-sched=source < %s | FileCheck %s --check-prefix=SOURCE-SCHED
target triple = "armv6-apple-ios"
; Reduced from 177.mesa. This test causes a live range split before an LDR_POST instruction.
@ -11,6 +12,26 @@ for.body.lr.ph: ; preds = %entry
br label %for.body
for.body: ; preds = %for.body, %for.body.lr.ph
; SOURCE-SCHED: str
; SOURCE-SCHED: add
; SOURCE-SCHED: sub
; SOURCE-SCHED: ldr
; SOURCE-SCHED: ldr
; SOURCE-SCHED: str
; SOURCE-SCHED: str
; SOURCE-SCHED: str
; SOURCE-SCHED: str
; SOURCE-SCHED: add
; SOURCE-SCHED: add
; SOURCE-SCHED: add
; SOURCE-SCHED: add
; SOURCE-SCHED: str
; SOURCE-SCHED: mov
; SOURCE-SCHED: bl
; SOURCE-SCHED: ldr
; SOURCE-SCHED: ldr
; SOURCE-SCHED: cmp
; SOURCE-SCHED: bne
%i.031 = phi i32 [ 0, %for.body.lr.ph ], [ %0, %for.body ]
%arrayidx11 = getelementptr float* %t, i32 %i.031
%arrayidx15 = getelementptr float* %u, i32 %i.031

16
test/CodeGen/Mips/selectcc.ll
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@ -1,4 +1,5 @@
; RUN: llc -march=mipsel < %s
; RUN: llc -march=mipsel -pre-RA-sched=source < %s | FileCheck %s --check-prefix=SOURCE-SCHED
@gf0 = external global float
@gf1 = external global float
@ -7,6 +8,21 @@
define float @select_cc_f32(float %a, float %b) nounwind {
entry:
; SOURCE-SCHED: lui
; SOURCE-SCHED: addiu
; SOURCE-SCHED: addu
; SOURCE-SCHED: lw
; SOURCE-SCHED: sw
; SOURCE-SCHED: lw
; SOURCE-SCHED: lui
; SOURCE-SCHED: sw
; SOURCE-SCHED: addiu
; SOURCE-SCHED: addiu
; SOURCE-SCHED: c.olt.s
; SOURCE-SCHED: movt
; SOURCE-SCHED: mtc1
; SOURCE-SCHED: jr
store float 0.000000e+00, float* @gf0, align 4
store float 1.000000e+00, float* @gf1, align 4
%cmp = fcmp olt float %a, %b

12
test/CodeGen/X86/2008-09-11-CoalescerBug2.ll
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@ -1,4 +1,5 @@
; RUN: llc < %s -march=x86
; RUN: llc -pre-RA-sched=source < %s -march=x86 | FileCheck %s --check-prefix=SOURCE-SCHED
; PR2748
@g_73 = external global i32 ; <i32*> [#uses=1]
@ -6,6 +7,17 @@
define i32 @func_44(i16 signext %p_46) nounwind {
entry:
; SOURCE-SCHED: subl
; SOURCE-SCHED: movl
; SOURCE-SCHED: sarl
; SOURCE-SCHED: cmpl
; SOURCE-SCHED: setg
; SOURCE-SCHED: movzbl
; SOURCE-SCHED: movb
; SOURCE-SCHED: xorl
; SOURCE-SCHED: subl
; SOURCE-SCHED: testb
; SOURCE-SCHED: jne
%0 = load i32* @g_5, align 4 ; <i32> [#uses=1]
%1 = ashr i32 %0, 1 ; <i32> [#uses=1]
%2 = icmp sgt i32 %1, 1 ; <i1> [#uses=1]