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Remove BRTWOWAY*
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch selector smarter about the code it generates, fixing a case in the readme. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26814 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
parent
e261c474ca
commit
81e8097377
@ -302,25 +302,12 @@ namespace ISD {
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// to if the condition is true.
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BRCOND,
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// BRCONDTWOWAY - Two-way conditional branch. The first operand is the
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// chain, the second is the condition, the third is the block to branch to
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// if true, and the forth is the block to branch to if false. Targets
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// usually do not implement this, preferring to have legalize demote the
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// operation to BRCOND/BR pairs when necessary.
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BRCONDTWOWAY,
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// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in
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// that the condition is represented as condition code, and two nodes to
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// compare, rather than as a combined SetCC node. The operands in order are
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// chain, cc, lhs, rhs, block to branch to if condition is true.
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BR_CC,
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// BRTWOWAY_CC - Two-way conditional branch. The operands in order are
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// chain, cc, lhs, rhs, block to branch to if condition is true, block to
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// branch to if condition is false. Targets usually do not implement this,
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// preferring to have legalize demote the operation to BRCOND/BR pairs.
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BRTWOWAY_CC,
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// RET - Return from function. The first operand is the chain,
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// and any subsequent operands are the return values for the
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// function. This operation can have variable number of operands.
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@ -206,9 +206,7 @@ namespace {
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SDOperand visitFNEG(SDNode *N);
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SDOperand visitFABS(SDNode *N);
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SDOperand visitBRCOND(SDNode *N);
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SDOperand visitBRCONDTWOWAY(SDNode *N);
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SDOperand visitBR_CC(SDNode *N);
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SDOperand visitBRTWOWAY_CC(SDNode *N);
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SDOperand visitLOAD(SDNode *N);
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SDOperand visitSTORE(SDNode *N);
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@ -639,9 +637,7 @@ SDOperand DAGCombiner::visit(SDNode *N) {
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case ISD::FNEG: return visitFNEG(N);
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case ISD::FABS: return visitFABS(N);
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case ISD::BRCOND: return visitBRCOND(N);
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case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N);
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case ISD::BR_CC: return visitBR_CC(N);
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case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N);
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case ISD::LOAD: return visitLOAD(N);
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case ISD::STORE: return visitSTORE(N);
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}
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@ -2219,35 +2215,6 @@ SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
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return SDOperand();
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}
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SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) {
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SDOperand Chain = N->getOperand(0);
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SDOperand N1 = N->getOperand(1);
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SDOperand N2 = N->getOperand(2);
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SDOperand N3 = N->getOperand(3);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
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// unconditional branch to true mbb
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if (N1C && N1C->getValue() == 1)
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return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
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// unconditional branch to false mbb
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if (N1C && N1C->isNullValue())
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return DAG.getNode(ISD::BR, MVT::Other, Chain, N3);
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// fold a brcondtwoway with a setcc condition into a BRTWOWAY_CC node if
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// BRTWOWAY_CC is legal on the target.
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if (N1.getOpcode() == ISD::SETCC &&
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TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) {
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std::vector<SDOperand> Ops;
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Ops.push_back(Chain);
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Ops.push_back(N1.getOperand(2));
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Ops.push_back(N1.getOperand(0));
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Ops.push_back(N1.getOperand(1));
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Ops.push_back(N2);
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Ops.push_back(N3);
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return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops);
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}
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return SDOperand();
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}
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// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
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//
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SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
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@ -2273,41 +2240,6 @@ SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
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return SDOperand();
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}
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SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) {
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SDOperand Chain = N->getOperand(0);
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SDOperand CCN = N->getOperand(1);
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SDOperand LHS = N->getOperand(2);
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SDOperand RHS = N->getOperand(3);
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SDOperand N4 = N->getOperand(4);
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SDOperand N5 = N->getOperand(5);
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SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS,
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cast<CondCodeSDNode>(CCN)->get(), false);
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ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
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// fold select_cc lhs, rhs, x, x, cc -> x
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if (N4 == N5)
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return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
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// fold select_cc true, x, y -> x
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if (SCCC && SCCC->getValue())
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return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
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// fold select_cc false, x, y -> y
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if (SCCC && SCCC->isNullValue())
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return DAG.getNode(ISD::BR, MVT::Other, Chain, N5);
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// fold to a simpler setcc
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if (SCC.Val && SCC.getOpcode() == ISD::SETCC) {
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std::vector<SDOperand> Ops;
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Ops.push_back(Chain);
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Ops.push_back(SCC.getOperand(2));
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Ops.push_back(SCC.getOperand(0));
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Ops.push_back(SCC.getOperand(1));
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Ops.push_back(N4);
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Ops.push_back(N5);
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return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops);
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}
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return SDOperand();
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}
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SDOperand DAGCombiner::visitLOAD(SDNode *N) {
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SDOperand Chain = N->getOperand(0);
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SDOperand Ptr = N->getOperand(1);
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@ -945,100 +945,6 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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break;
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}
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break;
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case ISD::BRCONDTWOWAY:
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Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
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switch (getTypeAction(Node->getOperand(1).getValueType())) {
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case Expand: assert(0 && "It's impossible to expand bools");
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case Legal:
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Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
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break;
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case Promote:
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Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
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break;
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}
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// If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR
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// pair.
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switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) {
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case TargetLowering::Promote:
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Legal:
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Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
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Node->getOperand(3));
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break;
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case TargetLowering::Expand:
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// If BRTWOWAY_CC is legal for this target, then simply expand this node
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// to that. Otherwise, skip BRTWOWAY_CC and expand directly to a
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// BRCOND/BR pair.
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if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) {
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if (Tmp2.getOpcode() == ISD::SETCC) {
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Tmp3 = Tmp2.getOperand(0);
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Tmp4 = Tmp2.getOperand(1);
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Tmp2 = Tmp2.getOperand(2);
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} else {
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Tmp3 = Tmp2;
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Tmp4 = DAG.getConstant(0, Tmp2.getValueType());
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Tmp2 = DAG.getCondCode(ISD::SETNE);
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}
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std::vector<SDOperand> Ops;
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Ops.push_back(Tmp1);
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Ops.push_back(Tmp2);
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Ops.push_back(Tmp3);
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Ops.push_back(Tmp4);
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Ops.push_back(Node->getOperand(2));
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Ops.push_back(Node->getOperand(3));
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Result = DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops);
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} else {
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Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
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Node->getOperand(2));
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Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3));
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}
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break;
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}
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break;
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case ISD::BRTWOWAY_CC: {
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Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
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// Ensure that libcalls are emitted before a branch.
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Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
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Tmp1 = LegalizeOp(Tmp1);
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LastCALLSEQ_END = DAG.getEntryNode();
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Tmp2 = Node->getOperand(2); // LHS
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Tmp3 = Node->getOperand(3); // RHS
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Tmp4 = Node->getOperand(1); // CC
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LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
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// If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
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// the LHS is a legal SETCC itself. In this case, we need to compare
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// the result against zero to select between true and false values.
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if (Tmp3.Val == 0) {
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Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
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Tmp4 = DAG.getCondCode(ISD::SETNE);
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}
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std::vector<SDOperand> Ops;
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Ops.push_back(Tmp1);
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Ops.push_back(Tmp4);
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Ops.push_back(Tmp2);
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Ops.push_back(Tmp3);
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Ops.push_back(Node->getOperand(4));
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Ops.push_back(Node->getOperand(5));
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Result = DAG.UpdateNodeOperands(Result, Ops);
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// Everything is legal, see if we should expand this op or something.
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switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Legal: break;
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case TargetLowering::Expand:
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Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1,
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DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp2,
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Tmp3, Tmp4),
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Result.getOperand(4));
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Result = DAG.getNode(ISD::BR, MVT::Other, Result, Result.getOperand(5));
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break;
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}
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break;
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}
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case ISD::LOAD: {
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Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
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Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
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@ -1486,18 +1486,6 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Ops[1].Val);
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switch (Opcode) {
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default: break;
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case ISD::BRCONDTWOWAY:
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if (N1C)
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if (N1C->getValue()) // Unconditional branch to true dest.
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return getNode(ISD::BR, MVT::Other, Ops[0], Ops[2]);
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else // Unconditional branch to false dest.
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return getNode(ISD::BR, MVT::Other, Ops[0], Ops[3]);
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break;
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case ISD::BRTWOWAY_CC:
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assert(Ops.size() == 6 && "BRTWOWAY_CC takes 6 operands!");
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assert(Ops[2].getValueType() == Ops[3].getValueType() &&
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"LHS and RHS of comparison must have same type!");
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break;
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case ISD::TRUNCSTORE: {
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assert(Ops.size() == 5 && "TRUNCSTORE takes 5 operands!");
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MVT::ValueType EVT = cast<VTSDNode>(Ops[4])->getVT();
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@ -2692,9 +2680,7 @@ const char *SDNode::getOperationName(const SelectionDAG *G) const {
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// Control flow instructions
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case ISD::BR: return "br";
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case ISD::BRCOND: return "brcond";
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case ISD::BRCONDTWOWAY: return "brcondtwoway";
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case ISD::BR_CC: return "br_cc";
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case ISD::BRTWOWAY_CC: return "brtwoway_cc";
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case ISD::BR_CC: return "br_cc";
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case ISD::RET: return "ret";
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case ISD::CALLSEQ_START: return "callseq_start";
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case ISD::CALLSEQ_END: return "callseq_end";
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@ -691,10 +691,10 @@ void SelectionDAGLowering::visitBr(BranchInst &I) {
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SDOperand True = DAG.getConstant(1, Cond.getValueType());
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Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
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}
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Ops.push_back(Cond);
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Ops.push_back(DAG.getBasicBlock(Succ0MBB));
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Ops.push_back(DAG.getBasicBlock(Succ1MBB));
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DAG.setRoot(DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops));
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SDOperand True = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
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DAG.getBasicBlock(Succ0MBB));
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DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, True,
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DAG.getBasicBlock(Succ1MBB)));
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}
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}
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}
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@ -48,8 +48,6 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
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addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
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addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
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setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
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setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::Other, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
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@ -36,8 +36,6 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
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addRegisterClass(MVT::i1, IA64::PRRegisterClass);
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setOperationAction(ISD::BR_CC , MVT::Other, Expand);
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setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
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setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
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setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
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// ia64 uses SELECT not SELECT_CC
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@ -48,10 +48,10 @@ FunctionPass *llvm::createPPCBranchSelectionPass() {
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static unsigned getNumBytesForInstruction(MachineInstr *MI) {
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switch (MI->getOpcode()) {
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case PPC::COND_BRANCH:
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// while this will be 4 most of the time, if we emit 12 it is just a
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// while this will be 4 most of the time, if we emit 8 it is just a
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// minor pessimization that saves us from having to worry about
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// keeping the offsets up to date later when we emit long branch glue.
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return 12;
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return 8;
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case PPC::IMPLICIT_DEF_GPR: // no asm emitted
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case PPC::IMPLICIT_DEF_F4: // no asm emitted
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case PPC::IMPLICIT_DEF_F8: // no asm emitted
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@ -102,7 +102,6 @@ bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
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// long branch:
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// bInverseCC $PC+8
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// b .L_TARGET_MBB
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// b .L_FALLTHROUGH_MBB
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for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
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++MFI) {
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MachineBasicBlock *MBB = MFI;
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@ -123,8 +122,6 @@ bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
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// 3. fallthrough MBB
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MachineBasicBlock *trueMBB =
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MBBI->getOperand(2).getMachineBasicBlock();
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MachineBasicBlock *falseMBB =
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MBBI->getOperand(3).getMachineBasicBlock();
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int Displacement = OffsetMap[trueMBB] - ByteCount;
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unsigned Opcode = MBBI->getOperand(1).getImmedValue();
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@ -136,7 +133,6 @@ bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
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} else {
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BuildMI(*MBB, MBBJ, Inverted, 2).addReg(CRReg).addSImm(8);
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BuildMI(*MBB, MBBJ, PPC::B, 1).addMBB(trueMBB);
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BuildMI(*MBB, MBBJ, PPC::B, 1).addMBB(falseMBB);
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}
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// Erase the psuedo COND_BRANCH instruction, and then back up the
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@ -1105,44 +1105,14 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
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N2, N3, getI32Imm(BROpc));
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return;
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}
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case ISD::BR_CC:
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case ISD::BRTWOWAY_CC: {
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case ISD::BR_CC: {
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SDOperand Chain;
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Select(Chain, N->getOperand(0));
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MachineBasicBlock *Dest =
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cast<BasicBlockSDNode>(N->getOperand(4))->getBasicBlock();
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ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
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SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
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// If this is a two way branch, then grab the fallthrough basic block
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// argument and build a PowerPC branch pseudo-op, suitable for long branch
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// conversion if necessary by the branch selection pass. Otherwise, emit a
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// standard conditional branch.
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if (N->getOpcode() == ISD::BRTWOWAY_CC) {
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SDOperand CondTrueBlock = N->getOperand(4);
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SDOperand CondFalseBlock = N->getOperand(5);
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unsigned Opc = getBCCForSetCC(CC);
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SDOperand CB =
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SDOperand(CurDAG->getTargetNode(PPC::COND_BRANCH, MVT::Other,
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CondCode, getI32Imm(Opc),
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CondTrueBlock, CondFalseBlock,
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Chain), 0);
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Result = CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, CondFalseBlock, CB);
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} else {
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// Iterate to the next basic block
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ilist<MachineBasicBlock>::iterator It = BB;
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++It;
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// If the fallthrough path is off the end of the function, which would be
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// undefined behavior, set it to be the same as the current block because
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// we have nothing better to set it to, and leaving it alone will cause
|
||||
// the PowerPC Branch Selection pass to crash.
|
||||
if (It == BB->getParent()->end()) It = Dest;
|
||||
Result = CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, CondCode,
|
||||
getI32Imm(getBCCForSetCC(CC)),
|
||||
N->getOperand(4), CurDAG->getBasicBlock(It),
|
||||
Chain);
|
||||
}
|
||||
Result = CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other,
|
||||
CondCode, getI32Imm(getBCCForSetCC(CC)),
|
||||
N->getOperand(4), Chain);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
@ -94,9 +94,8 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
|
||||
// PowerPC wants to optimize integer setcc a bit
|
||||
setOperationAction(ISD::SETCC, MVT::i32, Custom);
|
||||
|
||||
// PowerPC does not have BRCOND* which requires SetCC
|
||||
setOperationAction(ISD::BRCOND, MVT::Other, Expand);
|
||||
setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
|
||||
// PowerPC does not have BRCOND which requires SetCC
|
||||
setOperationAction(ISD::BRCOND, MVT::Other, Expand);
|
||||
|
||||
// PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
|
||||
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
|
||||
|
||||
@ -245,8 +245,7 @@ let Defs = [LR] in
|
||||
|
||||
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
|
||||
noResults = 1, PPC970_Unit = 7 in {
|
||||
def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
|
||||
target:$true, target:$false),
|
||||
def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$true),
|
||||
"; COND_BRANCH", []>;
|
||||
def B : IForm<18, 0, 0, (ops target:$dst),
|
||||
"b $dst", BrB,
|
||||
|
||||
@ -10,41 +10,8 @@ still a codesize win.
|
||||
|
||||
===-------------------------------------------------------------------------===
|
||||
|
||||
Should hint to the branch select pass that it doesn't need to print the second
|
||||
unconditional branch, so we don't end up with things like:
|
||||
b .LBBl42__2E_expand_function_8_674 ; loopentry.24
|
||||
b .LBBl42__2E_expand_function_8_42 ; NewDefault
|
||||
b .LBBl42__2E_expand_function_8_42 ; NewDefault
|
||||
|
||||
This occurs in SPASS.
|
||||
|
||||
The power of diet coke came up with a solution to this today:
|
||||
|
||||
We know the only two cases that can happen here are either:
|
||||
a) we have a conditional branch followed by a fallthrough to the next BB
|
||||
b) we have a conditional branch followed by an unconditional branch
|
||||
|
||||
We also invented the BRTWOWAY node to model (b).
|
||||
|
||||
Currently, these are modeled by the PPC_BRCOND node which is a 12-byte pseudo
|
||||
that codegens to
|
||||
bccinv false
|
||||
true:
|
||||
b truebb
|
||||
false:
|
||||
b falsebb
|
||||
|
||||
However, realizing that for (a), we can bccinv directly to the fallthrough
|
||||
block, and for (b) we will already have another unconditional branch after
|
||||
the conditional branch (see SPASS case above), then we know that we don't need
|
||||
BRTWOWAY at all, and can just codegen PPC_BRCOND as
|
||||
|
||||
bccinv +8
|
||||
b truebb
|
||||
|
||||
This will also allow us to selectively not run the ppc branch selector, by just
|
||||
selecting PPC_BRCOND pseudo directly to the correct conditional branch
|
||||
instruction for small functions.
|
||||
Teach the .td file to pattern match PPC::BR_COND to appropriate bc variant, so
|
||||
we don't have to always run the branch selector for small functions.
|
||||
|
||||
===-------------------------------------------------------------------------===
|
||||
|
||||
|
||||
@ -17,7 +17,11 @@ We currently compile this into a memcpy from a static array into 'm', then
|
||||
a bunch of loads from m. It would be better to avoid the memcpy and just do
|
||||
loads from the static array.
|
||||
|
||||
===-------------------------------------------------------------------------===
|
||||
//===---------------------------------------------------------------------===//
|
||||
|
||||
Make the PPC branch selector target independant
|
||||
|
||||
//===---------------------------------------------------------------------===//
|
||||
|
||||
Get the C front-end to expand hypot(x,y) -> llvm.sqrt(x*x+y*y) when errno and
|
||||
precision don't matter (ffastmath). Misc/mandel will like this. :)
|
||||
|
||||
@ -166,8 +166,6 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
|
||||
|
||||
// Sparc doesn't have BRCOND either, it has BR_CC.
|
||||
setOperationAction(ISD::BRCOND, MVT::Other, Expand);
|
||||
setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
|
||||
setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
|
||||
setOperationAction(ISD::BR_CC, MVT::i32, Custom);
|
||||
setOperationAction(ISD::BR_CC, MVT::f32, Custom);
|
||||
setOperationAction(ISD::BR_CC, MVT::f64, Custom);
|
||||
|
||||
@ -125,8 +125,6 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
|
||||
setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
|
||||
|
||||
setOperationAction(ISD::BRCOND , MVT::Other, Custom);
|
||||
setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
|
||||
setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
|
||||
setOperationAction(ISD::BR_CC , MVT::Other, Expand);
|
||||
setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
|
||||
setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user