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Thumb2 assembly parsing and encoding for STMIA.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139938 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-09-16 20:50:13 +00:00
parent ffee5728af
commit 8213c96655
3 changed files with 55 additions and 1 deletions
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3
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -3861,3 +3861,6 @@ def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
(t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
// STM w/o the .w suffix.
def : t2InstAlias<"stm${p} $Rn, $regs",
(t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;

15
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -3679,7 +3679,7 @@ validateInstruction(MCInst &Inst,
}
case ARM::tSTMIA_UPD: {
bool listContainsBase;
if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase))
if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
return Error(Operands[4]->getStartLoc(),
"registers must be in range r0-r7");
break;
@ -3778,6 +3778,19 @@ processInstruction(MCInst &Inst,
}
break;
}
case ARM::tSTMIA_UPD: {
// If the register list contains any high registers, we need to use
// the 32-bit encoding instead if we're in Thumb2. Otherwise, this
// should have generated an error in validateInstruction().
unsigned Rn = Inst.getOperand(0).getReg();
bool listContainsBase;
if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
// 16-bit encoding isn't sufficient. Switch to the 32-bit version.
assert (isThumbTwo());
Inst.setOpcode(ARM::t2STMIA_UPD);
}
break;
}
case ARM::t2MOVi: {
// If we can use the 16-bit encoding and the user didn't explicitly
// request the 32-bit variant, transform it here.

38
test/MC/ARM/basic-thumb2-instructions.s
View File

@ -2108,6 +2108,44 @@ _func:
@ CHECK: ssub8eq r5, r1, r2 @ encoding: [0xc1,0xfa,0x02,0xf5]
@------------------------------------------------------------------------------
@ STMIA
@------------------------------------------------------------------------------
stmia.w r4, {r4, r5, r8, r9}
stmia.w r4, {r5, r6}
stmia.w r5!, {r3, r8}
stm.w r4, {r4, r5, r8, r9}
stm.w r4, {r5, r6}
stm.w r5!, {r3, r8}
stm.w r5!, {r1, r2}
stm.w r2, {r1, r2}
stmia r4, {r4, r5, r8, r9}
stmia r4, {r5, r6}
stmia r5!, {r3, r8}
stm r4, {r4, r5, r8, r9}
stm r4, {r5, r6}
stm r5!, {r3, r8}
stmea r5!, {r3, r8}
@ CHECK: stm.w r4, {r4, r5, r8, r9} @ encoding: [0x84,0xe8,0x30,0x03]
@ CHECK: stm.w r4, {r5, r6} @ encoding: [0x84,0xe8,0x60,0x00]
@ CHECK: stm.w r5!, {r3, r8} @ encoding: [0xa5,0xe8,0x08,0x01]
@ CHECK: stm.w r4, {r4, r5, r8, r9} @ encoding: [0x84,0xe8,0x30,0x03]
@ CHECK: stm.w r4, {r5, r6} @ encoding: [0x84,0xe8,0x60,0x00]
@ CHECK: stm.w r5!, {r3, r8} @ encoding: [0xa5,0xe8,0x08,0x01]
@ CHECK: stm.w r5!, {r1, r2} @ encoding: [0xa5,0xe8,0x06,0x00]
@ CHECK: stm.w r2, {r1, r2} @ encoding: [0x82,0xe8,0x06,0x00]
@ CHECK: stm.w r4, {r4, r5, r8, r9} @ encoding: [0x84,0xe8,0x30,0x03]
@ CHECK: stm.w r4, {r5, r6} @ encoding: [0x84,0xe8,0x60,0x00]
@ CHECK: stm.w r5!, {r3, r8} @ encoding: [0xa5,0xe8,0x08,0x01]
@ CHECK: stm.w r4, {r4, r5, r8, r9} @ encoding: [0x84,0xe8,0x30,0x03]
@ CHECK: stm.w r4, {r5, r6} @ encoding: [0x84,0xe8,0x60,0x00]
@ CHECK: stm.w r5!, {r3, r8} @ encoding: [0xa5,0xe8,0x08,0x01]
@ CHECK: stm.w r5!, {r3, r8} @ encoding: [0xa5,0xe8,0x08,0x01]
@------------------------------------------------------------------------------
@ SUB (register)
@------------------------------------------------------------------------------