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First cut, un-optimized (and untested) fast isel lowering of GetElementPtrInst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55085 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -23,7 +23,9 @@ namespace llvm {
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class MachineBasicBlock;
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class MachineFunction;
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class MachineRegisterInfo;
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class TargetData;
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class TargetInstrInfo;
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class TargetLowering;
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class TargetRegisterClass;
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/// FastISel - This is a fast-path instruction selection class that
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@ -33,7 +35,9 @@ class FastISel {
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MachineBasicBlock *MBB;
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MachineFunction &MF;
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MachineRegisterInfo &MRI;
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const TargetData &TD;
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const TargetInstrInfo &TII;
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TargetLowering &TLI;
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public:
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/// SelectInstructions - Do "fast" instruction selection over the
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@ -72,6 +76,29 @@ protected:
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ISD::NodeType Opcode,
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unsigned Op0, unsigned Op1);
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/// FastEmit_i - This method is called by target-independent code
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/// to request that an instruction with the given type which materialize
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/// the specified immediate value.
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virtual unsigned FastEmit_i(MVT::SimpleValueType VT, uint64_t Imm);
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/// FastEmit_ri - This method is called by target-independent code
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/// to request that an instruction with the given type, opcode, and
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/// register and immediate operands be emitted.
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///
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virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
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ISD::NodeType Opcode,
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unsigned Op0, uint64_t Imm,
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MVT::SimpleValueType ImmType);
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/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
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/// to emit an instruction with an immediate operand using FastEmit_ri.
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/// If that fails, it materializes the immediate into a register and try
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/// FastEmit_rr instead.
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unsigned FastEmit_ri_(MVT::SimpleValueType VT,
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ISD::NodeType Opcode,
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unsigned Op0, uint64_t Imm,
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MVT::SimpleValueType ImmType);
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/// FastEmitInst_ - Emit a MachineInstr with no operands and a
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/// result register in the given register class.
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///
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@ -15,7 +15,9 @@
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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@ -48,8 +50,81 @@ bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
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bool FastISel::SelectGetElementPtr(Instruction *I,
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DenseMap<const Value*, unsigned> &ValueMap) {
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// TODO: implement me
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return false;
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unsigned N = ValueMap[I->getOperand(0)];
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if (N == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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const Type *Ty = I->getOperand(0)->getType();
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MVT VT = MVT::getMVT(Ty, /*HandleUnknown=*/true);
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MVT::SimpleValueType PtrVT = TLI.getPointerTy().getSimpleVT();
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for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
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OI != E; ++OI) {
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Value *Idx = *OI;
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if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
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unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
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if (Field) {
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// N = N + Offset
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uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
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// FIXME: This can be optimized by combining the add with a
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// subsequent one.
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N = FastEmit_ri(VT.getSimpleVT(), ISD::ADD, N, Offs, PtrVT);
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if (N == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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}
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Ty = StTy->getElementType(Field);
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} else {
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Ty = cast<SequentialType>(Ty)->getElementType();
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// If this is a constant subscript, handle it quickly.
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if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
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if (CI->getZExtValue() == 0) continue;
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uint64_t Offs =
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TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
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N = FastEmit_ri(VT.getSimpleVT(), ISD::ADD, N, Offs, PtrVT);
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if (N == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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continue;
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}
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// N = N + Idx * ElementSize;
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uint64_t ElementSize = TD.getABITypeSize(Ty);
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unsigned IdxN = ValueMap[Idx];
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if (IdxN == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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// If the index is smaller or larger than intptr_t, truncate or extend
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// it.
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MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/true);
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if (IdxVT.bitsLT(VT))
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IdxN = FastEmit_r(VT.getSimpleVT(), ISD::SIGN_EXTEND, IdxN);
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else if (IdxVT.bitsGT(VT))
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IdxN = FastEmit_r(VT.getSimpleVT(), ISD::TRUNCATE, IdxN);
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if (IdxN == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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// FIXME: If multiple is power of two, turn it into a shift. The
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// optimization should be in FastEmit_ri?
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IdxN = FastEmit_ri(VT.getSimpleVT(), ISD::MUL, IdxN,
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ElementSize, PtrVT);
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if (IdxN == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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N = FastEmit_rr(VT.getSimpleVT(), ISD::ADD, N, IdxN);
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if (N == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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}
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}
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// We successfully emitted code for the given LLVM Instruction.
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ValueMap[I] = N;
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return true;
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}
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BasicBlock::iterator
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@ -131,7 +206,10 @@ FastISel::SelectInstructions(BasicBlock::iterator Begin,
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}
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FastISel::FastISel(MachineFunction &mf)
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: MF(mf), MRI(mf.getRegInfo()), TII(*mf.getTarget().getInstrInfo()) {
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: MF(mf), MRI(mf.getRegInfo()),
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TD(*mf.getTarget().getTargetData()),
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TII(*mf.getTarget().getInstrInfo()),
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TLI(*mf.getTarget().getTargetLowering()) {
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}
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FastISel::~FastISel() {}
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@ -150,6 +228,32 @@ unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, ISD::NodeType,
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return 0;
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}
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unsigned FastISel::FastEmit_i(MVT::SimpleValueType, uint64_t) {
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return 0;
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}
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unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, ISD::NodeType,
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unsigned /*Op0*/, uint64_t Imm,
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MVT::SimpleValueType ImmType) {
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return 0;
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}
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/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
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/// to emit an instruction with an immediate operand using FastEmit_ri.
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/// If that fails, it materializes the immediate into a register and try
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/// FastEmit_rr instead.
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unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
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unsigned Op0, uint64_t Imm,
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MVT::SimpleValueType ImmType) {
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unsigned ResultReg = 0;
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// First check if immediate type is legal. If not, we can't use the ri form.
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if (TLI.getOperationAction(ISD::Constant, ImmType) == TargetLowering::Legal)
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ResultReg = FastEmit_ri(VT, Opcode, Op0, Imm, ImmType);
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if (ResultReg != 0)
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return ResultReg;
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return FastEmit_rr(VT, Opcode, Op0, FastEmit_i(ImmType, Imm));
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}
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unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
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const TargetRegisterClass* RC) {
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unsigned ResultReg = MRI.createVirtualRegister(RC);
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@ -2807,9 +2807,9 @@ void SelectionDAGLowering::visitGetElementPtr(User &I) {
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// If the index is smaller or larger than intptr_t, truncate or extend
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// it.
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if (IdxN.getValueType().bitsLT(N.getValueType())) {
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if (IdxN.getValueType().bitsLT(N.getValueType()))
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IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
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} else if (IdxN.getValueType().bitsGT(N.getValueType()))
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else if (IdxN.getValueType().bitsGT(N.getValueType()))
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IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
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// If this is a multiply by a power of two, turn it into a shl
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