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Wrap MVT::ValueType in a struct to get type safety

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and better control the abstraction.  Rename the type
to MVT.  To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits().  Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duncan Sands 2008-06-06 12:08:01 +00:00
parent cc41940dff
commit 83ec4b6711
68 changed files with 2858 additions and 2841 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
docs/CodeGenerator.html
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@ -790,7 +790,8 @@ to the node defining the used value. Because nodes may define multiple values,
edges are represented by instances of the <tt>SDOperand</tt> class, which is
a <tt>&lt;SDNode, unsigned&gt;</tt> pair, indicating the node and result
value being used, respectively. Each value produced by an <tt>SDNode</tt> has
an associated <tt>MVT::ValueType</tt> indicating what type the value is.</p>
an associated <tt>MVT</tt> (Machine Value Type) indicating what the type of the
value is.</p>
<p>SelectionDAGs contain two different kinds of values: those that represent
data flow and those that represent control flow dependencies. Data values are

24
include/llvm/CodeGen/CallingConvLower.h
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@ -49,14 +49,14 @@ private:
LocInfo HTP : 7;
/// ValVT - The type of the value being assigned.
MVT::ValueType ValVT;
MVT ValVT;
/// LocVT - The type of the location being assigned to.
MVT::ValueType LocVT;
MVT LocVT;
public:
static CCValAssign getReg(unsigned ValNo, MVT::ValueType ValVT,
unsigned RegNo, MVT::ValueType LocVT,
static CCValAssign getReg(unsigned ValNo, MVT ValVT,
unsigned RegNo, MVT LocVT,
LocInfo HTP) {
CCValAssign Ret;
Ret.ValNo = ValNo;
@ -67,8 +67,8 @@ public:
Ret.LocVT = LocVT;
return Ret;
}
static CCValAssign getMem(unsigned ValNo, MVT::ValueType ValVT,
unsigned Offset, MVT::ValueType LocVT,
static CCValAssign getMem(unsigned ValNo, MVT ValVT,
unsigned Offset, MVT LocVT,
LocInfo HTP) {
CCValAssign Ret;
Ret.ValNo = ValNo;
@ -81,14 +81,14 @@ public:
}
unsigned getValNo() const { return ValNo; }
MVT::ValueType getValVT() const { return ValVT; }
MVT getValVT() const { return ValVT; }
bool isRegLoc() const { return !isMem; }
bool isMemLoc() const { return isMem; }
unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; }
MVT::ValueType getLocVT() const { return LocVT; }
MVT getLocVT() const { return LocVT; }
LocInfo getLocInfo() const { return HTP; }
};
@ -96,8 +96,8 @@ public:
/// CCAssignFn - This function assigns a location for Val, updating State to
/// reflect the change.
typedef bool CCAssignFn(unsigned ValNo, MVT::ValueType ValVT,
MVT::ValueType LocVT, CCValAssign::LocInfo LocInfo,
typedef bool CCAssignFn(unsigned ValNo, MVT ValVT,
MVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State);
@ -217,8 +217,8 @@ public:
// HandleByVal - Allocate a stack slot large enough to pass an argument by
// value. The size and alignment information of the argument is encoded in its
// parameter attribute.
void HandleByVal(unsigned ValNo, MVT::ValueType ValVT,
MVT::ValueType LocVT, CCValAssign::LocInfo LocInfo,
void HandleByVal(unsigned ValNo, MVT ValVT,
MVT LocVT, CCValAssign::LocInfo LocInfo,
int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags);
private:

197
include/llvm/CodeGen/SelectionDAG.h
View File

@ -144,24 +144,22 @@ public:
/// getVTList - Return an SDVTList that represents the list of values
/// specified.
SDVTList getVTList(MVT::ValueType VT);
SDVTList getVTList(MVT::ValueType VT1, MVT::ValueType VT2);
SDVTList getVTList(MVT::ValueType VT1, MVT::ValueType VT2,MVT::ValueType VT3);
SDVTList getVTList(const MVT::ValueType *VTs, unsigned NumVTs);
SDVTList getVTList(MVT VT);
SDVTList getVTList(MVT VT1, MVT VT2);
SDVTList getVTList(MVT VT1, MVT VT2, MVT VT3);
SDVTList getVTList(const MVT *VTs, unsigned NumVTs);
/// getNodeValueTypes - These are obsolete, use getVTList instead.
const MVT::ValueType *getNodeValueTypes(MVT::ValueType VT) {
const MVT *getNodeValueTypes(MVT VT) {
return getVTList(VT).VTs;
}
const MVT::ValueType *getNodeValueTypes(MVT::ValueType VT1,
MVT::ValueType VT2) {
const MVT *getNodeValueTypes(MVT VT1, MVT VT2) {
return getVTList(VT1, VT2).VTs;
}
const MVT::ValueType *getNodeValueTypes(MVT::ValueType VT1,MVT::ValueType VT2,
MVT::ValueType VT3) {
const MVT *getNodeValueTypes(MVT VT1, MVT VT2, MVT VT3) {
return getVTList(VT1, VT2, VT3).VTs;
}
const MVT::ValueType *getNodeValueTypes(std::vector<MVT::ValueType> &vtList) {
const MVT *getNodeValueTypes(std::vector<MVT> &vtList) {
return getVTList(&vtList[0], (unsigned)vtList.size()).VTs;
}
@ -170,57 +168,56 @@ public:
// Node creation methods.
//
SDOperand getString(const std::string &Val);
SDOperand getConstant(uint64_t Val, MVT::ValueType VT, bool isTarget = false);
SDOperand getConstant(const APInt &Val, MVT::ValueType VT, bool isTarget = false);
SDOperand getConstant(uint64_t Val, MVT VT, bool isTarget = false);
SDOperand getConstant(const APInt &Val, MVT VT, bool isTarget = false);
SDOperand getIntPtrConstant(uint64_t Val, bool isTarget = false);
SDOperand getTargetConstant(uint64_t Val, MVT::ValueType VT) {
SDOperand getTargetConstant(uint64_t Val, MVT VT) {
return getConstant(Val, VT, true);
}
SDOperand getTargetConstant(const APInt &Val, MVT::ValueType VT) {
SDOperand getTargetConstant(const APInt &Val, MVT VT) {
return getConstant(Val, VT, true);
}
SDOperand getConstantFP(double Val, MVT::ValueType VT, bool isTarget = false);
SDOperand getConstantFP(const APFloat& Val, MVT::ValueType VT,
bool isTarget = false);
SDOperand getTargetConstantFP(double Val, MVT::ValueType VT) {
SDOperand getConstantFP(double Val, MVT VT, bool isTarget = false);
SDOperand getConstantFP(const APFloat& Val, MVT VT, bool isTarget = false);
SDOperand getTargetConstantFP(double Val, MVT VT) {
return getConstantFP(Val, VT, true);
}
SDOperand getTargetConstantFP(const APFloat& Val, MVT::ValueType VT) {
SDOperand getTargetConstantFP(const APFloat& Val, MVT VT) {
return getConstantFP(Val, VT, true);
}
SDOperand getGlobalAddress(const GlobalValue *GV, MVT::ValueType VT,
SDOperand getGlobalAddress(const GlobalValue *GV, MVT VT,
int offset = 0, bool isTargetGA = false);
SDOperand getTargetGlobalAddress(const GlobalValue *GV, MVT::ValueType VT,
SDOperand getTargetGlobalAddress(const GlobalValue *GV, MVT VT,
int offset = 0) {
return getGlobalAddress(GV, VT, offset, true);
}
SDOperand getFrameIndex(int FI, MVT::ValueType VT, bool isTarget = false);
SDOperand getTargetFrameIndex(int FI, MVT::ValueType VT) {
SDOperand getFrameIndex(int FI, MVT VT, bool isTarget = false);
SDOperand getTargetFrameIndex(int FI, MVT VT) {
return getFrameIndex(FI, VT, true);
}
SDOperand getJumpTable(int JTI, MVT::ValueType VT, bool isTarget = false);
SDOperand getTargetJumpTable(int JTI, MVT::ValueType VT) {
SDOperand getJumpTable(int JTI, MVT VT, bool isTarget = false);
SDOperand getTargetJumpTable(int JTI, MVT VT) {
return getJumpTable(JTI, VT, true);
}
SDOperand getConstantPool(Constant *C, MVT::ValueType VT,
SDOperand getConstantPool(Constant *C, MVT VT,
unsigned Align = 0, int Offs = 0, bool isT=false);
SDOperand getTargetConstantPool(Constant *C, MVT::ValueType VT,
SDOperand getTargetConstantPool(Constant *C, MVT VT,
unsigned Align = 0, int Offset = 0) {
return getConstantPool(C, VT, Align, Offset, true);
}
SDOperand getConstantPool(MachineConstantPoolValue *C, MVT::ValueType VT,
SDOperand getConstantPool(MachineConstantPoolValue *C, MVT VT,
unsigned Align = 0, int Offs = 0, bool isT=false);
SDOperand getTargetConstantPool(MachineConstantPoolValue *C,
MVT::ValueType VT, unsigned Align = 0,
MVT VT, unsigned Align = 0,
int Offset = 0) {
return getConstantPool(C, VT, Align, Offset, true);
}
SDOperand getBasicBlock(MachineBasicBlock *MBB);
SDOperand getExternalSymbol(const char *Sym, MVT::ValueType VT);
SDOperand getTargetExternalSymbol(const char *Sym, MVT::ValueType VT);
SDOperand getExternalSymbol(const char *Sym, MVT VT);
SDOperand getTargetExternalSymbol(const char *Sym, MVT VT);
SDOperand getArgFlags(ISD::ArgFlagsTy Flags);
SDOperand getValueType(MVT::ValueType);
SDOperand getRegister(unsigned Reg, MVT::ValueType VT);
SDOperand getValueType(MVT);
SDOperand getRegister(unsigned Reg, MVT VT);
SDOperand getCopyToReg(SDOperand Chain, unsigned Reg, SDOperand N) {
return getNode(ISD::CopyToReg, MVT::Other, Chain,
@ -232,7 +229,7 @@ public:
// null) and that there should be a flag result.
SDOperand getCopyToReg(SDOperand Chain, unsigned Reg, SDOperand N,
SDOperand Flag) {
const MVT::ValueType *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
SDOperand Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Flag };
return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.Val ? 4 : 3);
}
@ -240,13 +237,13 @@ public:
// Similar to last getCopyToReg() except parameter Reg is a SDOperand
SDOperand getCopyToReg(SDOperand Chain, SDOperand Reg, SDOperand N,
SDOperand Flag) {
const MVT::ValueType *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
SDOperand Ops[] = { Chain, Reg, N, Flag };
return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.Val ? 4 : 3);
}
SDOperand getCopyFromReg(SDOperand Chain, unsigned Reg, MVT::ValueType VT) {
const MVT::ValueType *VTs = getNodeValueTypes(VT, MVT::Other);
SDOperand getCopyFromReg(SDOperand Chain, unsigned Reg, MVT VT) {
const MVT *VTs = getNodeValueTypes(VT, MVT::Other);
SDOperand Ops[] = { Chain, getRegister(Reg, VT) };
return getNode(ISD::CopyFromReg, VTs, 2, Ops, 2);
}
@ -254,9 +251,9 @@ public:
// This version of the getCopyFromReg method takes an extra operand, which
// indicates that there is potentially an incoming flag value (if Flag is not
// null) and that there should be a flag result.
SDOperand getCopyFromReg(SDOperand Chain, unsigned Reg, MVT::ValueType VT,
SDOperand getCopyFromReg(SDOperand Chain, unsigned Reg, MVT VT,
SDOperand Flag) {
const MVT::ValueType *VTs = getNodeValueTypes(VT, MVT::Other, MVT::Flag);
const MVT *VTs = getNodeValueTypes(VT, MVT::Other, MVT::Flag);
SDOperand Ops[] = { Chain, getRegister(Reg, VT), Flag };
return getNode(ISD::CopyFromReg, VTs, 3, Ops, Flag.Val ? 3 : 2);
}
@ -265,12 +262,12 @@ public:
/// getZeroExtendInReg - Return the expression required to zero extend the Op
/// value assuming it was the smaller SrcTy value.
SDOperand getZeroExtendInReg(SDOperand Op, MVT::ValueType SrcTy);
SDOperand getZeroExtendInReg(SDOperand Op, MVT SrcTy);
/// getCALLSEQ_START - Return a new CALLSEQ_START node, which always must have
/// a flag result (to ensure it's not CSE'd).
SDOperand getCALLSEQ_START(SDOperand Chain, SDOperand Op) {
const MVT::ValueType *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
SDOperand Ops[] = { Chain, Op };
return getNode(ISD::CALLSEQ_START, VTs, 2, Ops, 2);
}
@ -291,27 +288,24 @@ public:
/// getNode - Gets or creates the specified node.
///
SDOperand getNode(unsigned Opcode, MVT::ValueType VT);
SDOperand getNode(unsigned Opcode, MVT::ValueType VT, SDOperand N);
SDOperand getNode(unsigned Opcode, MVT::ValueType VT,
SDOperand N1, SDOperand N2);
SDOperand getNode(unsigned Opcode, MVT::ValueType VT,
SDOperand getNode(unsigned Opcode, MVT VT);
SDOperand getNode(unsigned Opcode, MVT VT, SDOperand N);
SDOperand getNode(unsigned Opcode, MVT VT, SDOperand N1, SDOperand N2);
SDOperand getNode(unsigned Opcode, MVT VT,
SDOperand N1, SDOperand N2, SDOperand N3);
SDOperand getNode(unsigned Opcode, MVT::ValueType VT,
SDOperand getNode(unsigned Opcode, MVT VT,
SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4);
SDOperand getNode(unsigned Opcode, MVT::ValueType VT,
SDOperand getNode(unsigned Opcode, MVT VT,
SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4,
SDOperand N5);
SDOperand getNode(unsigned Opcode, MVT::ValueType VT,
SDOperand getNode(unsigned Opcode, MVT VT, SDOperandPtr Ops, unsigned NumOps);
SDOperand getNode(unsigned Opcode, std::vector<MVT> &ResultTys,
SDOperandPtr Ops, unsigned NumOps);
SDOperand getNode(unsigned Opcode, std::vector<MVT::ValueType> &ResultTys,
SDOperandPtr Ops, unsigned NumOps);
SDOperand getNode(unsigned Opcode, const MVT::ValueType *VTs, unsigned NumVTs,
SDOperand getNode(unsigned Opcode, const MVT *VTs, unsigned NumVTs,
SDOperandPtr Ops, unsigned NumOps);
SDOperand getNode(unsigned Opcode, SDVTList VTs);
SDOperand getNode(unsigned Opcode, SDVTList VTs, SDOperand N);
SDOperand getNode(unsigned Opcode, SDVTList VTs,
SDOperand N1, SDOperand N2);
SDOperand getNode(unsigned Opcode, SDVTList VTs, SDOperand N1, SDOperand N2);
SDOperand getNode(unsigned Opcode, SDVTList VTs,
SDOperand N1, SDOperand N2, SDOperand N3);
SDOperand getNode(unsigned Opcode, SDVTList VTs,
@ -340,7 +334,7 @@ public:
/// getSetCC - Helper function to make it easier to build SetCC's if you just
/// have an ISD::CondCode instead of an SDOperand.
///
SDOperand getSetCC(MVT::ValueType VT, SDOperand LHS, SDOperand RHS,
SDOperand getSetCC(MVT VT, SDOperand LHS, SDOperand RHS,
ISD::CondCode Cond) {
return getNode(ISD::SETCC, VT, LHS, RHS, getCondCode(Cond));
}
@ -348,7 +342,7 @@ public:
/// getVSetCC - Helper function to make it easier to build VSetCC's nodes
/// if you just have an ISD::CondCode instead of an SDOperand.
///
SDOperand getVSetCC(MVT::ValueType VT, SDOperand LHS, SDOperand RHS,
SDOperand getVSetCC(MVT VT, SDOperand LHS, SDOperand RHS,
ISD::CondCode Cond) {
return getNode(ISD::VSETCC, VT, LHS, RHS, getCondCode(Cond));
}
@ -364,35 +358,35 @@ public:
/// getVAArg - VAArg produces a result and token chain, and takes a pointer
/// and a source value as input.
SDOperand getVAArg(MVT::ValueType VT, SDOperand Chain, SDOperand Ptr,
SDOperand getVAArg(MVT VT, SDOperand Chain, SDOperand Ptr,
SDOperand SV);
/// getAtomic - Gets a node for an atomic op, produces result and chain, takes
// 3 operands
SDOperand getAtomic(unsigned Opcode, SDOperand Chain, SDOperand Ptr,
SDOperand Cmp, SDOperand Swp, MVT::ValueType VT);
SDOperand Cmp, SDOperand Swp, MVT VT);
/// getAtomic - Gets a node for an atomic op, produces result and chain, takes
// 2 operands
SDOperand getAtomic(unsigned Opcode, SDOperand Chain, SDOperand Ptr,
SDOperand Val, MVT::ValueType VT);
SDOperand Val, MVT VT);
/// getLoad - Loads are not normal binary operators: their result type is not
/// determined by their operands, and they produce a value AND a token chain.
///
SDOperand getLoad(MVT::ValueType VT, SDOperand Chain, SDOperand Ptr,
SDOperand getLoad(MVT VT, SDOperand Chain, SDOperand Ptr,
const Value *SV, int SVOffset, bool isVolatile=false,
unsigned Alignment=0);
SDOperand getExtLoad(ISD::LoadExtType ExtType, MVT::ValueType VT,
SDOperand getExtLoad(ISD::LoadExtType ExtType, MVT VT,
SDOperand Chain, SDOperand Ptr, const Value *SV,
int SVOffset, MVT::ValueType EVT, bool isVolatile=false,
int SVOffset, MVT EVT, bool isVolatile=false,
unsigned Alignment=0);
SDOperand getIndexedLoad(SDOperand OrigLoad, SDOperand Base,
SDOperand Offset, ISD::MemIndexedMode AM);
SDOperand getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
MVT::ValueType VT, SDOperand Chain,
MVT VT, SDOperand Chain,
SDOperand Ptr, SDOperand Offset,
const Value *SV, int SVOffset, MVT::ValueType EVT,
const Value *SV, int SVOffset, MVT EVT,
bool isVolatile=false, unsigned Alignment=0);
/// getStore - Helper function to build ISD::STORE nodes.
@ -401,7 +395,7 @@ public:
const Value *SV, int SVOffset, bool isVolatile=false,
unsigned Alignment=0);
SDOperand getTruncStore(SDOperand Chain, SDOperand Val, SDOperand Ptr,
const Value *SV, int SVOffset, MVT::ValueType TVT,
const Value *SV, int SVOffset, MVT TVT,
bool isVolatile=false, unsigned Alignment=0);
SDOperand getIndexedStore(SDOperand OrigStoe, SDOperand Base,
SDOperand Offset, ISD::MemIndexedMode AM);
@ -434,20 +428,18 @@ public:
/// operands. Note that target opcodes are stored as
/// ISD::BUILTIN_OP_END+TargetOpcode in the node opcode field. The 0th value
/// of the resultant node is returned.
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT,
SDOperand Op1);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT,
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT, SDOperand Op1);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT,
SDOperand Op1, SDOperand Op2);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT,
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT,
SDOperand Op1, SDOperand Op2, SDOperand Op3);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT,
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT,
SDOperandPtr Ops, unsigned NumOps);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT1,
MVT::ValueType VT2, SDOperand Op1, SDOperand Op2);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT1,
MVT::ValueType VT2, SDOperand Op1, SDOperand Op2,
SDOperand Op3);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
MVT VT2, SDOperand Op1, SDOperand Op2);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
MVT VT2, SDOperand Op1, SDOperand Op2, SDOperand Op3);
/// getTargetNode - These are used for target selectors to create a new node
@ -456,41 +448,30 @@ public:
/// Note that getTargetNode returns the resultant node. If there is already a
/// node of the specified opcode and operands, it returns that node instead of
/// the current one.
SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT);
SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT,
SDOperand Op1);
SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT,
SDOperand Op1, SDOperand Op2);
SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT,
SDNode *getTargetNode(unsigned Opcode, MVT VT);
SDNode *getTargetNode(unsigned Opcode, MVT VT, SDOperand Op1);
SDNode *getTargetNode(unsigned Opcode, MVT VT, SDOperand Op1, SDOperand Op2);
SDNode *getTargetNode(unsigned Opcode, MVT VT,
SDOperand Op1, SDOperand Op2, SDOperand Op3);
SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT,
SDNode *getTargetNode(unsigned Opcode, MVT VT,
SDOperandPtr Ops, unsigned NumOps);
SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2);
SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2, SDOperand Op1);
SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2, SDOperand Op1, SDOperand Op2);
SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2, SDOperand Op1, SDOperand Op2,
SDOperand Op3);
SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2,
SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2);
SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, SDOperand Op1);
SDNode *getTargetNode(unsigned Opcode, MVT VT1,
MVT VT2, SDOperand Op1, SDOperand Op2);
SDNode *getTargetNode(unsigned Opcode, MVT VT1,
MVT VT2, SDOperand Op1, SDOperand Op2, SDOperand Op3);
SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2,
SDOperandPtr Ops, unsigned NumOps);
SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2, MVT::ValueType VT3,
SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
SDOperand Op1, SDOperand Op2);
SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2, MVT::ValueType VT3,
SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
SDOperand Op1, SDOperand Op2, SDOperand Op3);
SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2, MVT::ValueType VT3,
SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
SDOperandPtr Ops, unsigned NumOps);
SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2, MVT::ValueType VT3,
MVT::ValueType VT4,
SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, MVT VT4,
SDOperandPtr Ops, unsigned NumOps);
SDNode *getTargetNode(unsigned Opcode, std::vector<MVT::ValueType> &ResultTys,
SDNode *getTargetNode(unsigned Opcode, std::vector<MVT> &ResultTys,
SDOperandPtr Ops, unsigned NumOps);
/// getNodeIfExists - Get the specified node if it's already available, or
@ -570,10 +551,10 @@ public:
/// CreateStackTemporary - Create a stack temporary, suitable for holding the
/// specified value type.
SDOperand CreateStackTemporary(MVT::ValueType VT);
SDOperand CreateStackTemporary(MVT VT);
/// FoldSetCC - Constant fold a setcc to true or false.
SDOperand FoldSetCC(MVT::ValueType VT, SDOperand N1,
SDOperand FoldSetCC(MVT VT, SDOperand N1,
SDOperand N2, ISD::CondCode Cond);
/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We
@ -623,13 +604,13 @@ private:
void DeleteNodeNotInCSEMaps(SDNode *N);
// List of non-single value types.
std::list<std::vector<MVT::ValueType> > VTList;
std::list<std::vector<MVT> > VTList;
// Maps to auto-CSE operations.
std::vector<CondCodeSDNode*> CondCodeNodes;
std::vector<SDNode*> ValueTypeNodes;
std::map<MVT::ValueType, SDNode*> ExtendedValueTypeNodes;
std::map<MVT, SDNode*> ExtendedValueTypeNodes;
std::map<std::string, SDNode*> ExternalSymbols;
std::map<std::string, SDNode*> TargetExternalSymbols;
std::map<std::string, StringSDNode*> StringNodes;

2
include/llvm/CodeGen/SelectionDAGISel.h
View File

@ -55,7 +55,7 @@ public:
virtual bool runOnFunction(Function &Fn);
unsigned MakeReg(MVT::ValueType VT);
unsigned MakeReg(MVT VT);
virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;

79
include/llvm/CodeGen/SelectionDAGNodes.h
View File

@ -48,7 +48,7 @@ template<typename NodeTy> class ilist_iterator;
/// SelectionDAG::getVTList(...).
///
struct SDVTList {
const MVT::ValueType *VTs;
const MVT *VTs;
unsigned short NumVTs;
};
@ -834,12 +834,12 @@ public:
/// getValueType - Return the ValueType of the referenced return value.
///
inline MVT::ValueType getValueType() const;
inline MVT getValueType() const;
/// getValueSizeInBits - Returns MVT::getSizeInBits(getValueType()).
/// getValueSizeInBits - Returns the size of the value in bits.
///
unsigned getValueSizeInBits() const {
return MVT::getSizeInBits(getValueType());
return getValueType().getSizeInBits();
}
// Forwarding methods - These forward to the corresponding methods in SDNode.
@ -1045,7 +1045,7 @@ private:
/// ValueList - The types of the values this node defines. SDNode's may
/// define multiple values simultaneously.
const MVT::ValueType *ValueList;
const MVT *ValueList;
/// NumOperands/NumValues - The number of entries in the Operand/Value list.
unsigned short NumOperands, NumValues;
@ -1216,7 +1216,7 @@ public:
/// getValueType - Return the type of a specified result.
///
MVT::ValueType getValueType(unsigned ResNo) const {
MVT getValueType(unsigned ResNo) const {
assert(ResNo < NumValues && "Illegal result number!");
return ValueList[ResNo];
}
@ -1224,10 +1224,10 @@ public:
/// getValueSizeInBits - Returns MVT::getSizeInBits(getValueType(ResNo)).
///
unsigned getValueSizeInBits(unsigned ResNo) const {
return MVT::getSizeInBits(getValueType(ResNo));
return getValueType(ResNo).getSizeInBits();
}
typedef const MVT::ValueType* value_iterator;
typedef const MVT* value_iterator;
value_iterator value_begin() const { return ValueList; }
value_iterator value_end() const { return ValueList+NumValues; }
@ -1249,8 +1249,8 @@ protected:
/// getValueTypeList - Return a pointer to the specified value type.
///
static const MVT::ValueType *getValueTypeList(MVT::ValueType VT);
static SDVTList getSDVTList(MVT::ValueType VT) {
static const MVT *getValueTypeList(MVT VT);
static SDVTList getSDVTList(MVT VT) {
SDVTList Ret = { getValueTypeList(VT), 1 };
return Ret;
}
@ -1344,7 +1344,7 @@ protected:
inline unsigned SDOperand::getOpcode() const {
return Val->getOpcode();
}
inline MVT::ValueType SDOperand::getValueType() const {
inline MVT SDOperand::getValueType() const {
return Val->getValueType(ResNo);
}
inline unsigned SDOperand::getNumOperands() const {
@ -1439,10 +1439,10 @@ public:
class AtomicSDNode : public SDNode {
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
SDUse Ops[4];
MVT::ValueType OrigVT;
MVT OrigVT;
public:
AtomicSDNode(unsigned Opc, SDVTList VTL, SDOperand Chain, SDOperand Ptr,
SDOperand Cmp, SDOperand Swp, MVT::ValueType VT)
SDOperand Cmp, SDOperand Swp, MVT VT)
: SDNode(Opc, VTL) {
Ops[0] = Chain;
Ops[1] = Ptr;
@ -1452,7 +1452,7 @@ public:
OrigVT=VT;
}
AtomicSDNode(unsigned Opc, SDVTList VTL, SDOperand Chain, SDOperand Ptr,
SDOperand Val, MVT::ValueType VT)
SDOperand Val, MVT VT)
: SDNode(Opc, VTL) {
Ops[0] = Chain;
Ops[1] = Ptr;
@ -1460,7 +1460,7 @@ public:
InitOperands(Ops, 3);
OrigVT=VT;
}
MVT::ValueType getVT() const { return OrigVT; }
MVT getVT() const { return OrigVT; }
bool isCompareAndSwap() const { return getOpcode() == ISD::ATOMIC_LCS; }
};
@ -1485,7 +1485,7 @@ class ConstantSDNode : public SDNode {
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
protected:
friend class SelectionDAG;
ConstantSDNode(bool isTarget, const APInt &val, MVT::ValueType VT)
ConstantSDNode(bool isTarget, const APInt &val, MVT VT)
: SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, getSDVTList(VT)),
Value(val) {
}
@ -1495,13 +1495,13 @@ public:
uint64_t getValue() const { return Value.getZExtValue(); }
int64_t getSignExtended() const {
unsigned Bits = MVT::getSizeInBits(getValueType(0));
unsigned Bits = getValueType(0).getSizeInBits();
return ((int64_t)Value.getZExtValue() << (64-Bits)) >> (64-Bits);
}
bool isNullValue() const { return Value == 0; }
bool isAllOnesValue() const {
return Value == MVT::getIntVTBitMask(getValueType(0));
return Value == getValueType(0).getIntegerVTBitMask();
}
static bool classof(const ConstantSDNode *) { return true; }
@ -1516,7 +1516,7 @@ class ConstantFPSDNode : public SDNode {
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
protected:
friend class SelectionDAG;
ConstantFPSDNode(bool isTarget, const APFloat& val, MVT::ValueType VT)
ConstantFPSDNode(bool isTarget, const APFloat& val, MVT VT)
: SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP,
getSDVTList(VT)), Value(val) {
}
@ -1542,7 +1542,7 @@ public:
}
bool isExactlyValue(const APFloat& V) const;
bool isValueValidForType(MVT::ValueType VT, const APFloat& Val);
bool isValueValidForType(MVT VT, const APFloat& Val);
static bool classof(const ConstantFPSDNode *) { return true; }
static bool classof(const SDNode *N) {
@ -1557,8 +1557,7 @@ class GlobalAddressSDNode : public SDNode {
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
protected:
friend class SelectionDAG;
GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, MVT::ValueType VT,
int o = 0);
GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, MVT VT, int o = 0);
public:
GlobalValue *getGlobal() const { return TheGlobal; }
@ -1578,7 +1577,7 @@ class FrameIndexSDNode : public SDNode {
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
protected:
friend class SelectionDAG;
FrameIndexSDNode(int fi, MVT::ValueType VT, bool isTarg)
FrameIndexSDNode(int fi, MVT VT, bool isTarg)
: SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex, getSDVTList(VT)),
FI(fi) {
}
@ -1598,7 +1597,7 @@ class JumpTableSDNode : public SDNode {
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
protected:
friend class SelectionDAG;
JumpTableSDNode(int jti, MVT::ValueType VT, bool isTarg)
JumpTableSDNode(int jti, MVT VT, bool isTarg)
: SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable, getSDVTList(VT)),
JTI(jti) {
}
@ -1623,22 +1622,20 @@ class ConstantPoolSDNode : public SDNode {
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
protected:
friend class SelectionDAG;
ConstantPoolSDNode(bool isTarget, Constant *c, MVT::ValueType VT,
int o=0)
ConstantPoolSDNode(bool isTarget, Constant *c, MVT VT, int o=0)
: SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,
getSDVTList(VT)), Offset(o), Alignment(0) {
assert((int)Offset >= 0 && "Offset is too large");
Val.ConstVal = c;
}
ConstantPoolSDNode(bool isTarget, Constant *c, MVT::ValueType VT, int o,
unsigned Align)
ConstantPoolSDNode(bool isTarget, Constant *c, MVT VT, int o, unsigned Align)
: SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,
getSDVTList(VT)), Offset(o), Alignment(Align) {
assert((int)Offset >= 0 && "Offset is too large");
Val.ConstVal = c;
}
ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v,
MVT::ValueType VT, int o=0)
MVT VT, int o=0)
: SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,
getSDVTList(VT)), Offset(o), Alignment(0) {
assert((int)Offset >= 0 && "Offset is too large");
@ -1646,7 +1643,7 @@ protected:
Offset |= 1 << (sizeof(unsigned)*8-1);
}
ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v,
MVT::ValueType VT, int o, unsigned Align)
MVT VT, int o, unsigned Align)
: SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,
getSDVTList(VT)), Offset(o), Alignment(Align) {
assert((int)Offset >= 0 && "Offset is too large");
@ -1760,7 +1757,7 @@ class RegisterSDNode : public SDNode {
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
protected:
friend class SelectionDAG;
RegisterSDNode(unsigned reg, MVT::ValueType VT)
RegisterSDNode(unsigned reg, MVT VT)
: SDNode(ISD::Register, getSDVTList(VT)), Reg(reg) {
}
public:
@ -1778,7 +1775,7 @@ class ExternalSymbolSDNode : public SDNode {
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
protected:
friend class SelectionDAG;
ExternalSymbolSDNode(bool isTarget, const char *Sym, MVT::ValueType VT)
ExternalSymbolSDNode(bool isTarget, const char *Sym, MVT VT)
: SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol,
getSDVTList(VT)), Symbol(Sym) {
}
@ -1914,19 +1911,19 @@ public:
}
};
/// VTSDNode - This class is used to represent MVT::ValueType's, which are used
/// VTSDNode - This class is used to represent MVT's, which are used
/// to parameterize some operations.
class VTSDNode : public SDNode {
MVT::ValueType ValueType;
MVT ValueType;
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
protected:
friend class SelectionDAG;
explicit VTSDNode(MVT::ValueType VT)
explicit VTSDNode(MVT VT)
: SDNode(ISD::VALUETYPE, getSDVTList(MVT::Other)), ValueType(VT) {
}
public:
MVT::ValueType getVT() const { return ValueType; }
MVT getVT() const { return ValueType; }
static bool classof(const VTSDNode *) { return true; }
static bool classof(const SDNode *N) {
@ -1942,7 +1939,7 @@ private:
ISD::MemIndexedMode AddrMode;
// MemoryVT - VT of in-memory value.
MVT::ValueType MemoryVT;
MVT MemoryVT;
//! SrcValue - Memory location for alias analysis.
const Value *SrcValue;
@ -1965,7 +1962,7 @@ protected:
SDUse Ops[4];
public:
LSBaseSDNode(ISD::NodeType NodeTy, SDOperand *Operands, unsigned numOperands,
SDVTList VTs, ISD::MemIndexedMode AM, MVT::ValueType VT,
SDVTList VTs, ISD::MemIndexedMode AM, MVT VT,
const Value *SV, int SVO, unsigned Align, bool Vol)
: SDNode(NodeTy, VTs),
AddrMode(AM), MemoryVT(VT),
@ -1989,7 +1986,7 @@ public:
const Value *getSrcValue() const { return SrcValue; }
int getSrcValueOffset() const { return SVOffset; }
unsigned getAlignment() const { return Alignment; }
MVT::ValueType getMemoryVT() const { return MemoryVT; }
MVT getMemoryVT() const { return MemoryVT; }
bool isVolatile() const { return IsVolatile; }
ISD::MemIndexedMode getAddressingMode() const { return AddrMode; }
@ -2022,7 +2019,7 @@ class LoadSDNode : public LSBaseSDNode {
protected:
friend class SelectionDAG;
LoadSDNode(SDOperand *ChainPtrOff, SDVTList VTs,
ISD::MemIndexedMode AM, ISD::LoadExtType ETy, MVT::ValueType LVT,
ISD::MemIndexedMode AM, ISD::LoadExtType ETy, MVT LVT,
const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
: LSBaseSDNode(ISD::LOAD, ChainPtrOff, 3,
VTs, AM, LVT, SV, O, Align, Vol),
@ -2049,7 +2046,7 @@ class StoreSDNode : public LSBaseSDNode {
protected:
friend class SelectionDAG;
StoreSDNode(SDOperand *ChainValuePtrOff, SDVTList VTs,
ISD::MemIndexedMode AM, bool isTrunc, MVT::ValueType SVT,
ISD::MemIndexedMode AM, bool isTrunc, MVT SVT,
const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
: LSBaseSDNode(ISD::STORE, ChainValuePtrOff, 4,
VTs, AM, SVT, SV, O, Align, Vol),

723
include/llvm/CodeGen/ValueTypes.h
View File

@ -24,369 +24,390 @@
namespace llvm {
class Type;
/// MVT namespace - This namespace defines the SimpleValueType enum, which
/// contains the various low-level value types, and the ValueType typedef.
///
namespace MVT { // MVT = Machine Value Types
enum SimpleValueType {
// If you change this numbering, you must change the values in ValueTypes.td
// well!
Other = 0, // This is a non-standard value
i1 = 1, // This is a 1 bit integer value
i8 = 2, // This is an 8 bit integer value
i16 = 3, // This is a 16 bit integer value
i32 = 4, // This is a 32 bit integer value
i64 = 5, // This is a 64 bit integer value
i128 = 6, // This is a 128 bit integer value
struct MVT { // MVT = Machine Value Type
FIRST_INTEGER_VALUETYPE = i1,
LAST_INTEGER_VALUETYPE = i128,
enum SimpleValueType {
// If you change this numbering, you must change the values in
// ValueTypes.td well!
Other = 0, // This is a non-standard value
i1 = 1, // This is a 1 bit integer value
i8 = 2, // This is an 8 bit integer value
i16 = 3, // This is a 16 bit integer value
i32 = 4, // This is a 32 bit integer value
i64 = 5, // This is a 64 bit integer value
i128 = 6, // This is a 128 bit integer value
f32 = 7, // This is a 32 bit floating point value
f64 = 8, // This is a 64 bit floating point value
f80 = 9, // This is a 80 bit floating point value
f128 = 10, // This is a 128 bit floating point value
ppcf128 = 11, // This is a PPC 128-bit floating point value
Flag = 12, // This is a condition code or machine flag.
FIRST_INTEGER_VALUETYPE = i1,
LAST_INTEGER_VALUETYPE = i128,
isVoid = 13, // This has no value
f32 = 7, // This is a 32 bit floating point value
f64 = 8, // This is a 64 bit floating point value
f80 = 9, // This is a 80 bit floating point value
f128 = 10, // This is a 128 bit floating point value
ppcf128 = 11, // This is a PPC 128-bit floating point value
Flag = 12, // This is a condition code or machine flag.
v8i8 = 14, // 8 x i8
v4i16 = 15, // 4 x i16
v2i32 = 16, // 2 x i32
v1i64 = 17, // 1 x i64
v16i8 = 18, // 16 x i8
v8i16 = 19, // 8 x i16
v3i32 = 20, // 3 x i32
v4i32 = 21, // 4 x i32
v2i64 = 22, // 2 x i64
isVoid = 13, // This has no value
v2f32 = 23, // 2 x f32
v3f32 = 24, // 3 x f32
v4f32 = 25, // 4 x f32
v2f64 = 26, // 2 x f64
v8i8 = 14, // 8 x i8
v4i16 = 15, // 4 x i16
v2i32 = 16, // 2 x i32
v1i64 = 17, // 1 x i64
v16i8 = 18, // 16 x i8
v8i16 = 19, // 8 x i16
v3i32 = 20, // 3 x i32
v4i32 = 21, // 4 x i32
v2i64 = 22, // 2 x i64
FIRST_VECTOR_VALUETYPE = v8i8,
LAST_VECTOR_VALUETYPE = v2f64,
v2f32 = 23, // 2 x f32
v3f32 = 24, // 3 x f32
v4f32 = 25, // 4 x f32
v2f64 = 26, // 2 x f64
LAST_VALUETYPE = 27, // This always remains at the end of the list.
FIRST_VECTOR_VALUETYPE = v8i8,
LAST_VECTOR_VALUETYPE = v2f64,
// fAny - Any floating-point or vector floating-point value. This is used
// for intrinsics that have overloadings based on floating-point types.
// This is only for tblgen's consumption!
fAny = 253,
LAST_VALUETYPE = 27, // This always remains at the end of the list.
// iAny - An integer or vector integer value of any bit width. This is
// used for intrinsics that have overloadings based on integer bit widths.
// This is only for tblgen's consumption!
iAny = 254,
// fAny - Any floating-point or vector floating-point value. This is used
// for intrinsics that have overloadings based on floating-point types.
// This is only for tblgen's consumption!
fAny = 253,
// iPTR - An int value the size of the pointer of the current
// target. This should only be used internal to tblgen!
iPTR = 255
// iAny - An integer or vector integer value of any bit width. This is
// used for intrinsics that have overloadings based on integer bit widths.
// This is only for tblgen's consumption!
iAny = 254,
// iPTR - An int value the size of the pointer of the current
// target. This should only be used internal to tblgen!
iPTR = 255
};
/// MVT - This type holds low-level value types. Valid values include any of
/// the values in the SimpleValueType enum, or any value returned from one
/// of the MVT methods. Any value type equal to one of the SimpleValueType
/// enum values is a "simple" value type. All others are "extended".
///
/// Note that simple doesn't necessary mean legal for the target machine.
/// All legal value types must be simple, but often there are some simple
/// value types that are not legal.
///
/// @internal
/// Extended types are either vector types or arbitrary precision integers.
/// Arbitrary precision integers have iAny in the first SimpleTypeBits bits,
/// and the bit-width in the next PrecisionBits bits, offset by minus one.
/// Vector types are encoded by having the first SimpleTypeBits+PrecisionBits
/// bits encode the vector element type (which must be a scalar type, possibly
/// an arbitrary precision integer) and the remaining VectorBits upper bits
/// encode the vector length, offset by one.
///
/// 31--------------16-----------8-------------0
/// | Vector length | Precision | Simple type |
/// | | Vector element |
///
static const int SimpleTypeBits = 8;
static const int PrecisionBits = 8;
static const int VectorBits = 32 - SimpleTypeBits - PrecisionBits;
static const uint32_t SimpleTypeMask =
(~uint32_t(0) << (32 - SimpleTypeBits)) >> (32 - SimpleTypeBits);
static const uint32_t PrecisionMask =
((~uint32_t(0) << VectorBits) >> (32 - PrecisionBits)) << SimpleTypeBits;
static const uint32_t VectorMask =
(~uint32_t(0) >> (32 - VectorBits)) << (32 - VectorBits);
static const uint32_t ElementMask =
(~uint32_t(0) << VectorBits) >> VectorBits;
uint32_t V;
MVT() {}
MVT(SimpleValueType S) { V = S; }
inline bool operator== (const MVT VT) const { return V == VT.V; }
inline bool operator!= (const MVT VT) const { return V != VT.V; }
/// FIXME: The following comparison methods are bogus - they are only here
/// to ease the transition to a struct type.
inline bool operator< (const MVT VT) const { return V < VT.V; }
inline bool operator<= (const MVT VT) const { return V <= VT.V; }
inline bool operator> (const MVT VT) const { return V > VT.V; }
inline bool operator>= (const MVT VT) const { return V >= VT.V; }
/// getIntegerVT - Returns the MVT that represents an integer with the given
/// number of bits.
static inline MVT getIntegerVT(unsigned BitWidth) {
switch (BitWidth) {
default:
break;
case 1:
return i1;
case 8:
return i8;
case 16:
return i16;
case 32:
return i32;
case 64:
return i64;
case 128:
return i128;
}
MVT VT;
VT.V = iAny | (((BitWidth - 1) << SimpleTypeBits) & PrecisionMask);
assert(VT.getSizeInBits() == BitWidth && "Bad bit width!");
return VT;
}
/// getVectorVT - Returns the MVT that represents a vector NumElements in
/// length, where each element is of type VT.
static inline MVT getVectorVT(MVT VT, unsigned NumElements) {
switch (VT.V) {
default:
break;
case i8:
if (NumElements == 8) return v8i8;
if (NumElements == 16) return v16i8;
break;
case i16:
if (NumElements == 4) return v4i16;
if (NumElements == 8) return v8i16;
break;
case i32:
if (NumElements == 2) return v2i32;
if (NumElements == 3) return v3i32;
if (NumElements == 4) return v4i32;
break;
case i64:
if (NumElements == 1) return v1i64;
if (NumElements == 2) return v2i64;
break;
case f32:
if (NumElements == 2) return v2f32;
if (NumElements == 3) return v3f32;
if (NumElements == 4) return v4f32;
break;
case f64:
if (NumElements == 2) return v2f64;
break;
}
// Set the length with the top bit forced to zero (needed by the verifier).
MVT Result;
Result.V = VT.V | (((NumElements + 1) << (33 - VectorBits)) >> 1);
assert(Result.getVectorElementType() == VT &&
"Bad vector element type!");
assert(Result.getVectorNumElements() == NumElements &&
"Bad vector length!");
return Result;
}
/// getIntVectorWithNumElements - Return any integer vector type that has
/// the specified number of elements.
static inline MVT getIntVectorWithNumElements(unsigned NumElts) {
switch (NumElts) {
default: return getVectorVT(i8, NumElts);
case 1: return v1i64;
case 2: return v2i32;
case 3: return v3i32;
case 4: return v4i16;
case 8: return v8i8;
case 16: return v16i8;
}
}
/// isSimple - Test if the given MVT is simple (as opposed to being
/// extended).
inline bool isSimple() const {
return V <= SimpleTypeMask;
}
/// isExtended - Test if the given MVT is extended (as opposed to
/// being simple).
inline bool isExtended() const {
return !isSimple();
}
/// isFloatingPoint - Return true if this is a FP, or a vector FP type.
inline bool isFloatingPoint() const {
uint32_t SVT = V & SimpleTypeMask;
return (SVT >= f32 && SVT <= ppcf128) || (SVT >= v2f32 && SVT <= v2f64);
}
/// isInteger - Return true if this is an integer, or a vector integer type.
inline bool isInteger() const {
uint32_t SVT = V & SimpleTypeMask;
return (SVT >= FIRST_INTEGER_VALUETYPE && SVT <= LAST_INTEGER_VALUETYPE) ||
(SVT >= v8i8 && SVT <= v2i64) || (SVT == iAny && (V & PrecisionMask));
}
/// isVector - Return true if this is a vector value type.
inline bool isVector() const {
return (V >= FIRST_VECTOR_VALUETYPE && V <= LAST_VECTOR_VALUETYPE) ||
(V & VectorMask);
}
/// is64BitVector - Return true if this is a 64-bit vector type.
inline bool is64BitVector() const {
return (V==v8i8 || V==v4i16 || V==v2i32 || V==v1i64 || V==v2f32 ||
(isExtended() && isVector() && getSizeInBits()==64));
}
/// is128BitVector - Return true if this is a 128-bit vector type.
inline bool is128BitVector() const {
return (V==v16i8 || V==v8i16 || V==v4i32 || V==v2i64 ||
V==v4f32 || V==v2f64 ||
(isExtended() && isVector() && getSizeInBits()==128));
}
/// getSimpleVT - Return the SimpleValueType held in the specified
/// simple MVT.
inline SimpleValueType getSimpleVT() const {
assert(isSimple() && "Expected a SimpleValueType!");
return (SimpleValueType)V;
}
/// getVectorElementType - Given a vector type, return the type of
/// each element.
inline MVT getVectorElementType() const {
assert(isVector() && "Invalid vector type!");
switch (V) {
default: {
assert(isExtended() && "Unknown simple vector type!");
MVT VT;
VT.V = V & ElementMask;
return VT;
}
case v8i8 :
case v16i8: return i8;
case v4i16:
case v8i16: return i16;
case v2i32:
case v3i32:
case v4i32: return i32;
case v1i64:
case v2i64: return i64;
case v2f32:
case v3f32:
case v4f32: return f32;
case v2f64: return f64;
}
}
/// getVectorNumElements - Given a vector type, return the number of
/// elements it contains.
inline unsigned getVectorNumElements() const {
assert(isVector() && "Invalid vector type!");
switch (V) {
default:
assert(isExtended() && "Unknown simple vector type!");
return ((V & VectorMask) >> (32 - VectorBits)) - 1;
case v16i8: return 16;
case v8i8 :
case v8i16: return 8;
case v4i16:
case v4i32:
case v4f32: return 4;
case v3i32:
case v3f32: return 3;
case v2i32:
case v2i64:
case v2f32:
case v2f64: return 2;
case v1i64: return 1;
}
}
/// getSizeInBits - Return the size of the specified value type in bits.
inline unsigned getSizeInBits() const {
switch (V) {
default:
assert(isExtended() && "MVT has no known size!");
if (isVector())
return getVectorElementType().getSizeInBits()*getVectorNumElements();
if (isInteger())
return ((V & PrecisionMask) >> SimpleTypeBits) + 1;
assert(false && "Unknown value type!");
return 0;
case i1 : return 1;
case i8 : return 8;
case i16 : return 16;
case f32 :
case i32 : return 32;
case f64 :
case i64 :
case v8i8:
case v4i16:
case v2i32:
case v1i64:
case v2f32: return 64;
case f80 : return 80;
case v3i32:
case v3f32: return 96;
case f128:
case ppcf128:
case i128:
case v16i8:
case v8i16:
case v4i32:
case v2i64:
case v4f32:
case v2f64: return 128;
}
}
/// getStoreSizeInBits - Return the number of bits overwritten by a store
/// of the specified value type.
inline unsigned getStoreSizeInBits() const {
return (getSizeInBits() + 7)/8*8;
}
/// getRoundIntegerType - Rounds the bit-width of the given integer MVT up
/// to the nearest power of two (and at least to eight), and returns the
/// integer MVT with that number of bits.
inline MVT getRoundIntegerType() const {
assert(isInteger() && !isVector() && "Invalid integer type!");
unsigned BitWidth = getSizeInBits();
if (BitWidth <= 8)
return i8;
else
return getIntegerVT(1 << Log2_32_Ceil(BitWidth));
}
/// getIntegerVTBitMask - Return an integer with 1's every place there are
/// bits in the specified integer value type. FIXME: Should return an apint.
inline uint64_t getIntegerVTBitMask() const {
assert(isInteger() && !isVector() && "Only applies to int scalars!");
return ~uint64_t(0UL) >> (64-getSizeInBits());
}
/// getIntegerVTSignBit - Return an integer with a 1 in the position of the
/// sign bit for the specified integer value type. FIXME: Should return an
/// apint.
inline uint64_t getIntegerVTSignBit() const {
assert(isInteger() && !isVector() && "Only applies to int scalars!");
return uint64_t(1UL) << (getSizeInBits()-1);
}
/// getMVTString - This function returns value type as a string,
/// e.g. "i32".
std::string getMVTString() const;
/// getTypeForMVT - This method returns an LLVM type corresponding to the
/// specified MVT. For integer types, this returns an unsigned type. Note
/// that this will abort for types that cannot be represented.
const Type *getTypeForMVT() const;
/// getMVT - Return the value type corresponding to the specified type.
/// This returns all pointers as iPTR. If HandleUnknown is true, unknown
/// types are returned as Other, otherwise they are invalid.
static MVT getMVT(const Type *Ty, bool HandleUnknown = false);
};
/// MVT::ValueType - This type holds low-level value types. Valid values
/// include any of the values in the SimpleValueType enum, or any value
/// returned from a function in the MVT namespace that has a ValueType
/// return type. Any value type equal to one of the SimpleValueType enum
/// values is a "simple" value type. All other value types are "extended".
///
/// Note that simple doesn't necessary mean legal for the target machine.
/// All legal value types must be simple, but often there are some simple
/// value types that are not legal.
///
/// @internal
/// Extended types are either vector types or arbitrary precision integers.
/// Arbitrary precision integers have iAny in the first SimpleTypeBits bits,
/// and the bit-width in the next PrecisionBits bits, offset by minus one.
/// Vector types are encoded by having the first SimpleTypeBits+PrecisionBits
/// bits encode the vector element type (which must be a scalar type, possibly
/// an arbitrary precision integer) and the remaining VectorBits upper bits
/// encode the vector length, offset by one.
///
/// 31--------------16-----------8-------------0
/// | Vector length | Precision | Simple type |
/// | | Vector element |
///
/// Note that the verifier currently requires the top bit to be zero.
typedef uint32_t ValueType;
static const int SimpleTypeBits = 8;
static const int PrecisionBits = 8;
static const int VectorBits = 32 - SimpleTypeBits - PrecisionBits;
static const uint32_t SimpleTypeMask =
(~uint32_t(0) << (32 - SimpleTypeBits)) >> (32 - SimpleTypeBits);
static const uint32_t PrecisionMask =
((~uint32_t(0) << VectorBits) >> (32 - PrecisionBits)) << SimpleTypeBits;
static const uint32_t VectorMask =
(~uint32_t(0) >> (32 - VectorBits)) << (32 - VectorBits);
static const uint32_t ElementMask =
(~uint32_t(0) << VectorBits) >> VectorBits;
/// MVT::isExtendedVT - Test if the given ValueType is extended
/// (as opposed to being simple).
static inline bool isExtendedVT(ValueType VT) {
return VT > SimpleTypeMask;
}
/// MVT::isInteger - Return true if this is an integer, or a vector integer
/// type.
static inline bool isInteger(ValueType VT) {
ValueType SVT = VT & SimpleTypeMask;
return (SVT >= FIRST_INTEGER_VALUETYPE && SVT <= LAST_INTEGER_VALUETYPE) ||
(SVT >= v8i8 && SVT <= v2i64) || (SVT == iAny && (VT & PrecisionMask));
}
/// MVT::isFloatingPoint - Return true if this is an FP, or a vector FP type.
static inline bool isFloatingPoint(ValueType VT) {
ValueType SVT = VT & SimpleTypeMask;
return (SVT >= f32 && SVT <= ppcf128) || (SVT >= v2f32 && SVT <= v2f64);
}
/// MVT::isVector - Return true if this is a vector value type.
static inline bool isVector(ValueType VT) {
return (VT >= FIRST_VECTOR_VALUETYPE && VT <= LAST_VECTOR_VALUETYPE) ||
(VT & VectorMask);
}
/// MVT::getVectorElementType - Given a vector type, return the type of
/// each element.
static inline ValueType getVectorElementType(ValueType VT) {
assert(isVector(VT) && "Invalid vector type!");
switch (VT) {
default:
assert(isExtendedVT(VT) && "Unknown simple vector type!");
return VT & ElementMask;
case v8i8 :
case v16i8: return i8;
case v4i16:
case v8i16: return i16;
case v2i32:
case v3i32:
case v4i32: return i32;
case v1i64:
case v2i64: return i64;
case v2f32:
case v3f32:
case v4f32: return f32;
case v2f64: return f64;
}
}
/// MVT::getVectorNumElements - Given a vector type, return the
/// number of elements it contains.
static inline unsigned getVectorNumElements(ValueType VT) {
assert(isVector(VT) && "Invalid vector type!");
switch (VT) {
default:
assert(isExtendedVT(VT) && "Unknown simple vector type!");
return ((VT & VectorMask) >> (32 - VectorBits)) - 1;
case v16i8: return 16;
case v8i8 :
case v8i16: return 8;
case v4i16:
case v4i32:
case v4f32: return 4;
case v3i32:
case v3f32: return 3;
case v2i32:
case v2i64:
case v2f32:
case v2f64: return 2;
case v1i64: return 1;
}
}
/// MVT::getSizeInBits - Return the size of the specified value type
/// in bits.
///
static inline unsigned getSizeInBits(ValueType VT) {
switch (VT) {
default:
assert(isExtendedVT(VT) && "ValueType has no known size!");
if (isVector(VT))
return getSizeInBits(getVectorElementType(VT)) *
getVectorNumElements(VT);
if (isInteger(VT))
return ((VT & PrecisionMask) >> SimpleTypeBits) + 1;
assert(0 && "Unknown value type!");
case MVT::i1 : return 1;
case MVT::i8 : return 8;
case MVT::i16 : return 16;
case MVT::f32 :
case MVT::i32 : return 32;
case MVT::f64 :
case MVT::i64 :
case MVT::v8i8:
case MVT::v4i16:
case MVT::v2i32:
case MVT::v1i64:
case MVT::v2f32: return 64;
case MVT::f80 : return 80;
case MVT::v3i32:
case MVT::v3f32: return 96;
case MVT::f128:
case MVT::ppcf128:
case MVT::i128:
case MVT::v16i8:
case MVT::v8i16:
case MVT::v4i32:
case MVT::v2i64:
case MVT::v4f32:
case MVT::v2f64: return 128;
}
}
/// MVT::getStoreSizeInBits - Return the number of bits overwritten by a
/// store of the specified value type.
///
static inline unsigned getStoreSizeInBits(ValueType VT) {
return (getSizeInBits(VT) + 7)/8*8;
}
/// MVT::is64BitVector - Return true if this is a 64-bit vector type.
static inline bool is64BitVector(ValueType VT) {
return (VT==v8i8 || VT==v4i16 || VT==v2i32 || VT==v1i64 || VT==v2f32 ||
(isExtendedVT(VT) && isVector(VT) && getSizeInBits(VT)==64));
}
/// MVT::is128BitVector - Return true if this is a 128-bit vector type.
static inline bool is128BitVector(ValueType VT) {
return (VT==v16i8 || VT==v8i16 || VT==v4i32 || VT==v2i64 ||
VT==v4f32 || VT==v2f64 ||
(isExtendedVT(VT) && isVector(VT) && getSizeInBits(VT)==128));
}
/// MVT::getIntegerType - Returns the ValueType that represents an integer
/// with the given number of bits.
///
static inline ValueType getIntegerType(unsigned BitWidth) {
switch (BitWidth) {
default:
break;
case 1:
return MVT::i1;
case 8:
return MVT::i8;
case 16:
return MVT::i16;
case 32:
return MVT::i32;
case 64:
return MVT::i64;
case 128:
return MVT::i128;
}
ValueType Result = iAny |
(((BitWidth - 1) << SimpleTypeBits) & PrecisionMask);
assert(getSizeInBits(Result) == BitWidth && "Bad bit width!");
return Result;
}
/// MVT::RoundIntegerType - Rounds the bit-width of the given integer
/// ValueType up to the nearest power of two (and at least to eight),
/// and returns the integer ValueType with that number of bits.
///
static inline ValueType RoundIntegerType(ValueType VT) {
assert(isInteger(VT) && !isVector(VT) && "Invalid integer type!");
unsigned BitWidth = getSizeInBits(VT);
if (BitWidth <= 8)
return MVT::i8;
else
return getIntegerType(1 << Log2_32_Ceil(BitWidth));
}
/// MVT::getVectorType - Returns the ValueType that represents a vector
/// NumElements in length, where each element is of type VT.
///
static inline ValueType getVectorType(ValueType VT, unsigned NumElements) {
switch (VT) {
default:
break;
case MVT::i8:
if (NumElements == 8) return MVT::v8i8;
if (NumElements == 16) return MVT::v16i8;
break;
case MVT::i16:
if (NumElements == 4) return MVT::v4i16;
if (NumElements == 8) return MVT::v8i16;
break;
case MVT::i32:
if (NumElements == 2) return MVT::v2i32;
if (NumElements == 3) return MVT::v3i32;
if (NumElements == 4) return MVT::v4i32;
break;
case MVT::i64:
if (NumElements == 1) return MVT::v1i64;
if (NumElements == 2) return MVT::v2i64;
break;
case MVT::f32:
if (NumElements == 2) return MVT::v2f32;
if (NumElements == 3) return MVT::v3f32;
if (NumElements == 4) return MVT::v4f32;
break;
case MVT::f64:
if (NumElements == 2) return MVT::v2f64;
break;
}
// Set the length with the top bit forced to zero (needed by the verifier).
ValueType Result = VT | (((NumElements + 1) << (33 - VectorBits)) >> 1);
assert(getVectorElementType(Result) == VT &&
"Bad vector element type!");
assert(getVectorNumElements(Result) == NumElements &&
"Bad vector length!");
return Result;
}
/// MVT::getIntVectorWithNumElements - Return any integer vector type that has
/// the specified number of elements.
static inline ValueType getIntVectorWithNumElements(unsigned NumElts) {
switch (NumElts) {
default: return getVectorType(i8, NumElts);
case 1: return v1i64;
case 2: return v2i32;
case 3: return v3i32;
case 4: return v4i16;
case 8: return v8i8;
case 16: return v16i8;
}
}
/// MVT::getIntVTBitMask - Return an integer with 1's every place there are
/// bits in the specified integer value type.
static inline uint64_t getIntVTBitMask(ValueType VT) {
assert(isInteger(VT) && !isVector(VT) && "Only applies to int scalars!");
return ~uint64_t(0UL) >> (64-getSizeInBits(VT));
}
/// MVT::getIntVTSignBit - Return an integer with a 1 in the position of the
/// sign bit for the specified integer value type.
static inline uint64_t getIntVTSignBit(ValueType VT) {
assert(isInteger(VT) && !isVector(VT) && "Only applies to int scalars!");
return uint64_t(1UL) << (getSizeInBits(VT)-1);
}
/// MVT::getValueTypeString - This function returns value type as a string,
/// e.g. "i32".
std::string getValueTypeString(ValueType VT);
/// MVT::getTypeForValueType - This method returns an LLVM type corresponding
/// to the specified ValueType. For integer types, this returns an unsigned
/// type. Note that this will abort for types that cannot be represented.
const Type *getTypeForValueType(ValueType VT);
/// MVT::getValueType - Return the value type corresponding to the specified
/// type. This returns all pointers as MVT::iPTR. If HandleUnknown is true,
/// unknown types are returned as Other, otherwise they are invalid.
ValueType getValueType(const Type *Ty, bool HandleUnknown = false);
}
} // End llvm namespace
#endif

308
include/llvm/Target/TargetLowering.h
View File

@ -90,8 +90,8 @@ public:
bool isBigEndian() const { return !IsLittleEndian; }
bool isLittleEndian() const { return IsLittleEndian; }
MVT::ValueType getPointerTy() const { return PointerTy; }
MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; }
MVT getPointerTy() const { return PointerTy; }
MVT getShiftAmountTy() const { return ShiftAmountTy; }
OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
/// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
@ -112,7 +112,7 @@ public:
/// getSetCCResultType - Return the ValueType of the result of setcc
/// operations.
virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
virtual MVT getSetCCResultType(const SDOperand &) const;
/// getSetCCResultContents - For targets without boolean registers, this flag
/// returns information about the contents of the high-bits in the setcc
@ -126,9 +126,9 @@ public:
/// getRegClassFor - Return the register class that should be used for the
/// specified value type. This may only be called on legal types.
TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const {
assert(VT < array_lengthof(RegClassForVT));
TargetRegisterClass *RC = RegClassForVT[VT];
TargetRegisterClass *getRegClassFor(MVT VT) const {
assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT()];
assert(RC && "This value type is not natively supported!");
return RC;
}
@ -136,9 +136,10 @@ public:
/// isTypeLegal - Return true if the target has native support for the
/// specified value type. This means that it has a register that directly
/// holds it without promotions or expansions.
bool isTypeLegal(MVT::ValueType VT) const {
assert(MVT::isExtendedVT(VT) || VT < array_lengthof(RegClassForVT));
return !MVT::isExtendedVT(VT) && RegClassForVT[VT] != 0;
bool isTypeLegal(MVT VT) const {
assert(!VT.isSimple() ||
(unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
return VT.isSimple() && RegClassForVT[VT.getSimpleVT()] != 0;
}
class ValueTypeActionImpl {
@ -155,20 +156,23 @@ public:
ValueTypeActions[1] = RHS.ValueTypeActions[1];
}
LegalizeAction getTypeAction(MVT::ValueType VT) const {
if (MVT::isExtendedVT(VT)) {
if (MVT::isVector(VT)) return Expand;
if (MVT::isInteger(VT))
LegalizeAction getTypeAction(MVT VT) const {
if (VT.isExtended()) {
if (VT.isVector()) return Expand;
if (VT.isInteger())
// First promote to a power-of-two size, then expand if necessary.
return VT == MVT::RoundIntegerType(VT) ? Expand : Promote;
return VT == VT.getRoundIntegerType() ? Expand : Promote;
assert(0 && "Unsupported extended type!");
return Legal;
}
assert(VT<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3);
unsigned I = VT.getSimpleVT();
assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3);
}
void setTypeAction(MVT::ValueType VT, LegalizeAction Action) {
assert(VT<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31);
void setTypeAction(MVT VT, LegalizeAction Action) {
unsigned I = VT.getSimpleVT();
assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
ValueTypeActions[I>>4] |= Action << ((I*2) & 31);
}
};
@ -180,7 +184,7 @@ public:
/// it is already legal (return 'Legal') or we need to promote it to a larger
/// type (return 'Promote'), or we need to expand it into multiple registers
/// of smaller integer type (return 'Expand'). 'Custom' is not an option.
LegalizeAction getTypeAction(MVT::ValueType VT) const {
LegalizeAction getTypeAction(MVT VT) const {
return ValueTypeActions.getTypeAction(VT);
}
@ -190,37 +194,37 @@ public:
/// than the largest integer register, this contains one step in the expansion
/// to get to the smaller register. For illegal floating point types, this
/// returns the integer type to transform to.
MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const {
if (!MVT::isExtendedVT(VT)) {
assert(VT < array_lengthof(TransformToType));
MVT::ValueType NVT = TransformToType[VT];
MVT getTypeToTransformTo(MVT VT) const {
if (VT.isSimple()) {
assert((unsigned)VT.getSimpleVT() < array_lengthof(TransformToType));
MVT NVT = TransformToType[VT.getSimpleVT()];
assert(getTypeAction(NVT) != Promote &&
"Promote may not follow Expand or Promote");
return NVT;
}
if (MVT::isVector(VT))
return MVT::getVectorType(MVT::getVectorElementType(VT),
MVT::getVectorNumElements(VT) / 2);
if (MVT::isInteger(VT)) {
MVT::ValueType NVT = MVT::RoundIntegerType(VT);
if (VT.isVector())
return MVT::getVectorVT(VT.getVectorElementType(),
VT.getVectorNumElements() / 2);
if (VT.isInteger()) {
MVT NVT = VT.getRoundIntegerType();
if (NVT == VT)
// Size is a power of two - expand to half the size.
return MVT::getIntegerType(MVT::getSizeInBits(VT) / 2);
return MVT::getIntegerVT(VT.getSizeInBits() / 2);
else
// Promote to a power of two size, avoiding multi-step promotion.
return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
}
assert(0 && "Unsupported extended type!");
return MVT::ValueType(); // Not reached
return MVT(); // Not reached
}
/// getTypeToExpandTo - For types supported by the target, this is an
/// identity function. For types that must be expanded (i.e. integer types
/// that are larger than the largest integer register or illegal floating
/// point types), this returns the largest legal type it will be expanded to.
MVT::ValueType getTypeToExpandTo(MVT::ValueType VT) const {
assert(!MVT::isVector(VT));
MVT getTypeToExpandTo(MVT VT) const {
assert(!VT.isVector());
while (true) {
switch (getTypeAction(VT)) {
case Legal:
@ -245,10 +249,10 @@ public:
/// register. It also returns the VT and quantity of the intermediate values
/// before they are promoted/expanded.
///
unsigned getVectorTypeBreakdown(MVT::ValueType VT,
MVT::ValueType &IntermediateVT,
unsigned getVectorTypeBreakdown(MVT VT,
MVT &IntermediateVT,
unsigned &NumIntermediates,
MVT::ValueType &RegisterVT) const;
MVT &RegisterVT) const;
typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator;
legal_fpimm_iterator legal_fpimm_begin() const {
@ -262,7 +266,7 @@ public:
/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
/// are assumed to be legal.
virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
virtual bool isShuffleMaskLegal(SDOperand Mask, MVT VT) const {
return true;
}
@ -271,7 +275,7 @@ public:
/// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
/// pool entry.
virtual bool isVectorClearMaskLegal(const std::vector<SDOperand> &BVOps,
MVT::ValueType EVT,
MVT EVT,
SelectionDAG &DAG) const {
return false;
}
@ -280,16 +284,17 @@ public:
/// it is legal, needs to be promoted to a larger size, needs to be
/// expanded to some other code sequence, or the target has a custom expander
/// for it.
LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const {
if (MVT::isExtendedVT(VT)) return Expand;
LegalizeAction getOperationAction(unsigned Op, MVT VT) const {
if (VT.isExtended()) return Expand;
assert(Op < array_lengthof(OpActions) &&
VT < sizeof(OpActions[0])*4 && "Table isn't big enough!");
return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3);
(unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 &&
"Table isn't big enough!");
return (LegalizeAction)((OpActions[Op] >> (2*VT.getSimpleVT())) & 3);
}
/// isOperationLegal - Return true if the specified operation is legal on this
/// target.
bool isOperationLegal(unsigned Op, MVT::ValueType VT) const {
bool isOperationLegal(unsigned Op, MVT VT) const {
return getOperationAction(Op, VT) == Legal ||
getOperationAction(Op, VT) == Custom;
}
@ -298,16 +303,17 @@ public:
/// either it is legal, needs to be promoted to a larger size, needs to be
/// expanded to some other code sequence, or the target has a custom expander
/// for it.
LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const {
LegalizeAction getLoadXAction(unsigned LType, MVT VT) const {
assert(LType < array_lengthof(LoadXActions) &&
VT < sizeof(LoadXActions[0])*4 && "Table isn't big enough!");
return (LegalizeAction)((LoadXActions[LType] >> (2*VT)) & 3);
(unsigned)VT.getSimpleVT() < sizeof(LoadXActions[0])*4 &&
"Table isn't big enough!");
return (LegalizeAction)((LoadXActions[LType] >> (2*VT.getSimpleVT())) & 3);
}
/// isLoadXLegal - Return true if the specified load with extension is legal
/// on this target.
bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const {
return !MVT::isExtendedVT(VT) &&
bool isLoadXLegal(unsigned LType, MVT VT) const {
return VT.isSimple() &&
(getLoadXAction(LType, VT) == Legal ||
getLoadXAction(LType, VT) == Custom);
}
@ -316,17 +322,19 @@ public:
/// treated: either it is legal, needs to be promoted to a larger size, needs
/// to be expanded to some other code sequence, or the target has a custom
/// expander for it.
LegalizeAction getTruncStoreAction(MVT::ValueType ValVT,
MVT::ValueType MemVT) const {
assert(ValVT < array_lengthof(TruncStoreActions) &&
MemVT < sizeof(TruncStoreActions[0])*4 && "Table isn't big enough!");
return (LegalizeAction)((TruncStoreActions[ValVT] >> (2*MemVT)) & 3);
LegalizeAction getTruncStoreAction(MVT ValVT,
MVT MemVT) const {
assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
(unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
"Table isn't big enough!");
return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT()] >>
(2*MemVT.getSimpleVT())) & 3);
}
/// isTruncStoreLegal - Return true if the specified store with truncation is
/// legal on this target.
bool isTruncStoreLegal(MVT::ValueType ValVT, MVT::ValueType MemVT) const {
return !MVT::isExtendedVT(MemVT) &&
bool isTruncStoreLegal(MVT ValVT, MVT MemVT) const {
return MemVT.isSimple() &&
(getTruncStoreAction(ValVT, MemVT) == Legal ||
getTruncStoreAction(ValVT, MemVT) == Custom);
}
@ -336,16 +344,17 @@ public:
/// expanded to some other code sequence, or the target has a custom expander
/// for it.
LegalizeAction
getIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT) const {
getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
assert(IdxMode < array_lengthof(IndexedModeActions[0]) &&
VT < sizeof(IndexedModeActions[0][0])*4 &&
(unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0][0])*4 &&
"Table isn't big enough!");
return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> (2*VT)) & 3);
return (LegalizeAction)((IndexedModeActions[0][IdxMode] >>
(2*VT.getSimpleVT())) & 3);
}
/// isIndexedLoadLegal - Return true if the specified indexed load is legal
/// on this target.
bool isIndexedLoadLegal(unsigned IdxMode, MVT::ValueType VT) const {
bool isIndexedLoadLegal(unsigned IdxMode, MVT VT) const {
return getIndexedLoadAction(IdxMode, VT) == Legal ||
getIndexedLoadAction(IdxMode, VT) == Custom;
}
@ -355,16 +364,17 @@ public:
/// expanded to some other code sequence, or the target has a custom expander
/// for it.
LegalizeAction
getIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT) const {
getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
assert(IdxMode < array_lengthof(IndexedModeActions[1]) &&
VT < sizeof(IndexedModeActions[1][0])*4 &&
(unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 &&
"Table isn't big enough!");
return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> (2*VT)) & 3);
return (LegalizeAction)((IndexedModeActions[1][IdxMode] >>
(2*VT.getSimpleVT())) & 3);
}
/// isIndexedStoreLegal - Return true if the specified indexed load is legal
/// on this target.
bool isIndexedStoreLegal(unsigned IdxMode, MVT::ValueType VT) const {
bool isIndexedStoreLegal(unsigned IdxMode, MVT VT) const {
return getIndexedStoreAction(IdxMode, VT) == Legal ||
getIndexedStoreAction(IdxMode, VT) == Custom;
}
@ -374,50 +384,52 @@ public:
/// expanded to some other code sequence, or the target has a custom expander
/// for it.
LegalizeAction
getConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT) const {
assert(FromVT < array_lengthof(ConvertActions) &&
ToVT < sizeof(ConvertActions[0])*4 && "Table isn't big enough!");
return (LegalizeAction)((ConvertActions[FromVT] >> (2*ToVT)) & 3);
getConvertAction(MVT FromVT, MVT ToVT) const {
assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
(unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
"Table isn't big enough!");
return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT()] >>
(2*ToVT.getSimpleVT())) & 3);
}
/// isConvertLegal - Return true if the specified conversion is legal
/// on this target.
bool isConvertLegal(MVT::ValueType FromVT, MVT::ValueType ToVT) const {
bool isConvertLegal(MVT FromVT, MVT ToVT) const {
return getConvertAction(FromVT, ToVT) == Legal ||
getConvertAction(FromVT, ToVT) == Custom;
}
/// getTypeToPromoteTo - If the action for this operation is to promote, this
/// method returns the ValueType to promote to.
MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const {
MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
assert(getOperationAction(Op, VT) == Promote &&
"This operation isn't promoted!");
// See if this has an explicit type specified.
std::map<std::pair<unsigned, MVT::ValueType>,
MVT::ValueType>::const_iterator PTTI =
std::map<std::pair<unsigned, MVT>,
MVT>::const_iterator PTTI =
PromoteToType.find(std::make_pair(Op, VT));
if (PTTI != PromoteToType.end()) return PTTI->second;
assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) &&
assert((VT.isInteger() || VT.isFloatingPoint()) &&
"Cannot autopromote this type, add it with AddPromotedToType.");
MVT::ValueType NVT = VT;
MVT NVT = VT;
do {
NVT = (MVT::ValueType)(NVT+1);
assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid &&
NVT = (MVT::SimpleValueType)(NVT.getSimpleVT()+1);
assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
"Didn't find type to promote to!");
} while (!isTypeLegal(NVT) ||
getOperationAction(Op, NVT) == Promote);
return NVT;
}
/// getValueType - Return the MVT::ValueType corresponding to this LLVM type.
/// getValueType - Return the MVT corresponding to this LLVM type.
/// This is fixed by the LLVM operations except for the pointer size. If
/// AllowUnknown is true, this will return MVT::Other for types with no MVT
/// counterpart (e.g. structs), otherwise it will assert.
MVT::ValueType getValueType(const Type *Ty, bool AllowUnknown = false) const {
MVT::ValueType VT = MVT::getValueType(Ty, AllowUnknown);
MVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
MVT VT = MVT::getMVT(Ty, AllowUnknown);
return VT == MVT::iPTR ? PointerTy : VT;
}
@ -428,22 +440,22 @@ public:
/// getRegisterType - Return the type of registers that this ValueType will
/// eventually require.
MVT::ValueType getRegisterType(MVT::ValueType VT) const {
if (!MVT::isExtendedVT(VT)) {
assert(VT < array_lengthof(RegisterTypeForVT));
return RegisterTypeForVT[VT];
MVT getRegisterType(MVT VT) const {
if (VT.isSimple()) {
assert((unsigned)VT.getSimpleVT() < array_lengthof(RegisterTypeForVT));
return RegisterTypeForVT[VT.getSimpleVT()];
}
if (MVT::isVector(VT)) {
MVT::ValueType VT1, RegisterVT;
if (VT.isVector()) {
MVT VT1, RegisterVT;
unsigned NumIntermediates;
(void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT);
return RegisterVT;
}
if (MVT::isInteger(VT)) {
if (VT.isInteger()) {
return getRegisterType(getTypeToTransformTo(VT));
}
assert(0 && "Unsupported extended type!");
return MVT::ValueType(); // Not reached
return MVT(); // Not reached
}
/// getNumRegisters - Return the number of registers that this ValueType will
@ -452,19 +464,19 @@ public:
/// into pieces. For types like i140, which are first promoted then expanded,
/// it is the number of registers needed to hold all the bits of the original
/// type. For an i140 on a 32 bit machine this means 5 registers.
unsigned getNumRegisters(MVT::ValueType VT) const {
if (!MVT::isExtendedVT(VT)) {
assert(VT < array_lengthof(NumRegistersForVT));
return NumRegistersForVT[VT];
unsigned getNumRegisters(MVT VT) const {
if (VT.isSimple()) {
assert((unsigned)VT.getSimpleVT() < array_lengthof(NumRegistersForVT));
return NumRegistersForVT[VT.getSimpleVT()];
}
if (MVT::isVector(VT)) {
MVT::ValueType VT1, VT2;
if (VT.isVector()) {
MVT VT1, VT2;
unsigned NumIntermediates;
return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2);
}
if (MVT::isInteger(VT)) {
unsigned BitWidth = MVT::getSizeInBits(VT);
unsigned RegWidth = MVT::getSizeInBits(getRegisterType(VT));
if (VT.isInteger()) {
unsigned BitWidth = VT.getSizeInBits();
unsigned RegWidth = getRegisterType(VT).getSizeInBits();
return (BitWidth + RegWidth - 1) / RegWidth;
}
assert(0 && "Unsupported extended type!");
@ -474,7 +486,7 @@ public:
/// ShouldShrinkFPConstant - If true, then instruction selection should
/// seek to shrink the FP constant of the specified type to a smaller type
/// in order to save space and / or reduce runtime.
virtual bool ShouldShrinkFPConstant(MVT::ValueType VT) const { return true; }
virtual bool ShouldShrinkFPConstant(MVT VT) const { return true; }
/// hasTargetDAGCombine - If true, the target has custom DAG combine
/// transformations that it can perform for the specified node.
@ -515,8 +527,8 @@ public:
/// and store operations as a result of memset, memcpy, and memmove lowering.
/// It returns MVT::iAny if SelectionDAG should be responsible for
/// determining it.
virtual MVT::ValueType getOptimalMemOpType(uint64_t Size, unsigned Align,
bool isSrcConst, bool isSrcStr) const {
virtual MVT getOptimalMemOpType(uint64_t Size, unsigned Align,
bool isSrcConst, bool isSrcStr) const {
return MVT::iAny;
}
@ -687,7 +699,7 @@ public:
/// SimplifySetCC - Try to simplify a setcc built with the specified operands
/// and cc. If it is unable to simplify it, return a null SDOperand.
SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
SDOperand SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1,
ISD::CondCode Cond, bool foldBooleans,
DAGCombinerInfo &DCI) const;
@ -729,7 +741,7 @@ protected:
/// setShiftAmountType - Describe the type that should be used for shift
/// amounts. This type defaults to the pointer type.
void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; }
void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
/// setSetCCResultContents - Specify how the target extends the result of a
/// setcc operation in a register.
@ -798,10 +810,10 @@ protected:
/// addRegisterClass - Add the specified register class as an available
/// regclass for the specified value type. This indicates the selector can
/// handle values of that class natively.
void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) {
assert(VT < array_lengthof(RegClassForVT));
void addRegisterClass(MVT VT, TargetRegisterClass *RC) {
assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
AvailableRegClasses.push_back(std::make_pair(VT, RC));
RegClassForVT[VT] = RC;
RegClassForVT[VT.getSimpleVT()] = RC;
}
/// computeRegisterProperties - Once all of the register classes are added,
@ -810,77 +822,82 @@ protected:
/// setOperationAction - Indicate that the specified operation does not work
/// with the specified type and indicate what to do about it.
void setOperationAction(unsigned Op, MVT::ValueType VT,
void setOperationAction(unsigned Op, MVT VT,
LegalizeAction Action) {
assert(VT < sizeof(OpActions[0])*4 && Op < array_lengthof(OpActions) &&
"Table isn't big enough!");
OpActions[Op] &= ~(uint64_t(3UL) << VT*2);
OpActions[Op] |= (uint64_t)Action << VT*2;
assert((unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 &&
Op < array_lengthof(OpActions) && "Table isn't big enough!");
OpActions[Op] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
OpActions[Op] |= (uint64_t)Action << VT.getSimpleVT()*2;
}
/// setLoadXAction - Indicate that the specified load with extension does not
/// work with the with specified type and indicate what to do about it.
void setLoadXAction(unsigned ExtType, MVT::ValueType VT,
void setLoadXAction(unsigned ExtType, MVT VT,
LegalizeAction Action) {
assert(VT < sizeof(LoadXActions[0])*4 &&
assert((unsigned)VT.getSimpleVT() < sizeof(LoadXActions[0])*4 &&
ExtType < array_lengthof(LoadXActions) &&
"Table isn't big enough!");
LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2);
LoadXActions[ExtType] |= (uint64_t)Action << VT*2;
LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
LoadXActions[ExtType] |= (uint64_t)Action << VT.getSimpleVT()*2;
}
/// setTruncStoreAction - Indicate that the specified truncating store does
/// not work with the with specified type and indicate what to do about it.
void setTruncStoreAction(MVT::ValueType ValVT, MVT::ValueType MemVT,
void setTruncStoreAction(MVT ValVT, MVT MemVT,
LegalizeAction Action) {
assert(ValVT < array_lengthof(TruncStoreActions) &&
MemVT < sizeof(TruncStoreActions[0])*4 && "Table isn't big enough!");
TruncStoreActions[ValVT] &= ~(uint64_t(3UL) << MemVT*2);
TruncStoreActions[ValVT] |= (uint64_t)Action << MemVT*2;
assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
(unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
"Table isn't big enough!");
TruncStoreActions[ValVT.getSimpleVT()] &= ~(uint64_t(3UL) <<
MemVT.getSimpleVT()*2);
TruncStoreActions[ValVT.getSimpleVT()] |= (uint64_t)Action <<
MemVT.getSimpleVT()*2;
}
/// setIndexedLoadAction - Indicate that the specified indexed load does or
/// does not work with the with specified type and indicate what to do abort
/// it. NOTE: All indexed mode loads are initialized to Expand in
/// TargetLowering.cpp
void setIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT,
void setIndexedLoadAction(unsigned IdxMode, MVT VT,
LegalizeAction Action) {
assert(VT < sizeof(IndexedModeActions[0])*4 && IdxMode <
array_lengthof(IndexedModeActions[0]) &&
assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0])*4 &&
IdxMode < array_lengthof(IndexedModeActions[0]) &&
"Table isn't big enough!");
IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT*2);
IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT*2;
IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2;
}
/// setIndexedStoreAction - Indicate that the specified indexed store does or
/// does not work with the with specified type and indicate what to do about
/// it. NOTE: All indexed mode stores are initialized to Expand in
/// TargetLowering.cpp
void setIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT,
void setIndexedStoreAction(unsigned IdxMode, MVT VT,
LegalizeAction Action) {
assert(VT < sizeof(IndexedModeActions[1][0])*4 &&
assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 &&
IdxMode < array_lengthof(IndexedModeActions[1]) &&
"Table isn't big enough!");
IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT*2);
IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT*2;
IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2;
}
/// setConvertAction - Indicate that the specified conversion does or does
/// not work with the with specified type and indicate what to do about it.
void setConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT,
void setConvertAction(MVT FromVT, MVT ToVT,
LegalizeAction Action) {
assert(FromVT < array_lengthof(ConvertActions) &&
ToVT < sizeof(ConvertActions[0])*4 && "Table isn't big enough!");
ConvertActions[FromVT] &= ~(uint64_t(3UL) << ToVT*2);
ConvertActions[FromVT] |= (uint64_t)Action << ToVT*2;
assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
(unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
"Table isn't big enough!");
ConvertActions[FromVT.getSimpleVT()] &= ~(uint64_t(3UL) <<
ToVT.getSimpleVT()*2);
ConvertActions[FromVT.getSimpleVT()] |= (uint64_t)Action <<
ToVT.getSimpleVT()*2;
}
/// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
/// promotion code defaults to trying a larger integer/fp until it can find
/// one that works. If that default is insufficient, this method can be used
/// by the target to override the default.
void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT,
MVT::ValueType DestVT) {
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT;
}
@ -1121,7 +1138,7 @@ public:
Value *CallOperandVal;
/// ConstraintVT - The ValueType for the operand value.
MVT::ValueType ConstraintVT;
MVT ConstraintVT;
AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
: InlineAsm::ConstraintInfo(info),
@ -1148,7 +1165,7 @@ public:
/// This should only be used for C_RegisterClass constraints.
virtual std::vector<unsigned>
getRegClassForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
MVT VT) const;
/// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
/// {edx}), return the register number and the register class for the
@ -1162,13 +1179,13 @@ public:
/// this returns a register number of 0 and a null register class pointer..
virtual std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
MVT VT) const;
/// LowerXConstraint - try to replace an X constraint, which matches anything,
/// with another that has more specific requirements based on the type of the
/// corresponding operand. This returns null if there is no replacement to
/// make.
virtual const char *LowerXConstraint(MVT::ValueType ConstraintVT) const;
virtual const char *LowerXConstraint(MVT ConstraintVT) const;
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops.
@ -1220,7 +1237,7 @@ public:
return false;
}
virtual bool isTruncateFree(MVT::ValueType VT1, MVT::ValueType VT2) const {
virtual bool isTruncateFree(MVT VT1, MVT VT2) const {
return false;
}
@ -1271,7 +1288,7 @@ private:
/// PointerTy - The type to use for pointers, usually i32 or i64.
///
MVT::ValueType PointerTy;
MVT PointerTy;
/// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
///
@ -1279,7 +1296,7 @@ private:
/// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
/// PointerTy is.
MVT::ValueType ShiftAmountTy;
MVT ShiftAmountTy;
OutOfRangeShiftAmount ShiftAmtHandling;
@ -1352,14 +1369,14 @@ private:
/// each ValueType the target supports natively.
TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
MVT::ValueType RegisterTypeForVT[MVT::LAST_VALUETYPE];
MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
/// TransformToType - For any value types we are promoting or expanding, this
/// contains the value type that we are changing to. For Expanded types, this
/// contains one step of the expand (e.g. i64 -> i32), even if there are
/// multiple steps required (e.g. i64 -> i16). For types natively supported
/// by the system, this holds the same type (e.g. i32 -> i32).
MVT::ValueType TransformToType[MVT::LAST_VALUETYPE];
MVT TransformToType[MVT::LAST_VALUETYPE];
// Defines the capacity of the TargetLowering::OpActions table
static const int OpActionsCapacity = 176;
@ -1396,8 +1413,7 @@ private:
std::vector<APFloat> LegalFPImmediates;
std::vector<std::pair<MVT::ValueType,
TargetRegisterClass*> > AvailableRegClasses;
std::vector<std::pair<MVT, TargetRegisterClass*> > AvailableRegClasses;
/// TargetDAGCombineArray - Targets can specify ISD nodes that they would
/// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
@ -1411,7 +1427,7 @@ private:
///
/// Targets add entries to this map with AddPromotedToType(..), clients access
/// this with getTypeToPromoteTo(..).
std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType;
std::map<std::pair<unsigned, MVT>, MVT> PromoteToType;
/// LibcallRoutineNames - Stores the name each libcall.
///

8
include/llvm/Target/TargetRegisterInfo.h
View File

@ -61,7 +61,7 @@ public:
typedef const unsigned* iterator;
typedef const unsigned* const_iterator;
typedef const MVT::ValueType* vt_iterator;
typedef const MVT* vt_iterator;
typedef const TargetRegisterClass* const * sc_iterator;
private:
unsigned ID;
@ -76,7 +76,7 @@ private:
const iterator RegsBegin, RegsEnd;
public:
TargetRegisterClass(unsigned id,
const MVT::ValueType *vts,
const MVT *vts,
const TargetRegisterClass * const *subcs,
const TargetRegisterClass * const *supcs,
const TargetRegisterClass * const *subregcs,
@ -118,7 +118,7 @@ public:
/// hasType - return true if this TargetRegisterClass has the ValueType vt.
///
bool hasType(MVT::ValueType vt) const {
bool hasType(MVT vt) const {
for(int i = 0; VTs[i] != MVT::Other; ++i)
if (VTs[i] == vt)
return true;
@ -324,7 +324,7 @@ public:
/// register of the given type. If type is MVT::Other, then just return any
/// register class the register belongs to.
const TargetRegisterClass *getPhysicalRegisterRegClass(unsigned Reg,
MVT::ValueType VT = MVT::Other) const;
MVT VT = MVT::Other) const;
/// getAllocatableSet - Returns a bitset indexed by register number
/// indicating if a register is allocatable or not. If a register class is

20
lib/CodeGen/SelectionDAG/CallingConvLower.cpp
View File

@ -32,8 +32,8 @@ CCState::CCState(unsigned CC, bool isVarArg, const TargetMachine &tm,
// HandleByVal - Allocate a stack slot large enough to pass an argument by
// value. The size and alignment information of the argument is encoded in its
// parameter attribute.
void CCState::HandleByVal(unsigned ValNo, MVT::ValueType ValVT,
MVT::ValueType LocVT, CCValAssign::LocInfo LocInfo,
void CCState::HandleByVal(unsigned ValNo, MVT ValVT,
MVT LocVT, CCValAssign::LocInfo LocInfo,
int MinSize, int MinAlign,
ISD::ArgFlagsTy ArgFlags) {
unsigned Align = ArgFlags.getByValAlign();
@ -62,12 +62,12 @@ void CCState::AnalyzeFormalArguments(SDNode *TheArgs, CCAssignFn Fn) {
unsigned NumArgs = TheArgs->getNumValues()-1;
for (unsigned i = 0; i != NumArgs; ++i) {
MVT::ValueType ArgVT = TheArgs->getValueType(i);
MVT ArgVT = TheArgs->getValueType(i);
ISD::ArgFlagsTy ArgFlags =
cast<ARG_FLAGSSDNode>(TheArgs->getOperand(3+i))->getArgFlags();
if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
cerr << "Formal argument #" << i << " has unhandled type "
<< MVT::getValueTypeString(ArgVT) << "\n";
<< ArgVT.getMVTString() << "\n";
abort();
}
}
@ -78,12 +78,12 @@ void CCState::AnalyzeFormalArguments(SDNode *TheArgs, CCAssignFn Fn) {
void CCState::AnalyzeReturn(SDNode *TheRet, CCAssignFn Fn) {
// Determine which register each value should be copied into.
for (unsigned i = 0, e = TheRet->getNumOperands() / 2; i != e; ++i) {
MVT::ValueType VT = TheRet->getOperand(i*2+1).getValueType();
MVT VT = TheRet->getOperand(i*2+1).getValueType();
ISD::ArgFlagsTy ArgFlags =
cast<ARG_FLAGSSDNode>(TheRet->getOperand(i*2+2))->getArgFlags();
if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)){
cerr << "Return operand #" << i << " has unhandled type "
<< MVT::getValueTypeString(VT) << "\n";
<< VT.getMVTString() << "\n";
abort();
}
}
@ -95,12 +95,12 @@ void CCState::AnalyzeReturn(SDNode *TheRet, CCAssignFn Fn) {
void CCState::AnalyzeCallOperands(SDNode *TheCall, CCAssignFn Fn) {
unsigned NumOps = (TheCall->getNumOperands() - 5) / 2;
for (unsigned i = 0; i != NumOps; ++i) {
MVT::ValueType ArgVT = TheCall->getOperand(5+2*i).getValueType();
MVT ArgVT = TheCall->getOperand(5+2*i).getValueType();
ISD::ArgFlagsTy ArgFlags =
cast<ARG_FLAGSSDNode>(TheCall->getOperand(5+2*i+1))->getArgFlags();
if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
cerr << "Call operand #" << i << " has unhandled type "
<< MVT::getValueTypeString(ArgVT) << "\n";
<< ArgVT.getMVTString() << "\n";
abort();
}
}
@ -110,10 +110,10 @@ void CCState::AnalyzeCallOperands(SDNode *TheCall, CCAssignFn Fn) {
/// incorporating info about the passed values into this state.
void CCState::AnalyzeCallResult(SDNode *TheCall, CCAssignFn Fn) {
for (unsigned i = 0, e = TheCall->getNumValues() - 1; i != e; ++i) {
MVT::ValueType VT = TheCall->getValueType(i);
MVT VT = TheCall->getValueType(i);
if (Fn(i, VT, VT, CCValAssign::Full, ISD::ArgFlagsTy(), *this)) {
cerr << "Call result #" << i << " has unhandled type "
<< MVT::getValueTypeString(VT) << "\n";
<< VT.getMVTString() << "\n";
abort();
}
}

464
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

File diff suppressed because it is too large Load Diff

572
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

File diff suppressed because it is too large Load Diff

37
lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
View File

@ -68,7 +68,7 @@ void DAGTypeLegalizer::run() {
unsigned i = 0;
unsigned NumResults = N->getNumValues();
do {
MVT::ValueType ResultVT = N->getValueType(i);
MVT ResultVT = N->getValueType(i);
switch (getTypeAction(ResultVT)) {
default:
assert(false && "Unknown action!");
@ -98,7 +98,7 @@ void DAGTypeLegalizer::run() {
unsigned NumOperands = N->getNumOperands();
bool NeedsRevisit = false;
for (i = 0; i != NumOperands; ++i) {
MVT::ValueType OpVT = N->getOperand(i).getValueType();
MVT OpVT = N->getOperand(i).getValueType();
switch (getTypeAction(OpVT)) {
default:
assert(false && "Unknown action!");
@ -472,13 +472,12 @@ void DAGTypeLegalizer::SetSplitOp(SDOperand Op, SDOperand Lo, SDOperand Hi) {
/// BitConvertToInteger - Convert to an integer of the same size.
SDOperand DAGTypeLegalizer::BitConvertToInteger(SDOperand Op) {
return DAG.getNode(ISD::BIT_CONVERT,
MVT::getIntegerType(MVT::getSizeInBits(Op.getValueType())),
Op);
unsigned BitWidth = Op.getValueType().getSizeInBits();
return DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerVT(BitWidth), Op);
}
SDOperand DAGTypeLegalizer::CreateStackStoreLoad(SDOperand Op,
MVT::ValueType DestVT) {
MVT DestVT) {
// Create the stack frame object.
SDOperand FIPtr = DAG.CreateStackTemporary(DestVT);
@ -490,14 +489,13 @@ SDOperand DAGTypeLegalizer::CreateStackStoreLoad(SDOperand Op,
/// JoinIntegers - Build an integer with low bits Lo and high bits Hi.
SDOperand DAGTypeLegalizer::JoinIntegers(SDOperand Lo, SDOperand Hi) {
MVT::ValueType LVT = Lo.getValueType();
MVT::ValueType HVT = Hi.getValueType();
MVT::ValueType NVT = MVT::getIntegerType(MVT::getSizeInBits(LVT) +
MVT::getSizeInBits(HVT));
MVT LVT = Lo.getValueType();
MVT HVT = Hi.getValueType();
MVT NVT = MVT::getIntegerVT(LVT.getSizeInBits() + HVT.getSizeInBits());
Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Lo);
Hi = DAG.getNode(ISD::ANY_EXTEND, NVT, Hi);
Hi = DAG.getNode(ISD::SHL, NVT, Hi, DAG.getConstant(MVT::getSizeInBits(LVT),
Hi = DAG.getNode(ISD::SHL, NVT, Hi, DAG.getConstant(LVT.getSizeInBits(),
TLI.getShiftAmountTy()));
return DAG.getNode(ISD::OR, NVT, Lo, Hi);
}
@ -505,13 +503,13 @@ SDOperand DAGTypeLegalizer::JoinIntegers(SDOperand Lo, SDOperand Hi) {
/// SplitInteger - Return the lower LoVT bits of Op in Lo and the upper HiVT
/// bits in Hi.
void DAGTypeLegalizer::SplitInteger(SDOperand Op,
MVT::ValueType LoVT, MVT::ValueType HiVT,
MVT LoVT, MVT HiVT,
SDOperand &Lo, SDOperand &Hi) {
assert(MVT::getSizeInBits(LoVT) + MVT::getSizeInBits(HiVT) ==
MVT::getSizeInBits(Op.getValueType()) && "Invalid integer splitting!");
assert(LoVT.getSizeInBits() + HiVT.getSizeInBits() ==
Op.getValueType().getSizeInBits() && "Invalid integer splitting!");
Lo = DAG.getNode(ISD::TRUNCATE, LoVT, Op);
Hi = DAG.getNode(ISD::SRL, Op.getValueType(), Op,
DAG.getConstant(MVT::getSizeInBits(LoVT),
DAG.getConstant(LoVT.getSizeInBits(),
TLI.getShiftAmountTy()));
Hi = DAG.getNode(ISD::TRUNCATE, HiVT, Hi);
}
@ -520,14 +518,13 @@ void DAGTypeLegalizer::SplitInteger(SDOperand Op,
/// half the size of Op's.
void DAGTypeLegalizer::SplitInteger(SDOperand Op,
SDOperand &Lo, SDOperand &Hi) {
MVT::ValueType HalfVT =
MVT::getIntegerType(MVT::getSizeInBits(Op.getValueType())/2);
MVT HalfVT = MVT::getIntegerVT(Op.getValueType().getSizeInBits()/2);
SplitInteger(Op, HalfVT, HalfVT, Lo, Hi);
}
/// MakeLibCall - Generate a libcall taking the given operands as arguments and
/// returning a result of type RetVT.
SDOperand DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT::ValueType RetVT,
SDOperand DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT RetVT,
const SDOperand *Ops, unsigned NumOps,
bool isSigned) {
TargetLowering::ArgListTy Args;
@ -536,7 +533,7 @@ SDOperand DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT::ValueType RetVT,
TargetLowering::ArgListEntry Entry;
for (unsigned i = 0; i != NumOps; ++i) {
Entry.Node = Ops[i];
Entry.Ty = MVT::getTypeForValueType(Entry.Node.getValueType());
Entry.Ty = Entry.Node.getValueType().getTypeForMVT();
Entry.isSExt = isSigned;
Entry.isZExt = !isSigned;
Args.push_back(Entry);
@ -544,7 +541,7 @@ SDOperand DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT::ValueType RetVT,
SDOperand Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
TLI.getPointerTy());
const Type *RetTy = MVT::getTypeForValueType(RetVT);
const Type *RetTy = RetVT.getTypeForMVT();
std::pair<SDOperand,SDOperand> CallInfo =
TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
CallingConv::C, false, Callee, Args, DAG);

23
lib/CodeGen/SelectionDAG/LegalizeTypes.h
View File

@ -77,7 +77,7 @@ private:
/// we need to expand it into multiple registers of a smaller integer type, or
/// we need to scalarize a one-element vector type into the element type, or
/// we need to split a vector type into smaller vector types.
LegalizeAction getTypeAction(MVT::ValueType VT) const {
LegalizeAction getTypeAction(MVT VT) const {
switch (ValueTypeActions.getTypeAction(VT)) {
default:
assert(false && "Unknown legalize action!");
@ -89,13 +89,12 @@ private:
// Expand can mean
// 1) split scalar in half, 2) convert a float to an integer,
// 3) scalarize a single-element vector, 4) split a vector in two.
if (!MVT::isVector(VT)) {
if (MVT::getSizeInBits(VT) ==
MVT::getSizeInBits(TLI.getTypeToTransformTo(VT)))
if (!VT.isVector()) {
if (VT.getSizeInBits() == TLI.getTypeToTransformTo(VT).getSizeInBits())
return FloatToInt;
else
return Expand;
} else if (MVT::getVectorNumElements(VT) == 1) {
} else if (VT.getVectorNumElements() == 1) {
return Scalarize;
} else {
return Split;
@ -104,7 +103,7 @@ private:
}
/// isTypeLegal - Return true if this type is legal on this target.
bool isTypeLegal(MVT::ValueType VT) const {
bool isTypeLegal(MVT VT) const {
return ValueTypeActions.getTypeAction(VT) == TargetLowering::Legal;
}
@ -164,12 +163,12 @@ private:
// Common routines.
SDOperand BitConvertToInteger(SDOperand Op);
SDOperand CreateStackStoreLoad(SDOperand Op, MVT::ValueType DestVT);
SDOperand CreateStackStoreLoad(SDOperand Op, MVT DestVT);
SDOperand JoinIntegers(SDOperand Lo, SDOperand Hi);
void SplitInteger(SDOperand Op, SDOperand &Lo, SDOperand &Hi);
void SplitInteger(SDOperand Op, MVT::ValueType LoVT, MVT::ValueType HiVT,
void SplitInteger(SDOperand Op, MVT LoVT, MVT HiVT,
SDOperand &Lo, SDOperand &Hi);
SDOperand MakeLibCall(RTLIB::Libcall LC, MVT::ValueType RetVT,
SDOperand MakeLibCall(RTLIB::Libcall LC, MVT RetVT,
const SDOperand *Ops, unsigned NumOps, bool isSigned);
//===--------------------------------------------------------------------===//
@ -187,7 +186,7 @@ private:
/// GetPromotedZExtOp - Get a promoted operand and zero extend it to the final
/// size.
SDOperand GetPromotedZExtOp(SDOperand Op) {
MVT::ValueType OldVT = Op.getValueType();
MVT OldVT = Op.getValueType();
Op = GetPromotedOp(Op);
return DAG.getZeroExtendInReg(Op, OldVT);
}
@ -292,10 +291,10 @@ private:
SDOperand ExpandOperand_BUILD_VECTOR(SDNode *N);
SDOperand ExpandOperand_EXTRACT_ELEMENT(SDNode *N);
SDOperand ExpandOperand_SETCC(SDNode *N);
SDOperand ExpandOperand_SINT_TO_FP(SDOperand Source, MVT::ValueType DestTy);
SDOperand ExpandOperand_SINT_TO_FP(SDOperand Source, MVT DestTy);
SDOperand ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo);
SDOperand ExpandOperand_TRUNCATE(SDNode *N);
SDOperand ExpandOperand_UINT_TO_FP(SDOperand Source, MVT::ValueType DestTy);
SDOperand ExpandOperand_UINT_TO_FP(SDOperand Source, MVT DestTy);
void ExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
ISD::CondCode &CCCode);

207
lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp
View File

@ -105,14 +105,14 @@ void DAGTypeLegalizer::ExpandResult(SDNode *N, unsigned ResNo) {
void DAGTypeLegalizer::ExpandResult_UNDEF(SDNode *N,
SDOperand &Lo, SDOperand &Hi) {
MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
Lo = Hi = DAG.getNode(ISD::UNDEF, NVT);
}
void DAGTypeLegalizer::ExpandResult_Constant(SDNode *N,
SDOperand &Lo, SDOperand &Hi) {
MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
unsigned NBitWidth = MVT::getSizeInBits(NVT);
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
unsigned NBitWidth = NVT.getSizeInBits();
const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
@ -148,9 +148,9 @@ void DAGTypeLegalizer::ExpandResult_MERGE_VALUES(SDNode *N,
void DAGTypeLegalizer::ExpandResult_ANY_EXTEND(SDNode *N,
SDOperand &Lo, SDOperand &Hi) {
MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDOperand Op = N->getOperand(0);
if (MVT::getSizeInBits(Op.getValueType()) <= MVT::getSizeInBits(NVT)) {
if (Op.getValueType().getSizeInBits() <= NVT.getSizeInBits()) {
// The low part is any extension of the input (which degenerates to a copy).
Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op);
Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined.
@ -169,9 +169,9 @@ void DAGTypeLegalizer::ExpandResult_ANY_EXTEND(SDNode *N,
void DAGTypeLegalizer::ExpandResult_ZERO_EXTEND(SDNode *N,
SDOperand &Lo, SDOperand &Hi) {
MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDOperand Op = N->getOperand(0);
if (MVT::getSizeInBits(Op.getValueType()) <= MVT::getSizeInBits(NVT)) {
if (Op.getValueType().getSizeInBits() <= NVT.getSizeInBits()) {
// The low part is zero extension of the input (which degenerates to a copy).
Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
@ -186,20 +186,20 @@ void DAGTypeLegalizer::ExpandResult_ZERO_EXTEND(SDNode *N,
// Split the promoted operand. This will simplify when it is expanded.
SplitInteger(Res, Lo, Hi);
unsigned ExcessBits =
MVT::getSizeInBits(Op.getValueType()) - MVT::getSizeInBits(NVT);
Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerType(ExcessBits));
Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits));
}
}
void DAGTypeLegalizer::ExpandResult_SIGN_EXTEND(SDNode *N,
SDOperand &Lo, SDOperand &Hi) {
MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDOperand Op = N->getOperand(0);
if (MVT::getSizeInBits(Op.getValueType()) <= MVT::getSizeInBits(NVT)) {
if (Op.getValueType().getSizeInBits() <= NVT.getSizeInBits()) {
// The low part is sign extension of the input (which degenerates to a copy).
Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0));
// The high part is obtained by SRA'ing all but one of the bits of low part.
unsigned LoSize = MVT::getSizeInBits(NVT);
unsigned LoSize = NVT.getSizeInBits();
Hi = DAG.getNode(ISD::SRA, NVT, Lo,
DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
} else {
@ -213,23 +213,23 @@ void DAGTypeLegalizer::ExpandResult_SIGN_EXTEND(SDNode *N,
// Split the promoted operand. This will simplify when it is expanded.
SplitInteger(Res, Lo, Hi);
unsigned ExcessBits =
MVT::getSizeInBits(Op.getValueType()) - MVT::getSizeInBits(NVT);
Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
DAG.getValueType(MVT::getIntegerType(ExcessBits)));
DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
}
}
void DAGTypeLegalizer::ExpandResult_AssertZext(SDNode *N,
SDOperand &Lo, SDOperand &Hi) {
GetExpandedOp(N->getOperand(0), Lo, Hi);
MVT::ValueType NVT = Lo.getValueType();
MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
unsigned NVTBits = MVT::getSizeInBits(NVT);
unsigned EVTBits = MVT::getSizeInBits(EVT);
MVT NVT = Lo.getValueType();
MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
unsigned NVTBits = NVT.getSizeInBits();
unsigned EVTBits = EVT.getSizeInBits();
if (NVTBits < EVTBits) {
Hi = DAG.getNode(ISD::AssertZext, NVT, Hi,
DAG.getValueType(MVT::getIntegerType(EVTBits - NVTBits)));
DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
} else {
Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT));
// The high part must be zero, make it explicit.
@ -239,19 +239,19 @@ void DAGTypeLegalizer::ExpandResult_AssertZext(SDNode *N,
void DAGTypeLegalizer::ExpandResult_TRUNCATE(SDNode *N,
SDOperand &Lo, SDOperand &Hi) {
MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0));
Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0),
DAG.getConstant(MVT::getSizeInBits(NVT),
DAG.getConstant(NVT.getSizeInBits(),
TLI.getShiftAmountTy()));
Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi);
}
void DAGTypeLegalizer::ExpandResult_BIT_CONVERT(SDNode *N,
SDOperand &Lo, SDOperand &Hi) {
MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDOperand InOp = N->getOperand(0);
MVT::ValueType InVT = InOp.getValueType();
MVT InVT = InOp.getValueType();
// Handle some special cases efficiently.
switch (getTypeAction(InVT)) {
@ -299,9 +299,9 @@ void DAGTypeLegalizer::ExpandResult_BIT_CONVERT(SDNode *N,
void DAGTypeLegalizer::
ExpandResult_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
GetExpandedOp(N->getOperand(0), Lo, Hi);
MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
if (MVT::getSizeInBits(EVT) <= MVT::getSizeInBits(Lo.getValueType())) {
if (EVT.getSizeInBits() <= Lo.getValueType().getSizeInBits()) {
// sext_inreg the low part if needed.
Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo,
N->getOperand(1));
@ -309,21 +309,21 @@ ExpandResult_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
// The high part gets the sign extension from the lo-part. This handles
// things like sextinreg V:i64 from i8.
Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo,
DAG.getConstant(MVT::getSizeInBits(Hi.getValueType())-1,
DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
TLI.getShiftAmountTy()));
} else {
// For example, extension of an i48 to an i64. Leave the low part alone,
// sext_inreg the high part.
unsigned ExcessBits =
MVT::getSizeInBits(EVT) - MVT::getSizeInBits(Lo.getValueType());
EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
DAG.getValueType(MVT::getIntegerType(ExcessBits)));
DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
}
}
void DAGTypeLegalizer::ExpandResult_FP_TO_SINT(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
MVT::ValueType VT = N->getValueType(0);
MVT VT = N->getValueType(0);
SDOperand Op = N->getOperand(0);
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
if (VT == MVT::i64) {
@ -352,7 +352,7 @@ void DAGTypeLegalizer::ExpandResult_FP_TO_SINT(SDNode *N, SDOperand &Lo,
void DAGTypeLegalizer::ExpandResult_FP_TO_UINT(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
MVT::ValueType VT = N->getValueType(0);
MVT VT = N->getValueType(0);
SDOperand Op = N->getOperand(0);
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
if (VT == MVT::i64) {
@ -382,8 +382,8 @@ void DAGTypeLegalizer::ExpandResult_FP_TO_UINT(SDNode *N, SDOperand &Lo,
void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N,
SDOperand &Lo, SDOperand &Hi) {
// FIXME: Add support for indexed loads.
MVT::ValueType VT = N->getValueType(0);
MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
MVT VT = N->getValueType(0);
MVT NVT = TLI.getTypeToTransformTo(VT);
SDOperand Ch = N->getChain(); // Legalize the chain.
SDOperand Ptr = N->getBasePtr(); // Legalize the pointer.
ISD::LoadExtType ExtType = N->getExtensionType();
@ -391,13 +391,13 @@ void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N,
unsigned Alignment = N->getAlignment();
bool isVolatile = N->isVolatile();
assert(!(MVT::getSizeInBits(NVT) & 7) && "Expanded type not byte sized!");
assert(!(NVT.getSizeInBits() & 7) && "Expanded type not byte sized!");
if (ExtType == ISD::NON_EXTLOAD) {
Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
isVolatile, Alignment);
// Increment the pointer to the other half.
unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
unsigned IncrementSize = NVT.getSizeInBits()/8;
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
DAG.getIntPtrConstant(IncrementSize));
Hi = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
@ -411,8 +411,8 @@ void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N,
// Handle endianness of the load.
if (TLI.isBigEndian())
std::swap(Lo, Hi);
} else if (MVT::getSizeInBits(N->getMemoryVT()) <= MVT::getSizeInBits(NVT)) {
MVT::ValueType EVT = N->getMemoryVT();
} else if (N->getMemoryVT().getSizeInBits() <= NVT.getSizeInBits()) {
MVT EVT = N->getMemoryVT();
Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT,
isVolatile, Alignment);
@ -423,7 +423,7 @@ void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N,
if (ExtType == ISD::SEXTLOAD) {
// The high part is obtained by SRA'ing all but one of the bits of the
// lo part.
unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
unsigned LoSize = Lo.getValueType().getSizeInBits();
Hi = DAG.getNode(ISD::SRA, NVT, Lo,
DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
} else if (ExtType == ISD::ZEXTLOAD) {
@ -440,11 +440,11 @@ void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N,
isVolatile, Alignment);
unsigned ExcessBits =
MVT::getSizeInBits(N->getMemoryVT()) - MVT::getSizeInBits(NVT);
MVT::ValueType NEVT = MVT::getIntegerType(ExcessBits);
N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
MVT NEVT = MVT::getIntegerVT(ExcessBits);
// Increment the pointer to the other half.
unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
unsigned IncrementSize = NVT.getSizeInBits()/8;
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
DAG.getIntPtrConstant(IncrementSize));
Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(),
@ -458,14 +458,14 @@ void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N,
} else {
// Big-endian - high bits are at low addresses. Favor aligned loads at
// the cost of some bit-fiddling.
MVT::ValueType EVT = N->getMemoryVT();
unsigned EBytes = MVT::getStoreSizeInBits(EVT)/8;
unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
MVT EVT = N->getMemoryVT();
unsigned EBytes = EVT.getStoreSizeInBits()/8;
unsigned IncrementSize = NVT.getSizeInBits()/8;
unsigned ExcessBits = (EBytes - IncrementSize)*8;
// Load both the high bits and maybe some of the low bits.
Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
MVT::getIntegerType(MVT::getSizeInBits(EVT)-ExcessBits),
MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
isVolatile, Alignment);
// Increment the pointer to the other half.
@ -473,7 +473,8 @@ void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N,
DAG.getIntPtrConstant(IncrementSize));
// Load the rest of the low bits.
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(),
SVOffset+IncrementSize, MVT::getIntegerType(ExcessBits),
SVOffset+IncrementSize,
MVT::getIntegerVT(ExcessBits),
isVolatile, MinAlign(Alignment, IncrementSize));
// Build a factor node to remember that this load is independent of the
@ -481,7 +482,7 @@ void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N,
Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
if (ExcessBits < MVT::getSizeInBits(NVT)) {
if (ExcessBits < NVT.getSizeInBits()) {
// Transfer low bits from the bottom of Hi to the top of Lo.
Lo = DAG.getNode(ISD::OR, NVT, Lo,
DAG.getNode(ISD::SHL, NVT, Hi,
@ -489,7 +490,7 @@ void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N,
TLI.getShiftAmountTy())));
// Move high bits to the right position in Hi.
Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi,
DAG.getConstant(MVT::getSizeInBits(NVT) - ExcessBits,
DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
TLI.getShiftAmountTy()));
}
}
@ -602,8 +603,8 @@ void DAGTypeLegalizer::ExpandResult_ADDSUBE(SDNode *N,
void DAGTypeLegalizer::ExpandResult_MUL(SDNode *N,
SDOperand &Lo, SDOperand &Hi) {
MVT::ValueType VT = N->getValueType(0);
MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
MVT VT = N->getValueType(0);
MVT NVT = TLI.getTypeToTransformTo(VT);
bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
@ -613,8 +614,8 @@ void DAGTypeLegalizer::ExpandResult_MUL(SDNode *N,
SDOperand LL, LH, RL, RH;
GetExpandedOp(N->getOperand(0), LL, LH);
GetExpandedOp(N->getOperand(1), RL, RH);
unsigned OuterBitSize = MVT::getSizeInBits(VT);
unsigned BitSize = MVT::getSizeInBits(NVT);
unsigned OuterBitSize = VT.getSizeInBits();
unsigned BitSize = NVT.getSizeInBits();
unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
@ -705,7 +706,7 @@ void DAGTypeLegalizer::ExpandResult_UREM(SDNode *N,
void DAGTypeLegalizer::ExpandResult_Shift(SDNode *N,
SDOperand &Lo, SDOperand &Hi) {
MVT::ValueType VT = N->getValueType(0);
MVT VT = N->getValueType(0);
// If we can emit an efficient shift operation, do so now. Check to see if
// the RHS is a constant.
@ -730,7 +731,7 @@ void DAGTypeLegalizer::ExpandResult_Shift(SDNode *N,
// Next check to see if the target supports this SHL_PARTS operation or if it
// will custom expand it.
MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
MVT NVT = TLI.getTypeToTransformTo(VT);
TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
Action == TargetLowering::Custom) {
@ -739,7 +740,7 @@ void DAGTypeLegalizer::ExpandResult_Shift(SDNode *N,
GetExpandedOp(N->getOperand(0), LHSL, LHSH);
SDOperand Ops[] = { LHSL, LHSH, N->getOperand(1) };
MVT::ValueType VT = LHSL.getValueType();
MVT VT = LHSL.getValueType();
Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
Hi = Lo.getValue(1);
return;
@ -770,7 +771,7 @@ void DAGTypeLegalizer::ExpandResult_CTLZ(SDNode *N,
SDOperand &Lo, SDOperand &Hi) {
// ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
GetExpandedOp(N->getOperand(0), Lo, Hi);
MVT::ValueType NVT = Lo.getValueType();
MVT NVT = Lo.getValueType();
SDOperand HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
DAG.getConstant(0, NVT), ISD::SETNE);
@ -780,7 +781,7 @@ void DAGTypeLegalizer::ExpandResult_CTLZ(SDNode *N,
Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ,
DAG.getNode(ISD::ADD, NVT, LoLZ,
DAG.getConstant(MVT::getSizeInBits(NVT), NVT)));
DAG.getConstant(NVT.getSizeInBits(), NVT)));
Hi = DAG.getConstant(0, NVT);
}
@ -788,7 +789,7 @@ void DAGTypeLegalizer::ExpandResult_CTPOP(SDNode *N,
SDOperand &Lo, SDOperand &Hi) {
// ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
GetExpandedOp(N->getOperand(0), Lo, Hi);
MVT::ValueType NVT = Lo.getValueType();
MVT NVT = Lo.getValueType();
Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo),
DAG.getNode(ISD::CTPOP, NVT, Hi));
Hi = DAG.getConstant(0, NVT);
@ -798,7 +799,7 @@ void DAGTypeLegalizer::ExpandResult_CTTZ(SDNode *N,
SDOperand &Lo, SDOperand &Hi) {
// cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
GetExpandedOp(N->getOperand(0), Lo, Hi);
MVT::ValueType NVT = Lo.getValueType();
MVT NVT = Lo.getValueType();
SDOperand LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo,
DAG.getConstant(0, NVT), ISD::SETNE);
@ -808,7 +809,7 @@ void DAGTypeLegalizer::ExpandResult_CTTZ(SDNode *N,
Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ,
DAG.getNode(ISD::ADD, NVT, HiLZ,
DAG.getConstant(MVT::getSizeInBits(NVT), NVT)));
DAG.getConstant(NVT.getSizeInBits(), NVT)));
Hi = DAG.getConstant(0, NVT);
}
@ -816,25 +817,24 @@ void DAGTypeLegalizer::ExpandResult_EXTRACT_VECTOR_ELT(SDNode *N,
SDOperand &Lo,
SDOperand &Hi) {
SDOperand OldVec = N->getOperand(0);
unsigned OldElts = MVT::getVectorNumElements(OldVec.getValueType());
unsigned OldElts = OldVec.getValueType().getVectorNumElements();
// Convert to a vector of the expanded element type, for example
// <2 x i64> -> <4 x i32>.
MVT::ValueType OldVT = N->getValueType(0);
MVT::ValueType NewVT = TLI.getTypeToTransformTo(OldVT);
assert(MVT::getSizeInBits(OldVT) == 2 * MVT::getSizeInBits(NewVT) &&
MVT OldVT = N->getValueType(0);
MVT NewVT = TLI.getTypeToTransformTo(OldVT);
assert(OldVT.getSizeInBits() == 2 * NewVT.getSizeInBits() &&
"Do not know how to handle this expansion!");
SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT,
MVT::getVectorType(NewVT, 2 * OldElts),
MVT::getVectorVT(NewVT, 2*OldElts),
OldVec);
// Extract the elements at 2 * Idx and 2 * Idx + 1 from the new vector.
SDOperand Idx = N->getOperand(1);
// Make sure the type of Idx is big enough to hold the new values.
if (MVT::getSizeInBits(Idx.getValueType()) <
MVT::getSizeInBits(TLI.getPointerTy()))
if (Idx.getValueType().getSizeInBits() < TLI.getPointerTy().getSizeInBits())
Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
Idx = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, Idx);
@ -856,10 +856,10 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
SDOperand InL, InH;
GetExpandedOp(N->getOperand(0), InL, InH);
MVT::ValueType NVT = InL.getValueType();
unsigned VTBits = MVT::getSizeInBits(N->getValueType(0));
unsigned NVTBits = MVT::getSizeInBits(NVT);
MVT::ValueType ShTy = N->getOperand(1).getValueType();
MVT NVT = InL.getValueType();
unsigned VTBits = N->getValueType(0).getSizeInBits();
unsigned NVTBits = NVT.getSizeInBits();
MVT ShTy = N->getOperand(1).getValueType();
if (N->getOpcode() == ISD::SHL) {
if (Amt > VTBits) {
@ -932,10 +932,10 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
bool DAGTypeLegalizer::
ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
SDOperand Amt = N->getOperand(1);
MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
MVT::ValueType ShTy = Amt.getValueType();
MVT::ValueType ShBits = MVT::getSizeInBits(ShTy);
unsigned NVTBits = MVT::getSizeInBits(NVT);
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
MVT ShTy = Amt.getValueType();
unsigned ShBits = ShTy.getSizeInBits();
unsigned NVTBits = NVT.getSizeInBits();
assert(isPowerOf2_32(NVTBits) &&
"Expanded integer type size not a power of two!");
@ -1077,14 +1077,14 @@ SDOperand DAGTypeLegalizer::ExpandOperand_TRUNCATE(SDNode *N) {
}
SDOperand DAGTypeLegalizer::ExpandOperand_BIT_CONVERT(SDNode *N) {
if (MVT::isVector(N->getValueType(0))) {
if (N->getValueType(0).isVector()) {
// An illegal integer type is being converted to a legal vector type.
// Make a two element vector out of the expanded parts and convert that
// instead, but only if the new vector type is legal (otherwise there
// is no point, and it might create expansion loops). For example, on
// x86 this turns v1i64 = BIT_CONVERT i64 into v1i64 = BIT_CONVERT v2i32.
MVT::ValueType OVT = N->getOperand(0).getValueType();
MVT::ValueType NVT = MVT::getVectorType(TLI.getTypeToTransformTo(OVT), 2);
MVT OVT = N->getOperand(0).getValueType();
MVT NVT = MVT::getVectorVT(TLI.getTypeToTransformTo(OVT), 2);
if (isTypeLegal(NVT)) {
SDOperand Parts[2];
@ -1103,9 +1103,9 @@ SDOperand DAGTypeLegalizer::ExpandOperand_BIT_CONVERT(SDNode *N) {
}
SDOperand DAGTypeLegalizer::ExpandOperand_SINT_TO_FP(SDOperand Source,
MVT::ValueType DestTy) {
MVT DestTy) {
// We know the destination is legal, but that the input needs to be expanded.
MVT::ValueType SourceVT = Source.getValueType();
MVT SourceVT = Source.getValueType();
// Check to see if the target has a custom way to lower this. If so, use it.
switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
@ -1149,7 +1149,7 @@ SDOperand DAGTypeLegalizer::ExpandOperand_SINT_TO_FP(SDOperand Source,
}
SDOperand DAGTypeLegalizer::ExpandOperand_UINT_TO_FP(SDOperand Source,
MVT::ValueType DestTy) {
MVT DestTy) {
// We know the destination is legal, but that the input needs to be expanded.
assert(getTypeAction(Source.getValueType()) == Expand &&
"This is not an expansion!");
@ -1179,7 +1179,7 @@ SDOperand DAGTypeLegalizer::ExpandOperand_UINT_TO_FP(SDOperand Source,
SDOperand FudgeInReg;
if (DestTy == MVT::f32)
FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
else if (DestTy.getSizeInBits() > MVT(MVT::f32).getSizeInBits())
// FIXME: Avoid the extend by construction the right constantpool?
FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
CPIdx, NULL, 0, MVT::f32);
@ -1234,7 +1234,7 @@ void DAGTypeLegalizer::ExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
GetExpandedOp(NewLHS, LHSLo, LHSHi);
GetExpandedOp(NewRHS, RHSLo, RHSHi);
MVT::ValueType VT = NewLHS.getValueType();
MVT VT = NewLHS.getValueType();
if (VT == MVT::ppcf128) {
// FIXME: This generated code sucks. We want to generate
// FCMP crN, hi1, hi2
@ -1343,8 +1343,8 @@ SDOperand DAGTypeLegalizer::ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo) {
// FIXME: Add support for indexed stores.
assert(OpNo == 1 && "Can only expand the stored value so far");
MVT::ValueType VT = N->getOperand(1).getValueType();
MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
MVT VT = N->getOperand(1).getValueType();
MVT NVT = TLI.getTypeToTransformTo(VT);
SDOperand Ch = N->getChain();
SDOperand Ptr = N->getBasePtr();
int SVOffset = N->getSrcValueOffset();
@ -1352,12 +1352,12 @@ SDOperand DAGTypeLegalizer::ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo) {
bool isVolatile = N->isVolatile();
SDOperand Lo, Hi;
assert(!(MVT::getSizeInBits(NVT) & 7) && "Expanded type not byte sized!");
assert(!(NVT.getSizeInBits() & 7) && "Expanded type not byte sized!");
if (!N->isTruncatingStore()) {
unsigned IncrementSize = 0;
GetExpandedOp(N->getValue(), Lo, Hi);
IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
IncrementSize = Hi.getValueType().getSizeInBits()/8;
if (TLI.isBigEndian())
std::swap(Lo, Hi);
@ -1371,7 +1371,7 @@ SDOperand DAGTypeLegalizer::ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo) {
Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
isVolatile, MinAlign(Alignment, IncrementSize));
return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
} else if (MVT::getSizeInBits(N->getMemoryVT()) <= MVT::getSizeInBits(NVT)) {
} else if (N->getMemoryVT().getSizeInBits() <= NVT.getSizeInBits()) {
GetExpandedOp(N->getValue(), Lo, Hi);
return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
N->getMemoryVT(), isVolatile, Alignment);
@ -1383,11 +1383,11 @@ SDOperand DAGTypeLegalizer::ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo) {
isVolatile, Alignment);
unsigned ExcessBits =
MVT::getSizeInBits(N->getMemoryVT()) - MVT::getSizeInBits(NVT);
MVT::ValueType NEVT = MVT::getIntegerType(ExcessBits);
N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
MVT NEVT = MVT::getIntegerVT(ExcessBits);
// Increment the pointer to the other half.
unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
unsigned IncrementSize = NVT.getSizeInBits()/8;
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
DAG.getIntPtrConstant(IncrementSize));
Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
@ -1399,17 +1399,16 @@ SDOperand DAGTypeLegalizer::ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo) {
// the cost of some bit-fiddling.
GetExpandedOp(N->getValue(), Lo, Hi);
MVT::ValueType EVT = N->getMemoryVT();
unsigned EBytes = MVT::getStoreSizeInBits(EVT)/8;
unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
MVT EVT = N->getMemoryVT();
unsigned EBytes = EVT.getStoreSizeInBits()/8;
unsigned IncrementSize = NVT.getSizeInBits()/8;
unsigned ExcessBits = (EBytes - IncrementSize)*8;
MVT::ValueType HiVT =
MVT::getIntegerType(MVT::getSizeInBits(EVT)-ExcessBits);
MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
if (ExcessBits < MVT::getSizeInBits(NVT)) {
if (ExcessBits < NVT.getSizeInBits()) {
// Transfer high bits from the top of Lo to the bottom of Hi.
Hi = DAG.getNode(ISD::SHL, NVT, Hi,
DAG.getConstant(MVT::getSizeInBits(NVT) - ExcessBits,
DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
TLI.getShiftAmountTy()));
Hi = DAG.getNode(ISD::OR, NVT, Hi,
DAG.getNode(ISD::SRL, NVT, Lo,
@ -1427,7 +1426,7 @@ SDOperand DAGTypeLegalizer::ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo) {
// Store the lowest ExcessBits bits in the second half.
Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(),
SVOffset+IncrementSize,
MVT::getIntegerType(ExcessBits),
MVT::getIntegerVT(ExcessBits),
isVolatile, MinAlign(Alignment, IncrementSize));
return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
}
@ -1435,12 +1434,12 @@ SDOperand DAGTypeLegalizer::ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo) {
SDOperand DAGTypeLegalizer::ExpandOperand_BUILD_VECTOR(SDNode *N) {
// The vector type is legal but the element type needs expansion.
MVT::ValueType VecVT = N->getValueType(0);
unsigned NumElts = MVT::getVectorNumElements(VecVT);
MVT::ValueType OldVT = N->getOperand(0).getValueType();
MVT::ValueType NewVT = TLI.getTypeToTransformTo(OldVT);
MVT VecVT = N->getValueType(0);
unsigned NumElts = VecVT.getVectorNumElements();
MVT OldVT = N->getOperand(0).getValueType();
MVT NewVT = TLI.getTypeToTransformTo(OldVT);
assert(MVT::getSizeInBits(OldVT) == 2 * MVT::getSizeInBits(NewVT) &&
assert(OldVT.getSizeInBits() == 2 * NewVT.getSizeInBits() &&
"Do not know how to expand this operand!");
// Build a vector of twice the length out of the expanded elements.
@ -1458,7 +1457,7 @@ SDOperand DAGTypeLegalizer::ExpandOperand_BUILD_VECTOR(SDNode *N) {
}
SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR,
MVT::getVectorType(NewVT, NewElts.size()),
MVT::getVectorVT(NewVT, NewElts.size()),
&NewElts[0], NewElts.size());
// Convert the new vector to the old vector type.

37
lib/CodeGen/SelectionDAG/LegalizeTypesFloatToInt.cpp
View File

@ -21,7 +21,7 @@
using namespace llvm;
/// GetFPLibCall - Return the right libcall for the given floating point type.
static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT,
static RTLIB::Libcall GetFPLibCall(MVT VT,
RTLIB::Libcall Call_F32,
RTLIB::Libcall Call_F64,
RTLIB::Libcall Call_F80,
@ -105,7 +105,7 @@ SDOperand DAGTypeLegalizer::FloatToIntRes_ConstantFP(ConstantFPSDNode *N) {
}
SDOperand DAGTypeLegalizer::FloatToIntRes_FADD(SDNode *N) {
MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDOperand Ops[2] = { GetIntegerOp(N->getOperand(0)),
GetIntegerOp(N->getOperand(1)) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
@ -120,11 +120,11 @@ SDOperand DAGTypeLegalizer::FloatToIntRes_FCOPYSIGN(SDNode *N) {
SDOperand LHS = GetIntegerOp(N->getOperand(0));
SDOperand RHS = BitConvertToInteger(N->getOperand(1));
MVT::ValueType LVT = LHS.getValueType();
MVT::ValueType RVT = RHS.getValueType();
MVT LVT = LHS.getValueType();
MVT RVT = RHS.getValueType();
unsigned LSize = MVT::getSizeInBits(LVT);
unsigned RSize = MVT::getSizeInBits(RVT);
unsigned LSize = LVT.getSizeInBits();
unsigned RSize = RVT.getSizeInBits();
// First get the sign bit of second operand.
SDOperand SignBit = DAG.getNode(ISD::SHL, RVT, DAG.getConstant(1, RVT),
@ -133,7 +133,7 @@ SDOperand DAGTypeLegalizer::FloatToIntRes_FCOPYSIGN(SDNode *N) {
SignBit = DAG.getNode(ISD::AND, RVT, RHS, SignBit);
// Shift right or sign-extend it if the two operands have different types.
int SizeDiff = MVT::getSizeInBits(RVT) - MVT::getSizeInBits(LVT);
int SizeDiff = RVT.getSizeInBits() - LVT.getSizeInBits();
if (SizeDiff > 0) {
SignBit = DAG.getNode(ISD::SRL, RVT, SignBit,
DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
@ -156,7 +156,7 @@ SDOperand DAGTypeLegalizer::FloatToIntRes_FCOPYSIGN(SDNode *N) {
}
SDOperand DAGTypeLegalizer::FloatToIntRes_FMUL(SDNode *N) {
MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDOperand Ops[2] = { GetIntegerOp(N->getOperand(0)),
GetIntegerOp(N->getOperand(1)) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
@ -168,7 +168,7 @@ SDOperand DAGTypeLegalizer::FloatToIntRes_FMUL(SDNode *N) {
}
SDOperand DAGTypeLegalizer::FloatToIntRes_FSUB(SDNode *N) {
MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDOperand Ops[2] = { GetIntegerOp(N->getOperand(0)),
GetIntegerOp(N->getOperand(1)) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
@ -181,8 +181,8 @@ SDOperand DAGTypeLegalizer::FloatToIntRes_FSUB(SDNode *N) {
SDOperand DAGTypeLegalizer::FloatToIntRes_LOAD(SDNode *N) {
LoadSDNode *L = cast<LoadSDNode>(N);
MVT::ValueType VT = N->getValueType(0);
MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
MVT VT = N->getValueType(0);
MVT NVT = TLI.getTypeToTransformTo(VT);
if (L->getExtensionType() == ISD::NON_EXTLOAD)
return DAG.getLoad(L->getAddressingMode(), L->getExtensionType(),
@ -202,7 +202,7 @@ SDOperand DAGTypeLegalizer::FloatToIntRes_LOAD(SDNode *N) {
SDOperand DAGTypeLegalizer::FloatToIntRes_XINT_TO_FP(SDNode *N) {
bool isSigned = N->getOpcode() == ISD::SINT_TO_FP;
MVT::ValueType DestVT = N->getValueType(0);
MVT DestVT = N->getValueType(0);
SDOperand Op = N->getOperand(0);
if (Op.getValueType() == MVT::i32) {
@ -212,8 +212,9 @@ SDOperand DAGTypeLegalizer::FloatToIntRes_XINT_TO_FP(SDNode *N) {
SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64);
// word offset constant for Hi/Lo address computation
SDOperand Offset = DAG.getConstant(MVT::getSizeInBits(MVT::i32) / 8,
TLI.getPointerTy());
SDOperand Offset =
DAG.getConstant(MVT(MVT::i32).getSizeInBits() / 8,
TLI.getPointerTy());
// set up Hi and Lo (into buffer) address based on endian
SDOperand Hi = StackSlot;
SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, Offset);
@ -251,10 +252,12 @@ SDOperand DAGTypeLegalizer::FloatToIntRes_XINT_TO_FP(SDNode *N) {
if (DestVT == MVT::f64) {
// do nothing
Result = Sub;
} else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
} else if (DestVT.getSizeInBits() <
MVT(MVT::f64).getSizeInBits()) {
Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
DAG.getIntPtrConstant(0));
} else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
} else if (DestVT.getSizeInBits() >
MVT(MVT::f64).getSizeInBits()) {
Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
}
return BitConvertToInteger(Result);
@ -273,7 +276,7 @@ SDOperand DAGTypeLegalizer::FloatToIntRes_XINT_TO_FP(SDNode *N) {
// as a negative number. To counteract this, the dynamic code adds an
// offset depending on the data type.
uint64_t FF;
switch (Op.getValueType()) {
switch (Op.getValueType().getSimpleVT()) {
default: assert(0 && "Unsupported integer type!");
case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)

92
lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp
View File

@ -91,7 +91,7 @@ SDOperand DAGTypeLegalizer::PromoteResult_UNDEF(SDNode *N) {
}
SDOperand DAGTypeLegalizer::PromoteResult_Constant(SDNode *N) {
MVT::ValueType VT = N->getValueType(0);
MVT VT = N->getValueType(0);
// Zero extend things like i1, sign extend everything else. It shouldn't
// matter in theory which one we pick, but this tends to give better code?
unsigned Opc = VT != MVT::i1 ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
@ -115,8 +115,8 @@ SDOperand DAGTypeLegalizer::PromoteResult_TRUNCATE(SDNode *N) {
break;
}
MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
assert(MVT::getSizeInBits(Res.getValueType()) >= MVT::getSizeInBits(NVT) &&
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
assert(Res.getValueType().getSizeInBits() >= NVT.getSizeInBits() &&
"Truncation doesn't make sense!");
if (Res.getValueType() == NVT)
return Res;
@ -126,11 +126,11 @@ SDOperand DAGTypeLegalizer::PromoteResult_TRUNCATE(SDNode *N) {
}
SDOperand DAGTypeLegalizer::PromoteResult_INT_EXTEND(SDNode *N) {
MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
if (getTypeAction(N->getOperand(0).getValueType()) == Promote) {
SDOperand Res = GetPromotedOp(N->getOperand(0));
assert(MVT::getSizeInBits(Res.getValueType()) <= MVT::getSizeInBits(NVT) &&
assert(Res.getValueType().getSizeInBits() <= NVT.getSizeInBits() &&
"Extension doesn't make sense!");
// If the result and operand types are the same after promotion, simplify
@ -168,7 +168,7 @@ SDOperand DAGTypeLegalizer::PromoteResult_FP_TO_XINT(SDNode *N) {
Op = GetPromotedOp(Op);
unsigned NewOpc = N->getOpcode();
MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
// If we're promoting a UINT to a larger size, check to see if the new node
// will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
@ -194,7 +194,7 @@ SDOperand DAGTypeLegalizer::PromoteResult_SETCC(SDNode *N) {
SDOperand DAGTypeLegalizer::PromoteResult_LOAD(LoadSDNode *N) {
// FIXME: Add support for indexed loads.
MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
ISD::LoadExtType ExtType =
ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
SDOperand Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
@ -218,9 +218,9 @@ SDOperand DAGTypeLegalizer::PromoteResult_BUILD_PAIR(SDNode *N) {
SDOperand DAGTypeLegalizer::PromoteResult_BIT_CONVERT(SDNode *N) {
SDOperand InOp = N->getOperand(0);
MVT::ValueType InVT = InOp.getValueType();
MVT::ValueType NInVT = TLI.getTypeToTransformTo(InVT);
MVT::ValueType OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
MVT InVT = InOp.getValueType();
MVT NInVT = TLI.getTypeToTransformTo(InVT);
MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
switch (getTypeAction(InVT)) {
default:
@ -229,7 +229,7 @@ SDOperand DAGTypeLegalizer::PromoteResult_BIT_CONVERT(SDNode *N) {
case Legal:
break;
case Promote:
if (MVT::getSizeInBits(OutVT) == MVT::getSizeInBits(NInVT))
if (OutVT.getSizeInBits() == NInVT.getSizeInBits())
// The input promotes to the same size. Convert the promoted value.
return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedOp(InOp));
break;
@ -254,7 +254,7 @@ SDOperand DAGTypeLegalizer::PromoteResult_BIT_CONVERT(SDNode *N) {
std::swap(Lo, Hi);
InOp = DAG.getNode(ISD::ANY_EXTEND,
MVT::getIntegerType(MVT::getSizeInBits(OutVT)),
MVT::getIntegerVT(OutVT.getSizeInBits()),
JoinIntegers(Lo, Hi));
return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp);
}
@ -278,7 +278,7 @@ SDOperand DAGTypeLegalizer::PromoteResult_SDIV(SDNode *N) {
// Sign extend the input.
SDOperand LHS = GetPromotedOp(N->getOperand(0));
SDOperand RHS = GetPromotedOp(N->getOperand(1));
MVT::ValueType VT = N->getValueType(0);
MVT VT = N->getValueType(0);
LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS,
DAG.getValueType(VT));
RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS,
@ -291,7 +291,7 @@ SDOperand DAGTypeLegalizer::PromoteResult_UDIV(SDNode *N) {
// Zero extend the input.
SDOperand LHS = GetPromotedOp(N->getOperand(0));
SDOperand RHS = GetPromotedOp(N->getOperand(1));
MVT::ValueType VT = N->getValueType(0);
MVT VT = N->getValueType(0);
LHS = DAG.getZeroExtendInReg(LHS, VT);
RHS = DAG.getZeroExtendInReg(RHS, VT);
@ -305,8 +305,8 @@ SDOperand DAGTypeLegalizer::PromoteResult_SHL(SDNode *N) {
SDOperand DAGTypeLegalizer::PromoteResult_SRA(SDNode *N) {
// The input value must be properly sign extended.
MVT::ValueType VT = N->getValueType(0);
MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
MVT VT = N->getValueType(0);
MVT NVT = TLI.getTypeToTransformTo(VT);
SDOperand Res = GetPromotedOp(N->getOperand(0));
Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT));
return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1));
@ -314,8 +314,8 @@ SDOperand DAGTypeLegalizer::PromoteResult_SRA(SDNode *N) {
SDOperand DAGTypeLegalizer::PromoteResult_SRL(SDNode *N) {
// The input value must be properly zero extended.
MVT::ValueType VT = N->getValueType(0);
MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
MVT VT = N->getValueType(0);
MVT NVT = TLI.getTypeToTransformTo(VT);
SDOperand Res = GetPromotedZExtOp(N->getOperand(0));
return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1));
}
@ -335,41 +335,41 @@ SDOperand DAGTypeLegalizer::PromoteResult_SELECT_CC(SDNode *N) {
SDOperand DAGTypeLegalizer::PromoteResult_CTLZ(SDNode *N) {
SDOperand Op = GetPromotedOp(N->getOperand(0));
MVT::ValueType OVT = N->getValueType(0);
MVT::ValueType NVT = Op.getValueType();
MVT OVT = N->getValueType(0);
MVT NVT = Op.getValueType();
// Zero extend to the promoted type and do the count there.
Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT));
// Subtract off the extra leading bits in the bigger type.
return DAG.getNode(ISD::SUB, NVT, Op,
DAG.getConstant(MVT::getSizeInBits(NVT) -
MVT::getSizeInBits(OVT), NVT));
DAG.getConstant(NVT.getSizeInBits() -
OVT.getSizeInBits(), NVT));
}
SDOperand DAGTypeLegalizer::PromoteResult_CTPOP(SDNode *N) {
SDOperand Op = GetPromotedOp(N->getOperand(0));
MVT::ValueType OVT = N->getValueType(0);
MVT::ValueType NVT = Op.getValueType();
MVT OVT = N->getValueType(0);
MVT NVT = Op.getValueType();
// Zero extend to the promoted type and do the count there.
return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT));
}
SDOperand DAGTypeLegalizer::PromoteResult_CTTZ(SDNode *N) {
SDOperand Op = GetPromotedOp(N->getOperand(0));
MVT::ValueType OVT = N->getValueType(0);
MVT::ValueType NVT = Op.getValueType();
MVT OVT = N->getValueType(0);
MVT NVT = Op.getValueType();
// The count is the same in the promoted type except if the original
// value was zero. This can be handled by setting the bit just off
// the top of the original type.
Op = DAG.getNode(ISD::OR, NVT, Op,
// FIXME: Do this using an APINT constant.
DAG.getConstant(1UL << MVT::getSizeInBits(OVT), NVT));
DAG.getConstant(1UL << OVT.getSizeInBits(), NVT));
return DAG.getNode(ISD::CTTZ, NVT, Op);
}
SDOperand DAGTypeLegalizer::PromoteResult_EXTRACT_VECTOR_ELT(SDNode *N) {
MVT::ValueType OldVT = N->getValueType(0);
MVT OldVT = N->getValueType(0);
SDOperand OldVec = N->getOperand(0);
unsigned OldElts = MVT::getVectorNumElements(OldVec.getValueType());
unsigned OldElts = OldVec.getValueType().getVectorNumElements();
if (OldElts == 1) {
assert(!isTypeLegal(OldVec.getValueType()) &&
@ -384,11 +384,11 @@ SDOperand DAGTypeLegalizer::PromoteResult_EXTRACT_VECTOR_ELT(SDNode *N) {
// Convert to a vector half as long with an element type of twice the width,
// for example <4 x i16> -> <2 x i32>.
assert(!(OldElts & 1) && "Odd length vectors not supported!");
MVT::ValueType NewVT = MVT::getIntegerType(2 * MVT::getSizeInBits(OldVT));
assert(!MVT::isExtendedVT(OldVT) && !MVT::isExtendedVT(NewVT));
MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
assert(OldVT.isSimple() && NewVT.isSimple());
SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT,
MVT::getVectorType(NewVT, OldElts / 2),
MVT::getVectorVT(NewVT, OldElts / 2),
OldVec);
// Extract the element at OldIdx / 2 from the new vector.
@ -401,7 +401,7 @@ SDOperand DAGTypeLegalizer::PromoteResult_EXTRACT_VECTOR_ELT(SDNode *N) {
// Hi if it was odd.
SDOperand Lo = Elt;
SDOperand Hi = DAG.getNode(ISD::SRL, NewVT, Elt,
DAG.getConstant(MVT::getSizeInBits(OldVT),
DAG.getConstant(OldVT.getSizeInBits(),
TLI.getShiftAmountTy()));
if (TLI.isBigEndian())
std::swap(Lo, Hi);
@ -513,7 +513,7 @@ SDOperand DAGTypeLegalizer::PromoteOperand_FP_ROUND(SDNode *N) {
SDOperand DAGTypeLegalizer::PromoteOperand_INT_TO_FP(SDNode *N) {
SDOperand In = GetPromotedOp(N->getOperand(0));
MVT::ValueType OpVT = N->getOperand(0).getValueType();
MVT OpVT = N->getOperand(0).getValueType();
if (N->getOpcode() == ISD::UINT_TO_FP)
In = DAG.getZeroExtendInReg(In, OpVT);
else
@ -525,14 +525,14 @@ SDOperand DAGTypeLegalizer::PromoteOperand_INT_TO_FP(SDNode *N) {
SDOperand DAGTypeLegalizer::PromoteOperand_BUILD_PAIR(SDNode *N) {
// Since the result type is legal, the operands must promote to it.
MVT::ValueType OVT = N->getOperand(0).getValueType();
MVT OVT = N->getOperand(0).getValueType();
SDOperand Lo = GetPromotedOp(N->getOperand(0));
SDOperand Hi = GetPromotedOp(N->getOperand(1));
assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
Lo = DAG.getZeroExtendInReg(Lo, OVT);
Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi,
DAG.getConstant(MVT::getSizeInBits(OVT),
DAG.getConstant(OVT.getSizeInBits(),
TLI.getShiftAmountTy()));
return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi);
}
@ -597,14 +597,14 @@ SDOperand DAGTypeLegalizer::PromoteOperand_SETCC(SDNode *N, unsigned OpNo) {
/// shared among BR_CC, SELECT_CC, and SETCC handlers.
void DAGTypeLegalizer::PromoteSetCCOperands(SDOperand &NewLHS,SDOperand &NewRHS,
ISD::CondCode CCCode) {
MVT::ValueType VT = NewLHS.getValueType();
MVT VT = NewLHS.getValueType();
// Get the promoted values.
NewLHS = GetPromotedOp(NewLHS);
NewRHS = GetPromotedOp(NewRHS);
// If this is an FP compare, the operands have already been extended.
if (!MVT::isInteger(NewLHS.getValueType()))
if (!NewLHS.getValueType().isInteger())
return;
// Otherwise, we have to insert explicit sign or zero extends. Note
@ -658,15 +658,15 @@ SDOperand DAGTypeLegalizer::PromoteOperand_BUILD_VECTOR(SDNode *N) {
// The vector type is legal but the element type is not. This implies
// that the vector is a power-of-two in length and that the element
// type does not have a strange size (eg: it is not i1).
MVT::ValueType VecVT = N->getValueType(0);
unsigned NumElts = MVT::getVectorNumElements(VecVT);
MVT VecVT = N->getValueType(0);
unsigned NumElts = VecVT.getVectorNumElements();
assert(!(NumElts & 1) && "Legal vector of one illegal element?");
// Build a vector of half the length out of elements of twice the bitwidth.
// For example <4 x i16> -> <2 x i32>.
MVT::ValueType OldVT = N->getOperand(0).getValueType();
MVT::ValueType NewVT = MVT::getIntegerType(2 * MVT::getSizeInBits(OldVT));
assert(!MVT::isExtendedVT(OldVT) && !MVT::isExtendedVT(NewVT));
MVT OldVT = N->getOperand(0).getValueType();
MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
assert(OldVT.isSimple() && NewVT.isSimple());
std::vector<SDOperand> NewElts;
NewElts.reserve(NumElts/2);
@ -681,7 +681,7 @@ SDOperand DAGTypeLegalizer::PromoteOperand_BUILD_VECTOR(SDNode *N) {
}
SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR,
MVT::getVectorType(NewVT, NewElts.size()),
MVT::getVectorVT(NewVT, NewElts.size()),
&NewElts[0], NewElts.size());
// Convert the new vector to the old vector type.
@ -695,8 +695,8 @@ SDOperand DAGTypeLegalizer::PromoteOperand_INSERT_VECTOR_ELT(SDNode *N,
// have to match the vector element type.
// Check that any extra bits introduced will be truncated away.
assert(MVT::getSizeInBits(N->getOperand(1).getValueType()) >=
MVT::getSizeInBits(MVT::getVectorElementType(N->getValueType(0))) &&
assert(N->getOperand(1).getValueType().getSizeInBits() >=
N->getValueType(0).getVectorElementType().getSizeInBits() &&
"Type of inserted value narrower than vector element type!");
return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
GetPromotedOp(N->getOperand(1)),

10
lib/CodeGen/SelectionDAG/LegalizeTypesScalarize.cpp
View File

@ -89,12 +89,12 @@ void DAGTypeLegalizer::ScalarizeResult(SDNode *N, unsigned ResNo) {
}
SDOperand DAGTypeLegalizer::ScalarizeRes_UNDEF(SDNode *N) {
return DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(N->getValueType(0)));
return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType());
}
SDOperand DAGTypeLegalizer::ScalarizeRes_LOAD(LoadSDNode *N) {
// FIXME: Add support for indexed loads.
SDOperand Result = DAG.getLoad(MVT::getVectorElementType(N->getValueType(0)),
SDOperand Result = DAG.getLoad(N->getValueType(0).getVectorElementType(),
N->getChain(), N->getBasePtr(),
N->getSrcValue(), N->getSrcValueOffset(),
N->isVolatile(), N->getAlignment());
@ -125,8 +125,8 @@ SDOperand DAGTypeLegalizer::ScalarizeRes_INSERT_VECTOR_ELT(SDNode *N) {
// The value to insert may have a wider type than the vector element type,
// so be sure to truncate it to the element type if necessary.
SDOperand Op = N->getOperand(1);
MVT::ValueType EltVT = MVT::getVectorElementType(N->getValueType(0));
if (MVT::getSizeInBits(Op.getValueType()) > MVT::getSizeInBits(EltVT))
MVT EltVT = N->getValueType(0).getVectorElementType();
if (Op.getValueType().getSizeInBits() > EltVT.getSizeInBits())
Op = DAG.getNode(ISD::TRUNCATE, EltVT, Op);
assert(Op.getValueType() == EltVT && "Invalid type for inserted value!");
return Op;
@ -140,7 +140,7 @@ SDOperand DAGTypeLegalizer::ScalarizeRes_VECTOR_SHUFFLE(SDNode *N) {
}
SDOperand DAGTypeLegalizer::ScalarizeRes_BIT_CONVERT(SDNode *N) {
MVT::ValueType NewVT = MVT::getVectorElementType(N->getValueType(0));
MVT NewVT = N->getValueType(0).getVectorElementType();
return DAG.getNode(ISD::BIT_CONVERT, NewVT, N->getOperand(0));
}

71
lib/CodeGen/SelectionDAG/LegalizeTypesSplit.cpp
View File

@ -19,18 +19,17 @@ using namespace llvm;
/// GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a vector
/// type that needs to be split. This handles non-power of two vectors.
static void GetSplitDestVTs(MVT::ValueType InVT,
MVT::ValueType &Lo, MVT::ValueType &Hi) {
MVT::ValueType NewEltVT = MVT::getVectorElementType(InVT);
unsigned NumElements = MVT::getVectorNumElements(InVT);
static void GetSplitDestVTs(MVT InVT, MVT &Lo, MVT &Hi) {
MVT NewEltVT = InVT.getVectorElementType();
unsigned NumElements = InVT.getVectorNumElements();
if ((NumElements & (NumElements-1)) == 0) { // Simple power of two vector.
NumElements >>= 1;
Lo = Hi = MVT::getVectorType(NewEltVT, NumElements);
Lo = Hi = MVT::getVectorVT(NewEltVT, NumElements);
} else { // Non-power-of-two vectors.
unsigned NewNumElts_Lo = 1 << Log2_32(NumElements);
unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
}
}
@ -117,7 +116,7 @@ void DAGTypeLegalizer::SplitResult(SDNode *N, unsigned ResNo) {
}
void DAGTypeLegalizer::SplitRes_UNDEF(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
MVT::ValueType LoVT, HiVT;
MVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
Lo = DAG.getNode(ISD::UNDEF, LoVT);
@ -127,7 +126,7 @@ void DAGTypeLegalizer::SplitRes_UNDEF(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
void DAGTypeLegalizer::SplitRes_LOAD(LoadSDNode *LD,
SDOperand &Lo, SDOperand &Hi) {
// FIXME: Add support for indexed loads.
MVT::ValueType LoVT, HiVT;
MVT LoVT, HiVT;
GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
SDOperand Ch = LD->getChain();
@ -138,7 +137,7 @@ void DAGTypeLegalizer::SplitRes_LOAD(LoadSDNode *LD,
bool isVolatile = LD->isVolatile();
Lo = DAG.getLoad(LoVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
unsigned IncrementSize = MVT::getSizeInBits(LoVT)/8;
unsigned IncrementSize = LoVT.getSizeInBits()/8;
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
DAG.getIntPtrConstant(IncrementSize));
SVOffset += IncrementSize;
@ -166,7 +165,7 @@ void DAGTypeLegalizer::SplitRes_INSERT_VECTOR_ELT(SDNode *N, SDOperand &Lo,
GetSplitOp(N->getOperand(0), Lo, Hi);
unsigned Index = cast<ConstantSDNode>(N->getOperand(2))->getValue();
SDOperand ScalarOp = N->getOperand(1);
unsigned LoNumElts = MVT::getVectorNumElements(Lo.getValueType());
unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
if (Index < LoNumElts)
Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, Lo.getValueType(), Lo, ScalarOp,
N->getOperand(2));
@ -180,10 +179,10 @@ void DAGTypeLegalizer::SplitRes_VECTOR_SHUFFLE(SDNode *N,
// Build the low part.
SDOperand Mask = N->getOperand(2);
SmallVector<SDOperand, 16> Ops;
MVT::ValueType LoVT, HiVT;
MVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
MVT::ValueType EltVT = MVT::getVectorElementType(LoVT);
unsigned LoNumElts = MVT::getVectorNumElements(LoVT);
MVT EltVT = LoVT.getVectorElementType();
unsigned LoNumElts = LoVT.getVectorNumElements();
unsigned NumElements = Mask.getNumOperands();
// Insert all of the elements from the input that are needed. We use
@ -217,9 +216,9 @@ void DAGTypeLegalizer::SplitRes_VECTOR_SHUFFLE(SDNode *N,
void DAGTypeLegalizer::SplitRes_BUILD_VECTOR(SDNode *N, SDOperand &Lo,
SDOperand &Hi) {
MVT::ValueType LoVT, HiVT;
MVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
unsigned LoNumElts = MVT::getVectorNumElements(LoVT);
unsigned LoNumElts = LoVT.getVectorNumElements();
SmallVector<SDOperand, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size());
@ -237,7 +236,7 @@ void DAGTypeLegalizer::SplitRes_CONCAT_VECTORS(SDNode *N,
return;
}
MVT::ValueType LoVT, HiVT;
MVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
SmallVector<SDOperand, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
@ -251,11 +250,11 @@ void DAGTypeLegalizer::SplitRes_BIT_CONVERT(SDNode *N,
SDOperand &Lo, SDOperand &Hi) {
// We know the result is a vector. The input may be either a vector or a
// scalar value.
MVT::ValueType LoVT, HiVT;
MVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
SDOperand InOp = N->getOperand(0);
MVT::ValueType InVT = InOp.getValueType();
MVT InVT = InOp.getValueType();
// Handle some special cases efficiently.
switch (getTypeAction(InVT)) {
@ -289,8 +288,8 @@ void DAGTypeLegalizer::SplitRes_BIT_CONVERT(SDNode *N,
}
// In the general case, convert the input to an integer and split it by hand.
MVT::ValueType LoIntVT = MVT::getIntegerType(MVT::getSizeInBits(LoVT));
MVT::ValueType HiIntVT = MVT::getIntegerType(MVT::getSizeInBits(HiVT));
MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits());
MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits());
if (TLI.isBigEndian())
std::swap(LoIntVT, HiIntVT);
@ -314,7 +313,7 @@ void DAGTypeLegalizer::SplitRes_BinOp(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
void DAGTypeLegalizer::SplitRes_UnOp(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
// Get the dest types. This doesn't always match input types, e.g. int_to_fp.
MVT::ValueType LoVT, HiVT;
MVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
GetSplitOp(N->getOperand(0), Lo, Hi);
@ -410,7 +409,7 @@ SDOperand DAGTypeLegalizer::SplitOp_STORE(StoreSDNode *N, unsigned OpNo) {
SDOperand Lo, Hi;
GetSplitOp(N->getOperand(1), Lo, Hi);
unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, isVol, Alignment);
@ -455,17 +454,16 @@ SDOperand DAGTypeLegalizer::SplitOp_BIT_CONVERT(SDNode *N) {
SDOperand DAGTypeLegalizer::SplitOp_EXTRACT_VECTOR_ELT(SDNode *N) {
SDOperand Vec = N->getOperand(0);
SDOperand Idx = N->getOperand(1);
MVT::ValueType VecVT = Vec.getValueType();
MVT VecVT = Vec.getValueType();
if (isa<ConstantSDNode>(Idx)) {
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue();
assert(IdxVal < MVT::getVectorNumElements(VecVT) &&
"Invalid vector index!");
assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
SDOperand Lo, Hi;
GetSplitOp(Vec, Lo, Hi);
uint64_t LoElts = MVT::getVectorNumElements(Lo.getValueType());
uint64_t LoElts = Lo.getValueType().getVectorNumElements();
if (IdxVal < LoElts)
return DAG.UpdateNodeOperands(SDOperand(N, 0), Lo, Idx);
@ -480,13 +478,12 @@ SDOperand DAGTypeLegalizer::SplitOp_EXTRACT_VECTOR_ELT(SDNode *N) {
SDOperand Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
// Add the offset to the index.
MVT::ValueType EltVT = MVT::getVectorElementType(VecVT);
unsigned EltSize = MVT::getSizeInBits(EltVT)/8; // FIXME: should be ABI size.
MVT EltVT = VecVT.getVectorElementType();
unsigned EltSize = EltVT.getSizeInBits()/8; // FIXME: should be ABI size.
Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
DAG.getConstant(EltSize, Idx.getValueType()));
if (MVT::getSizeInBits(Idx.getValueType()) >
MVT::getSizeInBits(TLI.getPointerTy()))
if (Idx.getValueType().getSizeInBits() > TLI.getPointerTy().getSizeInBits())
Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
else
Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
@ -498,16 +495,16 @@ SDOperand DAGTypeLegalizer::SplitOp_EXTRACT_VECTOR_ELT(SDNode *N) {
SDOperand DAGTypeLegalizer::SplitOp_EXTRACT_SUBVECTOR(SDNode *N) {
// We know that the extracted result type is legal. For now, assume the index
// is a constant.
MVT::ValueType SubVT = N->getValueType(0);
MVT SubVT = N->getValueType(0);
SDOperand Idx = N->getOperand(1);
SDOperand Lo, Hi;
GetSplitOp(N->getOperand(0), Lo, Hi);
uint64_t LoElts = MVT::getVectorNumElements(Lo.getValueType());
uint64_t LoElts = Lo.getValueType().getVectorNumElements();
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue();
if (IdxVal < LoElts) {
assert(IdxVal + MVT::getVectorNumElements(SubVT) <= LoElts &&
assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
"Extracted subvector crosses vector split!");
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Lo, Idx);
} else {
@ -519,7 +516,7 @@ SDOperand DAGTypeLegalizer::SplitOp_EXTRACT_SUBVECTOR(SDNode *N) {
SDOperand DAGTypeLegalizer::SplitOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo) {
assert(OpNo == 2 && "Shuffle source type differs from result type?");
SDOperand Mask = N->getOperand(2);
unsigned MaskLength = MVT::getVectorNumElements(Mask.getValueType());
unsigned MaskLength = Mask.getValueType().getVectorNumElements();
unsigned LargestMaskEntryPlusOne = 2 * MaskLength;
unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne);
@ -532,12 +529,12 @@ SDOperand DAGTypeLegalizer::SplitOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo) {
EltVT = MVT::SimpleValueType(EltVT + 1)) {
// Is the element type big enough to hold the values?
if (MVT::getSizeInBits(EltVT) < MinimumBitWidth)
if (MVT(EltVT).getSizeInBits() < MinimumBitWidth)
// Nope.
continue;
// Is the vector type legal?
MVT::ValueType VecVT = MVT::getVectorType(EltVT, MaskLength);
MVT VecVT = MVT::getVectorVT(EltVT, MaskLength);
if (!isTypeLegal(VecVT))
// Nope.
continue;

6
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
View File

@ -191,7 +191,7 @@ void ScheduleDAG::BuildSchedUnits() {
assert(OpSU && "Node has no SUnit!");
if (OpSU == SU) continue; // In the same group.
MVT::ValueType OpVT = N->getOperand(i).getValueType();
MVT OpVT = N->getOperand(i).getValueType();
assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
bool isChain = OpVT == MVT::Other;
@ -433,7 +433,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
SDOperand Op = Use->getOperand(i);
if (Op.Val != Node || Op.ResNo != ResNo)
continue;
MVT::ValueType VT = Node->getValueType(Op.ResNo);
MVT VT = Node->getValueType(Op.ResNo);
if (VT != MVT::Other && VT != MVT::Flag)
Match = false;
}
@ -677,7 +677,7 @@ static const TargetRegisterClass *getSubRegisterRegClass(
static const TargetRegisterClass *getSuperregRegisterClass(
const TargetRegisterClass *TRC,
unsigned SubIdx,
MVT::ValueType VT) {
MVT VT) {
// Pick the register class of the superegister for this type
for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
E = TRC->superregclasses_end(); I != E; ++I)

12
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
View File

@ -646,7 +646,7 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
SUnit *NewSU;
bool TryUnfold = false;
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
MVT::ValueType VT = N->getValueType(i);
MVT VT = N->getValueType(i);
if (VT == MVT::Flag)
return NULL;
else if (VT == MVT::Other)
@ -654,7 +654,7 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
}
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
const SDOperand &Op = N->getOperand(i);
MVT::ValueType VT = Op.Val->getValueType(Op.ResNo);
MVT VT = Op.Val->getValueType(Op.ResNo);
if (VT == MVT::Flag)
return NULL;
}
@ -872,8 +872,8 @@ void ScheduleDAGRRList::InsertCCCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
/// getPhysicalRegisterVT - Returns the ValueType of the physical register
/// definition of the specified node.
/// FIXME: Move to SelectionDAG?
static MVT::ValueType getPhysicalRegisterVT(SDNode *N, unsigned Reg,
const TargetInstrInfo *TII) {
static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
const TargetInstrInfo *TII) {
const TargetInstrDesc &TID = TII->get(N->getTargetOpcode());
assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
unsigned NumRes = TID.getNumDefs();
@ -1022,7 +1022,7 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
SUnit *NewDef = CopyAndMoveSuccessors(LRDef);
if (!NewDef) {
// Issue expensive cross register class copies.
MVT::ValueType VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII);
MVT VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII);
const TargetRegisterClass *RC =
TRI->getPhysicalRegisterRegClass(Reg, VT);
const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
@ -1599,7 +1599,7 @@ static bool canClobberPhysRegDefs(SUnit *SuccSU, SUnit *SU,
if (!SUImpDefs)
return false;
for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
MVT::ValueType VT = N->getValueType(i);
MVT VT = N->getValueType(i);
if (VT == MVT::Flag || VT == MVT::Other)
continue;
unsigned Reg = ImpDefs[i - NumDefs];

534
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

File diff suppressed because it is too large Load Diff

290
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -88,10 +88,10 @@ defaultListDAGScheduler("default", " Best scheduler for the target",
namespace { struct SDISelAsmOperandInfo; }
/// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
/// MVT::ValueTypes that represent all the individual underlying
/// MVTs that represent all the individual underlying
/// non-aggregate types that comprise it.
static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
SmallVectorImpl<MVT::ValueType> &ValueVTs) {
SmallVectorImpl<MVT> &ValueVTs) {
// Given a struct type, recursively traverse the elements.
if (const StructType *STy = dyn_cast<StructType>(Ty)) {
for (StructType::element_iterator EI = STy->element_begin(),
@ -107,7 +107,7 @@ static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
ComputeValueVTs(TLI, EltTy, ValueVTs);
return;
}
// Base case: we can get an MVT::ValueType for this LLVM IR type.
// Base case: we can get an MVT for this LLVM IR type.
ValueVTs.push_back(TLI.getValueType(Ty));
}
@ -129,7 +129,7 @@ namespace {
/// ValueVTs - The value types of the values, which may not be legal, and
/// may need be promoted or synthesized from one or more registers.
///
SmallVector<MVT::ValueType, 4> ValueVTs;
SmallVector<MVT, 4> ValueVTs;
/// RegVTs - The value types of the registers. This is the same size as
/// ValueVTs and it records, for each value, what the type of the assigned
@ -140,7 +140,7 @@ namespace {
/// getRegisterType member function, however when with physical registers
/// it is necessary to have a separate record of the types.
///
SmallVector<MVT::ValueType, 4> RegVTs;
SmallVector<MVT, 4> RegVTs;
/// Regs - This list holds the registers assigned to the values.
/// Each legal or promoted value requires one register, and each
@ -152,21 +152,21 @@ namespace {
RegsForValue(const TargetLowering &tli,
const SmallVector<unsigned, 4> &regs,
MVT::ValueType regvt, MVT::ValueType valuevt)
MVT regvt, MVT valuevt)
: TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
RegsForValue(const TargetLowering &tli,
const SmallVector<unsigned, 4> &regs,
const SmallVector<MVT::ValueType, 4> &regvts,
const SmallVector<MVT::ValueType, 4> &valuevts)
const SmallVector<MVT, 4> &regvts,
const SmallVector<MVT, 4> &valuevts)
: TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
RegsForValue(const TargetLowering &tli,
unsigned Reg, const Type *Ty) : TLI(&tli) {
ComputeValueVTs(tli, Ty, ValueVTs);
for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
MVT::ValueType ValueVT = ValueVTs[Value];
MVT ValueVT = ValueVTs[Value];
unsigned NumRegs = TLI->getNumRegisters(ValueVT);
MVT::ValueType RegisterVT = TLI->getRegisterType(ValueVT);
MVT RegisterVT = TLI->getRegisterType(ValueVT);
for (unsigned i = 0; i != NumRegs; ++i)
Regs.push_back(Reg + i);
RegVTs.push_back(RegisterVT);
@ -254,7 +254,7 @@ namespace llvm {
SmallSet<Instruction*, 8> CatchInfoFound;
#endif
unsigned MakeReg(MVT::ValueType VT) {
unsigned MakeReg(MVT VT) {
return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
}
@ -359,7 +359,7 @@ FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
if (PN->use_empty()) continue;
MVT::ValueType VT = TLI.getValueType(PN->getType());
MVT VT = TLI.getValueType(PN->getType());
unsigned NumRegisters = TLI.getNumRegisters(VT);
unsigned PHIReg = ValueMap[PN];
assert(PHIReg && "PHI node does not have an assigned virtual register!");
@ -378,13 +378,13 @@ FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
/// will assign registers for each member or element.
///
unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
SmallVector<MVT::ValueType, 4> ValueVTs;
SmallVector<MVT, 4> ValueVTs;
ComputeValueVTs(TLI, V->getType(), ValueVTs);
unsigned FirstReg = 0;
for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
MVT::ValueType ValueVT = ValueVTs[Value];
MVT::ValueType RegisterVT = TLI.getRegisterType(ValueVT);
MVT ValueVT = ValueVTs[Value];
MVT RegisterVT = TLI.getRegisterType(ValueVT);
unsigned NumRegs = TLI.getNumRegisters(ValueVT);
for (unsigned i = 0; i != NumRegs; ++i) {
@ -751,8 +751,8 @@ private:
static SDOperand getCopyFromParts(SelectionDAG &DAG,
const SDOperand *Parts,
unsigned NumParts,
MVT::ValueType PartVT,
MVT::ValueType ValueVT,
MVT PartVT,
MVT ValueVT,
ISD::NodeType AssertOp = ISD::DELETED_NODE) {
assert(NumParts > 0 && "No parts to assemble!");
TargetLowering &TLI = DAG.getTargetLoweringInfo();
@ -760,20 +760,20 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG,
if (NumParts > 1) {
// Assemble the value from multiple parts.
if (!MVT::isVector(ValueVT)) {
unsigned PartBits = MVT::getSizeInBits(PartVT);
unsigned ValueBits = MVT::getSizeInBits(ValueVT);
if (!ValueVT.isVector()) {
unsigned PartBits = PartVT.getSizeInBits();
unsigned ValueBits = ValueVT.getSizeInBits();
// Assemble the power of 2 part.
unsigned RoundParts = NumParts & (NumParts - 1) ?
1 << Log2_32(NumParts) : NumParts;
unsigned RoundBits = PartBits * RoundParts;
MVT::ValueType RoundVT = RoundBits == ValueBits ?
ValueVT : MVT::getIntegerType(RoundBits);
MVT RoundVT = RoundBits == ValueBits ?
ValueVT : MVT::getIntegerVT(RoundBits);
SDOperand Lo, Hi;
if (RoundParts > 2) {
MVT::ValueType HalfVT = MVT::getIntegerType(RoundBits/2);
MVT HalfVT = MVT::getIntegerVT(RoundBits/2);
Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
PartVT, HalfVT);
@ -788,24 +788,24 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG,
if (RoundParts < NumParts) {
// Assemble the trailing non-power-of-2 part.
unsigned OddParts = NumParts - RoundParts;
MVT::ValueType OddVT = MVT::getIntegerType(OddParts * PartBits);
MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
// Combine the round and odd parts.
Lo = Val;
if (TLI.isBigEndian())
std::swap(Lo, Hi);
MVT::ValueType TotalVT = MVT::getIntegerType(NumParts * PartBits);
MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
DAG.getConstant(MVT::getSizeInBits(Lo.getValueType()),
DAG.getConstant(Lo.getValueType().getSizeInBits(),
TLI.getShiftAmountTy()));
Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
}
} else {
// Handle a multi-element vector.
MVT::ValueType IntermediateVT, RegisterVT;
MVT IntermediateVT, RegisterVT;
unsigned NumIntermediates;
unsigned NumRegs =
TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
@ -837,7 +837,7 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG,
// Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
// operands.
Val = DAG.getNode(MVT::isVector(IntermediateVT) ?
Val = DAG.getNode(IntermediateVT.isVector() ?
ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
ValueVT, &Ops[0], NumIntermediates);
}
@ -849,21 +849,21 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG,
if (PartVT == ValueVT)
return Val;
if (MVT::isVector(PartVT)) {
assert(MVT::isVector(ValueVT) && "Unknown vector conversion!");
if (PartVT.isVector()) {
assert(ValueVT.isVector() && "Unknown vector conversion!");
return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
}
if (MVT::isVector(ValueVT)) {
assert(MVT::getVectorElementType(ValueVT) == PartVT &&
MVT::getVectorNumElements(ValueVT) == 1 &&
if (ValueVT.isVector()) {
assert(ValueVT.getVectorElementType() == PartVT &&
ValueVT.getVectorNumElements() == 1 &&
"Only trivial scalar-to-vector conversions should get here!");
return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
}
if (MVT::isInteger(PartVT) &&
MVT::isInteger(ValueVT)) {
if (MVT::getSizeInBits(ValueVT) < MVT::getSizeInBits(PartVT)) {
if (PartVT.isInteger() &&
ValueVT.isInteger()) {
if (ValueVT.getSizeInBits() < PartVT.getSizeInBits()) {
// For a truncate, see if we have any information to
// indicate whether the truncated bits will always be
// zero or sign-extension.
@ -876,7 +876,7 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG,
}
}
if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) {
if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
if (ValueVT < Val.getValueType())
// FP_ROUND's are always exact here.
return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
@ -884,7 +884,7 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG,
return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
}
if (MVT::getSizeInBits(PartVT) == MVT::getSizeInBits(ValueVT))
if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
assert(0 && "Unknown mismatch!");
@ -898,43 +898,43 @@ static void getCopyToParts(SelectionDAG &DAG,
SDOperand Val,
SDOperand *Parts,
unsigned NumParts,
MVT::ValueType PartVT,
MVT PartVT,
ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
TargetLowering &TLI = DAG.getTargetLoweringInfo();
MVT::ValueType PtrVT = TLI.getPointerTy();
MVT::ValueType ValueVT = Val.getValueType();
unsigned PartBits = MVT::getSizeInBits(PartVT);
MVT PtrVT = TLI.getPointerTy();
MVT ValueVT = Val.getValueType();
unsigned PartBits = PartVT.getSizeInBits();
assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
if (!NumParts)
return;
if (!MVT::isVector(ValueVT)) {
if (!ValueVT.isVector()) {
if (PartVT == ValueVT) {
assert(NumParts == 1 && "No-op copy with multiple parts!");
Parts[0] = Val;
return;
}
if (NumParts * PartBits > MVT::getSizeInBits(ValueVT)) {
if (NumParts * PartBits > ValueVT.getSizeInBits()) {
// If the parts cover more bits than the value has, promote the value.
if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) {
if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
assert(NumParts == 1 && "Do not know what to promote to!");
Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
} else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
ValueVT = MVT::getIntegerType(NumParts * PartBits);
} else if (PartVT.isInteger() && ValueVT.isInteger()) {
ValueVT = MVT::getIntegerVT(NumParts * PartBits);
Val = DAG.getNode(ExtendKind, ValueVT, Val);
} else {
assert(0 && "Unknown mismatch!");
}
} else if (PartBits == MVT::getSizeInBits(ValueVT)) {
} else if (PartBits == ValueVT.getSizeInBits()) {
// Different types of the same size.
assert(NumParts == 1 && PartVT != ValueVT);
Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
} else if (NumParts * PartBits < MVT::getSizeInBits(ValueVT)) {
} else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
// If the parts cover less bits than value has, truncate the value.
if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
ValueVT = MVT::getIntegerType(NumParts * PartBits);
if (PartVT.isInteger() && ValueVT.isInteger()) {
ValueVT = MVT::getIntegerVT(NumParts * PartBits);
Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
} else {
assert(0 && "Unknown mismatch!");
@ -943,7 +943,7 @@ static void getCopyToParts(SelectionDAG &DAG,
// The value may have changed - recompute ValueVT.
ValueVT = Val.getValueType();
assert(NumParts * PartBits == MVT::getSizeInBits(ValueVT) &&
assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
"Failed to tile the value with PartVT!");
if (NumParts == 1) {
@ -955,7 +955,7 @@ static void getCopyToParts(SelectionDAG &DAG,
// Expand the value into multiple parts.
if (NumParts & (NumParts - 1)) {
// The number of parts is not a power of 2. Split off and copy the tail.
assert(MVT::isInteger(PartVT) && MVT::isInteger(ValueVT) &&
assert(PartVT.isInteger() && ValueVT.isInteger() &&
"Do not know what to expand to!");
unsigned RoundParts = 1 << Log2_32(NumParts);
unsigned RoundBits = RoundParts * PartBits;
@ -968,19 +968,19 @@ static void getCopyToParts(SelectionDAG &DAG,
// The odd parts were reversed by getCopyToParts - unreverse them.
std::reverse(Parts + RoundParts, Parts + NumParts);
NumParts = RoundParts;
ValueVT = MVT::getIntegerType(NumParts * PartBits);
ValueVT = MVT::getIntegerVT(NumParts * PartBits);
Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
}
// The number of parts is a power of 2. Repeatedly bisect the value using
// EXTRACT_ELEMENT.
Parts[0] = DAG.getNode(ISD::BIT_CONVERT,
MVT::getIntegerType(MVT::getSizeInBits(ValueVT)),
MVT::getIntegerVT(ValueVT.getSizeInBits()),
Val);
for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
for (unsigned i = 0; i < NumParts; i += StepSize) {
unsigned ThisBits = StepSize * PartBits / 2;
MVT::ValueType ThisVT = MVT::getIntegerType (ThisBits);
MVT ThisVT = MVT::getIntegerVT (ThisBits);
SDOperand &Part0 = Parts[i];
SDOperand &Part1 = Parts[i+StepSize/2];
@ -1005,11 +1005,11 @@ static void getCopyToParts(SelectionDAG &DAG,
// Vector ValueVT.
if (NumParts == 1) {
if (PartVT != ValueVT) {
if (MVT::isVector(PartVT)) {
if (PartVT.isVector()) {
Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
} else {
assert(MVT::getVectorElementType(ValueVT) == PartVT &&
MVT::getVectorNumElements(ValueVT) == 1 &&
assert(ValueVT.getVectorElementType() == PartVT &&
ValueVT.getVectorNumElements() == 1 &&
"Only trivial vector-to-scalar conversions should get here!");
Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
DAG.getConstant(0, PtrVT));
@ -1021,13 +1021,13 @@ static void getCopyToParts(SelectionDAG &DAG,
}
// Handle a multi-element vector.
MVT::ValueType IntermediateVT, RegisterVT;
MVT IntermediateVT, RegisterVT;
unsigned NumIntermediates;
unsigned NumRegs =
DAG.getTargetLoweringInfo()
.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
RegisterVT);
unsigned NumElements = MVT::getVectorNumElements(ValueVT);
unsigned NumElements = ValueVT.getVectorNumElements();
assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
NumParts = NumRegs; // Silence a compiler warning.
@ -1036,7 +1036,7 @@ static void getCopyToParts(SelectionDAG &DAG,
// Split the vector into intermediate operands.
SmallVector<SDOperand, 8> Ops(NumIntermediates);
for (unsigned i = 0; i != NumIntermediates; ++i)
if (MVT::isVector(IntermediateVT))
if (IntermediateVT.isVector())
Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
IntermediateVT, Val,
DAG.getConstant(i * (NumElements / NumIntermediates),
@ -1069,7 +1069,7 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) {
if (N.Val) return N;
if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
MVT::ValueType VT = TLI.getValueType(V->getType(), true);
MVT VT = TLI.getValueType(V->getType(), true);
if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
return N = DAG.getConstant(CI->getValue(), VT);
@ -1105,12 +1105,12 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) {
} else {
assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
"Unknown vector constant!");
MVT::ValueType EltVT = TLI.getValueType(VecTy->getElementType());
MVT EltVT = TLI.getValueType(VecTy->getElementType());
SDOperand Op;
if (isa<UndefValue>(C))
Op = DAG.getNode(ISD::UNDEF, EltVT);
else if (MVT::isFloatingPoint(EltVT))
else if (EltVT.isFloatingPoint())
Op = DAG.getConstantFP(0, EltVT);
else
Op = DAG.getConstant(0, EltVT);
@ -1149,18 +1149,18 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) {
NewValues.push_back(getControlRoot());
for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
SDOperand RetOp = getValue(I.getOperand(i));
MVT::ValueType VT = RetOp.getValueType();
MVT VT = RetOp.getValueType();
// FIXME: C calling convention requires the return type to be promoted to
// at least 32-bit. But this is not necessary for non-C calling conventions.
if (MVT::isInteger(VT)) {
MVT::ValueType MinVT = TLI.getRegisterType(MVT::i32);
if (MVT::getSizeInBits(VT) < MVT::getSizeInBits(MinVT))
if (VT.isInteger()) {
MVT MinVT = TLI.getRegisterType(MVT::i32);
if (VT.getSizeInBits() < MinVT.getSizeInBits())
VT = MinVT;
}
unsigned NumParts = TLI.getNumRegisters(VT);
MVT::ValueType PartVT = TLI.getRegisterType(VT);
MVT PartVT = TLI.getRegisterType(VT);
SmallVector<SDOperand, 4> Parts(NumParts);
ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
@ -1475,7 +1475,7 @@ void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
SDOperand CmpOp = getValue(CB.CmpMHS);
MVT::ValueType VT = CmpOp.getValueType();
MVT VT = CmpOp.getValueType();
if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
@ -1517,7 +1517,7 @@ void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
// Emit the code for the jump table
assert(JT.Reg != -1U && "Should lower JT Header first!");
MVT::ValueType PTy = TLI.getPointerTy();
MVT PTy = TLI.getPointerTy();
SDOperand Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
@ -1533,7 +1533,7 @@ void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
// and conditional branch to default mbb if the result is greater than the
// difference between smallest and largest cases.
SDOperand SwitchOp = getValue(JTH.SValue);
MVT::ValueType VT = SwitchOp.getValueType();
MVT VT = SwitchOp.getValueType();
SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
DAG.getConstant(JTH.First, VT));
@ -1542,7 +1542,7 @@ void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
// register so it can be used as an index into the jump table in a
// subsequent basic block. This value may be smaller or larger than the
// target's pointer type, and therefore require extension or truncating.
if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
if (VT.getSizeInBits() > TLI.getPointerTy().getSizeInBits())
SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
else
SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
@ -1582,7 +1582,7 @@ void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
// Subtract the minimum value
SDOperand SwitchOp = getValue(B.SValue);
MVT::ValueType VT = SwitchOp.getValueType();
MVT VT = SwitchOp.getValueType();
SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
DAG.getConstant(B.First, VT));
@ -1592,7 +1592,7 @@ void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B)
ISD::SETUGT);
SDOperand ShiftOp;
if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy()))
if (VT.getSizeInBits() > TLI.getShiftAmountTy().getSizeInBits())
ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
else
ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
@ -2005,7 +2005,7 @@ bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
CaseRecVector& WorkList,
Value* SV,
MachineBasicBlock* Default){
unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy());
unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
Case& FrontCase = *CR.Range.first;
Case& BackCase = *(CR.Range.second-1);
@ -2271,8 +2271,8 @@ void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
SDOperand Op1 = getValue(I.getOperand(0));
SDOperand Op2 = getValue(I.getOperand(1));
if (MVT::getSizeInBits(TLI.getShiftAmountTy()) <
MVT::getSizeInBits(Op2.getValueType()))
if (TLI.getShiftAmountTy().getSizeInBits() <
Op2.getValueType().getSizeInBits())
Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
else if (TLI.getShiftAmountTy() > Op2.getValueType())
Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
@ -2410,7 +2410,7 @@ void SelectionDAGLowering::visitVFCmp(User &I) {
else
Condition = FPC;
MVT::ValueType DestVT = TLI.getValueType(I.getType());
MVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
}
@ -2427,7 +2427,7 @@ void SelectionDAGLowering::visitSelect(User &I) {
void SelectionDAGLowering::visitTrunc(User &I) {
// TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
SDOperand N = getValue(I.getOperand(0));
MVT::ValueType DestVT = TLI.getValueType(I.getType());
MVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
}
@ -2435,7 +2435,7 @@ void SelectionDAGLowering::visitZExt(User &I) {
// ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
// ZExt also can't be a cast to bool for same reason. So, nothing much to do
SDOperand N = getValue(I.getOperand(0));
MVT::ValueType DestVT = TLI.getValueType(I.getType());
MVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
}
@ -2443,49 +2443,49 @@ void SelectionDAGLowering::visitSExt(User &I) {
// SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
// SExt also can't be a cast to bool for same reason. So, nothing much to do
SDOperand N = getValue(I.getOperand(0));
MVT::ValueType DestVT = TLI.getValueType(I.getType());
MVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
}
void SelectionDAGLowering::visitFPTrunc(User &I) {
// FPTrunc is never a no-op cast, no need to check
SDOperand N = getValue(I.getOperand(0));
MVT::ValueType DestVT = TLI.getValueType(I.getType());
MVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
}
void SelectionDAGLowering::visitFPExt(User &I){
// FPTrunc is never a no-op cast, no need to check
SDOperand N = getValue(I.getOperand(0));
MVT::ValueType DestVT = TLI.getValueType(I.getType());
MVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
}
void SelectionDAGLowering::visitFPToUI(User &I) {
// FPToUI is never a no-op cast, no need to check
SDOperand N = getValue(I.getOperand(0));
MVT::ValueType DestVT = TLI.getValueType(I.getType());
MVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
}
void SelectionDAGLowering::visitFPToSI(User &I) {
// FPToSI is never a no-op cast, no need to check
SDOperand N = getValue(I.getOperand(0));
MVT::ValueType DestVT = TLI.getValueType(I.getType());
MVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
}
void SelectionDAGLowering::visitUIToFP(User &I) {
// UIToFP is never a no-op cast, no need to check
SDOperand N = getValue(I.getOperand(0));
MVT::ValueType DestVT = TLI.getValueType(I.getType());
MVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
}
void SelectionDAGLowering::visitSIToFP(User &I){
// UIToFP is never a no-op cast, no need to check
SDOperand N = getValue(I.getOperand(0));
MVT::ValueType DestVT = TLI.getValueType(I.getType());
MVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
}
@ -2493,10 +2493,10 @@ void SelectionDAGLowering::visitPtrToInt(User &I) {
// What to do depends on the size of the integer and the size of the pointer.
// We can either truncate, zero extend, or no-op, accordingly.
SDOperand N = getValue(I.getOperand(0));
MVT::ValueType SrcVT = N.getValueType();
MVT::ValueType DestVT = TLI.getValueType(I.getType());
MVT SrcVT = N.getValueType();
MVT DestVT = TLI.getValueType(I.getType());
SDOperand Result;
if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
if (DestVT.getSizeInBits() < SrcVT.getSizeInBits())
Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
else
// Note: ZERO_EXTEND can handle cases where the sizes are equal too
@ -2508,9 +2508,9 @@ void SelectionDAGLowering::visitIntToPtr(User &I) {
// What to do depends on the size of the integer and the size of the pointer.
// We can either truncate, zero extend, or no-op, accordingly.
SDOperand N = getValue(I.getOperand(0));
MVT::ValueType SrcVT = N.getValueType();
MVT::ValueType DestVT = TLI.getValueType(I.getType());
if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
MVT SrcVT = N.getValueType();
MVT DestVT = TLI.getValueType(I.getType());
if (DestVT.getSizeInBits() < SrcVT.getSizeInBits())
setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
else
// Note: ZERO_EXTEND can handle cases where the sizes are equal too
@ -2519,7 +2519,7 @@ void SelectionDAGLowering::visitIntToPtr(User &I) {
void SelectionDAGLowering::visitBitCast(User &I) {
SDOperand N = getValue(I.getOperand(0));
MVT::ValueType DestVT = TLI.getValueType(I.getType());
MVT DestVT = TLI.getValueType(I.getType());
// BitCast assures us that source and destination are the same size so this
// is either a BIT_CONVERT or a no-op.
@ -2640,7 +2640,7 @@ void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
I.getAlignment());
SDOperand AllocSize = getValue(I.getArraySize());
MVT::ValueType IntPtr = TLI.getPointerTy();
MVT IntPtr = TLI.getPointerTy();
if (IntPtr < AllocSize.getValueType())
AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
else if (IntPtr > AllocSize.getValueType())
@ -2666,7 +2666,7 @@ void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
MVT::Other);
SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
setValue(&I, DSA);
@ -2746,14 +2746,14 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
Ops.push_back(Op);
}
std::vector<MVT::ValueType> VTs;
std::vector<MVT> VTs;
if (I.getType() != Type::VoidTy) {
MVT::ValueType VT = TLI.getValueType(I.getType());
if (MVT::isVector(VT)) {
MVT VT = TLI.getValueType(I.getType());
if (VT.isVector()) {
const VectorType *DestTy = cast<VectorType>(I.getType());
MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
MVT EltVT = TLI.getValueType(DestTy->getElementType());
VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
}
@ -2763,7 +2763,7 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
if (HasChain)
VTs.push_back(MVT::Other);
const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
const MVT *VTList = DAG.getNodeValueTypes(VTs);
// Create the node.
SDOperand Result;
@ -2786,7 +2786,7 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
}
if (I.getType() != Type::VoidTy) {
if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
MVT::ValueType VT = TLI.getValueType(PTy);
MVT VT = TLI.getValueType(PTy);
Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
}
setValue(&I, Result);
@ -3038,7 +3038,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
case Intrinsic::eh_selector_i32:
case Intrinsic::eh_selector_i64: {
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
MVT::i32 : MVT::i64);
if (MMI) {
@ -3071,7 +3071,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
case Intrinsic::eh_typeid_for_i32:
case Intrinsic::eh_typeid_for_i64: {
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
MVT::i32 : MVT::i64);
if (MMI) {
@ -3114,9 +3114,9 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
}
case Intrinsic::eh_dwarf_cfa: {
MVT::ValueType VT = getValue(I.getOperand(1)).getValueType();
MVT VT = getValue(I.getOperand(1)).getValueType();
SDOperand CfaArg;
if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
if (VT.getSizeInBits() > TLI.getPointerTy().getSizeInBits())
CfaArg = DAG.getNode(ISD::TRUNCATE,
TLI.getPointerTy(), getValue(I.getOperand(1)));
else
@ -3196,21 +3196,21 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
return 0;
case Intrinsic::cttz: {
SDOperand Arg = getValue(I.getOperand(1));
MVT::ValueType Ty = Arg.getValueType();
MVT Ty = Arg.getValueType();
SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
setValue(&I, result);
return 0;
}
case Intrinsic::ctlz: {
SDOperand Arg = getValue(I.getOperand(1));
MVT::ValueType Ty = Arg.getValueType();
MVT Ty = Arg.getValueType();
SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
setValue(&I, result);
return 0;
}
case Intrinsic::ctpop: {
SDOperand Arg = getValue(I.getOperand(1));
MVT::ValueType Ty = Arg.getValueType();
MVT Ty = Arg.getValueType();
SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
setValue(&I, result);
return 0;
@ -3503,9 +3503,9 @@ SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
SmallVector<SDOperand, 8> Parts;
for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
// Copy the legal parts from the registers.
MVT::ValueType ValueVT = ValueVTs[Value];
MVT ValueVT = ValueVTs[Value];
unsigned NumRegs = TLI->getNumRegisters(ValueVT);
MVT::ValueType RegisterVT = RegVTs[Value];
MVT RegisterVT = RegVTs[Value];
Parts.resize(NumRegs);
for (unsigned i = 0; i != NumRegs; ++i) {
@ -3543,9 +3543,9 @@ void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
unsigned NumRegs = Regs.size();
SmallVector<SDOperand, 8> Parts(NumRegs);
for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
MVT::ValueType ValueVT = ValueVTs[Value];
MVT ValueVT = ValueVTs[Value];
unsigned NumParts = TLI->getNumRegisters(ValueVT);
MVT::ValueType RegisterVT = RegVTs[Value];
MVT RegisterVT = RegVTs[Value];
getCopyToParts(DAG, Val.getValue(Val.ResNo + Value),
&Parts[Part], NumParts, RegisterVT);
@ -3586,11 +3586,11 @@ void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
/// values added into it.
void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
std::vector<SDOperand> &Ops) const {
MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
MVT::ValueType RegisterVT = RegVTs[Value];
MVT RegisterVT = RegVTs[Value];
for (unsigned i = 0; i != NumRegs; ++i)
Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
}
@ -3603,11 +3603,11 @@ static const TargetRegisterClass *
isAllocatableRegister(unsigned Reg, MachineFunction &MF,
const TargetLowering &TLI,
const TargetRegisterInfo *TRI) {
MVT::ValueType FoundVT = MVT::Other;
MVT FoundVT = MVT::Other;
const TargetRegisterClass *FoundRC = 0;
for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
E = TRI->regclass_end(); RCI != E; ++RCI) {
MVT::ValueType ThisVT = MVT::Other;
MVT ThisVT = MVT::Other;
const TargetRegisterClass *RC = *RCI;
// If none of the the value types for this register class are valid, we
@ -3619,7 +3619,7 @@ isAllocatableRegister(unsigned Reg, MachineFunction &MF,
// choose the one with the largest VT specified. For example, on
// PowerPC, we favor f64 register classes over f32.
if (FoundVT == MVT::Other ||
MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
FoundVT.getSizeInBits() < (*I).getSizeInBits()) {
ThisVT = *I;
break;
}
@ -3745,8 +3745,8 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
unsigned NumRegs = 1;
if (OpInfo.ConstraintVT != MVT::Other)
NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
MVT::ValueType RegVT;
MVT::ValueType ValueVT = OpInfo.ConstraintVT;
MVT RegVT;
MVT ValueVT = OpInfo.ConstraintVT;
// If this is a constraint for a specific physical register, like {r17},
@ -3895,7 +3895,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
MVT::ValueType OpVT = MVT::Other;
MVT OpVT = MVT::Other;
// Compute the value type for each operand.
switch (OpInfo.Type) {
@ -4227,12 +4227,12 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
// bit_convert.
if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) {
for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) {
if (MVT::isVector(Val.Val->getValueType(i)))
if (Val.Val->getValueType(i).isVector())
Val = DAG.getNode(ISD::BIT_CONVERT,
TLI.getValueType(ResSTy->getElementType(i)), Val);
}
} else {
if (MVT::isVector(Val.getValueType()))
if (Val.getValueType().isVector())
Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()),
Val);
}
@ -4267,7 +4267,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
void SelectionDAGLowering::visitMalloc(MallocInst &I) {
SDOperand Src = getValue(I.getOperand(0));
MVT::ValueType IntPtr = TLI.getPointerTy();
MVT IntPtr = TLI.getPointerTy();
if (IntPtr < Src.getValueType())
Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
@ -4298,7 +4298,7 @@ void SelectionDAGLowering::visitFree(FreeInst &I) {
Entry.Node = getValue(I.getOperand(0));
Entry.Ty = TLI.getTargetData()->getIntPtrType();
Args.push_back(Entry);
MVT::ValueType IntPtr = TLI.getPointerTy();
MVT IntPtr = TLI.getPointerTy();
std::pair<SDOperand,SDOperand> Result =
TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
CallingConv::C, true,
@ -4361,11 +4361,11 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
// Add one result value for each formal argument.
std::vector<MVT::ValueType> RetVals;
std::vector<MVT> RetVals;
unsigned j = 1;
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
I != E; ++I, ++j) {
MVT::ValueType VT = getValueType(I->getType());
MVT VT = getValueType(I->getType());
ISD::ArgFlagsTy Flags;
unsigned OriginalAlignment =
getTargetData()->getABITypeAlignment(I->getType());
@ -4395,7 +4395,7 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
Flags.setNest();
Flags.setOrigAlign(OriginalAlignment);
MVT::ValueType RegisterVT = getRegisterType(VT);
MVT RegisterVT = getRegisterType(VT);
unsigned NumRegs = getNumRegisters(VT);
for (unsigned i = 0; i != NumRegs; ++i) {
RetVals.push_back(RegisterVT);
@ -4438,8 +4438,8 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
unsigned Idx = 1;
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
++I, ++Idx) {
MVT::ValueType VT = getValueType(I->getType());
MVT::ValueType PartVT = getRegisterType(VT);
MVT VT = getValueType(I->getType());
MVT PartVT = getRegisterType(VT);
unsigned NumParts = getNumRegisters(VT);
SmallVector<SDOperand, 4> Parts(NumParts);
@ -4479,7 +4479,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
// Handle all of the outgoing arguments.
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
MVT::ValueType VT = getValueType(Args[i].Ty);
MVT VT = getValueType(Args[i].Ty);
SDOperand Op = Args[i].Node;
ISD::ArgFlagsTy Flags;
unsigned OriginalAlignment =
@ -4510,7 +4510,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
Flags.setNest();
Flags.setOrigAlign(OriginalAlignment);
MVT::ValueType PartVT = getRegisterType(VT);
MVT PartVT = getRegisterType(VT);
unsigned NumParts = getNumRegisters(VT);
SmallVector<SDOperand, 4> Parts(NumParts);
ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
@ -4537,14 +4537,14 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
// Figure out the result value types. We start by making a list of
// the potentially illegal return value types.
SmallVector<MVT::ValueType, 4> LoweredRetTys;
SmallVector<MVT::ValueType, 4> RetTys;
SmallVector<MVT, 4> LoweredRetTys;
SmallVector<MVT, 4> RetTys;
ComputeValueVTs(*this, RetTy, RetTys);
// Then we translate that to a list of legal types.
for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
MVT::ValueType VT = RetTys[I];
MVT::ValueType RegisterVT = getRegisterType(VT);
MVT VT = RetTys[I];
MVT RegisterVT = getRegisterType(VT);
unsigned NumRegs = getNumRegisters(VT);
for (unsigned i = 0; i != NumRegs; ++i)
LoweredRetTys.push_back(RegisterVT);
@ -4571,8 +4571,8 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
SmallVector<SDOperand, 4> ReturnValues;
unsigned RegNo = 0;
for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
MVT::ValueType VT = RetTys[I];
MVT::ValueType RegisterVT = getRegisterType(VT);
MVT VT = RetTys[I];
MVT RegisterVT = getRegisterType(VT);
unsigned NumRegs = getNumRegisters(VT);
unsigned RegNoEnd = NumRegs + RegNo;
SmallVector<SDOperand, 4> Results;
@ -4609,7 +4609,7 @@ SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
// SelectionDAGISel code
//===----------------------------------------------------------------------===//
unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
unsigned SelectionDAGISel::MakeReg(MVT VT) {
return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
}
@ -4798,7 +4798,7 @@ static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
MachineFrameInfo *MFI = MF.getFrameInfo();
if (!isByVal &&
IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
MVT::ValueType VT = Arg.getValueType();
MVT VT = Arg.getValueType();
unsigned VReg = MF.getRegInfo().
createVirtualRegister(TLI.getRegClassFor(VT));
Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
@ -4951,7 +4951,7 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
// Remember that this register needs to added to the machine PHI node as
// the input for this MBB.
MVT::ValueType VT = TLI.getValueType(PN->getType());
MVT VT = TLI.getValueType(PN->getType());
unsigned NumRegisters = TLI.getNumRegisters(VT);
for (unsigned i = 0, e = NumRegisters; i != e; ++i)
PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
@ -5356,7 +5356,7 @@ SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
}
// Add this to the output node.
MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
IntPtrTy));
Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());

10
lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
View File

@ -48,7 +48,7 @@ namespace llvm {
template<typename EdgeIter>
static std::string getEdgeAttributes(const void *Node, EdgeIter EI) {
SDOperand Op = EI.getNode()->getOperand(EI.getOperand());
MVT::ValueType VT = Op.getValueType();
MVT VT = Op.getValueType();
if (VT == MVT::Flag)
return "color=red,style=bold";
else if (VT == MVT::Other)
@ -90,7 +90,7 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
if (Node->getValueType(i) == MVT::Other)
Op += ":ch";
else
Op = Op + ":" + MVT::getValueTypeString(Node->getValueType(i));
Op = Op + ":" + Node->getValueType(i).getMVTString();
if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(Node)) {
Op += ": " + utostr(CSDN->getValue());
@ -154,7 +154,7 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
} else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(Node)) {
Op = Op + " AF=" + N->getArgFlags().getArgFlagsString();
} else if (const VTSDNode *N = dyn_cast<VTSDNode>(Node)) {
Op = Op + " VT=" + MVT::getValueTypeString(N->getVT());
Op = Op + " VT=" + N->getVT().getMVTString();
} else if (const StringSDNode *N = dyn_cast<StringSDNode>(Node)) {
Op = Op + "\"" + N->getValue() + "\"";
} else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(Node)) {
@ -172,7 +172,7 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
break;
}
if (doExt)
Op += MVT::getValueTypeString(LD->getMemoryVT()) + ">";
Op += LD->getMemoryVT().getMVTString() + ">";
if (LD->isVolatile())
Op += "<V>";
Op += LD->getIndexedModeName(LD->getAddressingMode());
@ -180,7 +180,7 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
Op += " A=" + utostr(LD->getAlignment());
} else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(Node)) {
if (ST->isTruncatingStore())
Op += "<trunc " + MVT::getValueTypeString(ST->getMemoryVT()) + ">";
Op += "<trunc " + ST->getMemoryVT().getMVTString() + ">";
if (ST->isVolatile())
Op += "<V>";
Op += ST->getIndexedModeName(ST->getAddressingMode());

149
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -180,12 +180,12 @@ TargetLowering::TargetLowering(TargetMachine &tm)
// Default all indexed load / store to expand.
for (unsigned IM = (unsigned)ISD::PRE_INC;
IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
setIndexedLoadAction(IM, (MVT::ValueType)VT, Expand);
setIndexedStoreAction(IM, (MVT::ValueType)VT, Expand);
setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
}
// These operations default to expand.
setOperationAction(ISD::FGETSIGN, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
}
// Most targets ignore the @llvm.prefetch intrinsic.
@ -244,7 +244,7 @@ void TargetLowering::computeRegisterProperties() {
// Everything defaults to needing one register.
for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
NumRegistersForVT[i] = 1;
RegisterTypeForVT[i] = TransformToType[i] = i;
RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
}
// ...except isVoid, which doesn't need any registers.
NumRegistersForVT[MVT::isVoid] = 0;
@ -256,24 +256,28 @@ void TargetLowering::computeRegisterProperties() {
// Every integer value type larger than this largest register takes twice as
// many registers to represent as the previous ValueType.
for (MVT::ValueType ExpandedReg = LargestIntReg + 1;
MVT::isInteger(ExpandedReg); ++ExpandedReg) {
for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
MVT EVT = (MVT::SimpleValueType)ExpandedReg;
if (!EVT.isInteger())
break;
NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
RegisterTypeForVT[ExpandedReg] = LargestIntReg;
TransformToType[ExpandedReg] = ExpandedReg - 1;
ValueTypeActions.setTypeAction(ExpandedReg, Expand);
RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
ValueTypeActions.setTypeAction(EVT, Expand);
}
// Inspect all of the ValueType's smaller than the largest integer
// register to see which ones need promotion.
MVT::ValueType LegalIntReg = LargestIntReg;
for (MVT::ValueType IntReg = LargestIntReg - 1;
IntReg >= MVT::i1; --IntReg) {
if (isTypeLegal(IntReg)) {
unsigned LegalIntReg = LargestIntReg;
for (unsigned IntReg = LargestIntReg - 1;
IntReg >= (unsigned)MVT::i1; --IntReg) {
MVT IVT = (MVT::SimpleValueType)IntReg;
if (isTypeLegal(IVT)) {
LegalIntReg = IntReg;
} else {
RegisterTypeForVT[IntReg] = TransformToType[IntReg] = LegalIntReg;
ValueTypeActions.setTypeAction(IntReg, Promote);
RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
(MVT::SimpleValueType)LegalIntReg;
ValueTypeActions.setTypeAction(IVT, Promote);
}
}
@ -311,18 +315,19 @@ void TargetLowering::computeRegisterProperties() {
}
// Loop over all of the vector value types to see which need transformations.
for (MVT::ValueType i = MVT::FIRST_VECTOR_VALUETYPE;
i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
if (!isTypeLegal(i)) {
MVT::ValueType IntermediateVT, RegisterVT;
for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
MVT VT = (MVT::SimpleValueType)i;
if (!isTypeLegal(VT)) {
MVT IntermediateVT, RegisterVT;
unsigned NumIntermediates;
NumRegistersForVT[i] =
getVectorTypeBreakdown(i,
getVectorTypeBreakdown(VT,
IntermediateVT, NumIntermediates,
RegisterVT);
RegisterTypeForVT[i] = RegisterVT;
TransformToType[i] = MVT::Other; // this isn't actually used
ValueTypeActions.setTypeAction(i, Expand);
ValueTypeActions.setTypeAction(VT, Expand);
}
}
}
@ -332,8 +337,7 @@ const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
}
MVT::ValueType
TargetLowering::getSetCCResultType(const SDOperand &) const {
MVT TargetLowering::getSetCCResultType(const SDOperand &) const {
return getValueType(TD->getIntPtrType());
}
@ -347,13 +351,13 @@ TargetLowering::getSetCCResultType(const SDOperand &) const {
/// register. It also returns the VT and quantity of the intermediate values
/// before they are promoted/expanded.
///
unsigned TargetLowering::getVectorTypeBreakdown(MVT::ValueType VT,
MVT::ValueType &IntermediateVT,
unsigned TargetLowering::getVectorTypeBreakdown(MVT VT,
MVT &IntermediateVT,
unsigned &NumIntermediates,
MVT::ValueType &RegisterVT) const {
MVT &RegisterVT) const {
// Figure out the right, legal destination reg to copy into.
unsigned NumElts = MVT::getVectorNumElements(VT);
MVT::ValueType EltTy = MVT::getVectorElementType(VT);
unsigned NumElts = VT.getVectorNumElements();
MVT EltTy = VT.getVectorElementType();
unsigned NumVectorRegs = 1;
@ -366,24 +370,23 @@ unsigned TargetLowering::getVectorTypeBreakdown(MVT::ValueType VT,
// Divide the input until we get to a supported size. This will always
// end with a scalar if the target doesn't support vectors.
while (NumElts > 1 &&
!isTypeLegal(MVT::getVectorType(EltTy, NumElts))) {
while (NumElts > 1 && !isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
NumElts >>= 1;
NumVectorRegs <<= 1;
}
NumIntermediates = NumVectorRegs;
MVT::ValueType NewVT = MVT::getVectorType(EltTy, NumElts);
MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
if (!isTypeLegal(NewVT))
NewVT = EltTy;
IntermediateVT = NewVT;
MVT::ValueType DestVT = getTypeToTransformTo(NewVT);
MVT DestVT = getTypeToTransformTo(NewVT);
RegisterVT = DestVT;
if (DestVT < NewVT) {
// Value is expanded, e.g. i64 -> i16.
return NumVectorRegs*(MVT::getSizeInBits(NewVT)/MVT::getSizeInBits(DestVT));
return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
} else {
// Otherwise, promotion or legal types use the same number of registers as
// the vector decimated to the appropriate level.
@ -425,7 +428,7 @@ bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op,
case ISD::XOR:
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
if (C->getAPIntValue().intersects(~Demanded)) {
MVT::ValueType VT = Op.getValueType();
MVT VT = Op.getValueType();
SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
DAG.getConstant(Demanded &
C->getAPIntValue(),
@ -597,7 +600,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
// e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
if ((KnownOne & KnownOne2) == KnownOne) {
MVT::ValueType VT = Op.getValueType();
MVT VT = Op.getValueType();
SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0),
ANDC));
@ -612,7 +615,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
// if we can expand it to have all bits set, do it
if (Expanded.isAllOnesValue()) {
if (Expanded != C->getAPIntValue()) {
MVT::ValueType VT = Op.getValueType();
MVT VT = Op.getValueType();
SDOperand New = TLO.DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
TLO.DAG.getConstant(Expanded, VT));
return TLO.CombineTo(Op, New);
@ -688,7 +691,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
SDOperand NewSA =
TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
MVT::ValueType VT = Op.getValueType();
MVT VT = Op.getValueType();
return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
InOp.getOperand(0), NewSA));
}
@ -705,9 +708,9 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
break;
case ISD::SRL:
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
MVT::ValueType VT = Op.getValueType();
MVT VT = Op.getValueType();
unsigned ShAmt = SA->getValue();
unsigned VTSize = MVT::getSizeInBits(VT);
unsigned VTSize = VT.getSizeInBits();
SDOperand InOp = Op.getOperand(0);
// If the shift count is an invalid immediate, don't do anything.
@ -749,7 +752,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
break;
case ISD::SRA:
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
MVT::ValueType VT = Op.getValueType();
MVT VT = Op.getValueType();
unsigned ShAmt = SA->getValue();
// If the shift count is an invalid immediate, don't do anything.
@ -762,7 +765,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
// demand the input sign bit.
APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
if (HighBits.intersects(NewMask))
InDemandedMask |= APInt::getSignBit(MVT::getSizeInBits(VT));
InDemandedMask |= APInt::getSignBit(VT.getSizeInBits());
if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
KnownZero, KnownOne, TLO, Depth+1))
@ -785,22 +788,22 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
}
break;
case ISD::SIGN_EXTEND_INREG: {
MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
// Sign extension. Compute the demanded bits in the result that are not
// present in the input.
APInt NewBits = APInt::getHighBitsSet(BitWidth,
BitWidth - MVT::getSizeInBits(EVT)) &
BitWidth - EVT.getSizeInBits()) &
NewMask;
// If none of the extended bits are demanded, eliminate the sextinreg.
if (NewBits == 0)
return TLO.CombineTo(Op, Op.getOperand(0));
APInt InSignBit = APInt::getSignBit(MVT::getSizeInBits(EVT));
APInt InSignBit = APInt::getSignBit(EVT.getSizeInBits());
InSignBit.zext(BitWidth);
APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth,
MVT::getSizeInBits(EVT)) &
EVT.getSizeInBits()) &
NewMask;
// Since the sign extended bits are demanded, we know that the sign
@ -852,8 +855,8 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
break;
}
case ISD::SIGN_EXTEND: {
MVT::ValueType InVT = Op.getOperand(0).getValueType();
unsigned InBits = MVT::getSizeInBits(InVT);
MVT InVT = Op.getOperand(0).getValueType();
unsigned InBits = InVT.getSizeInBits();
APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
APInt NewBits = ~InMask & NewMask;
@ -948,9 +951,9 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
break;
}
case ISD::AssertZext: {
MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
APInt InMask = APInt::getLowBitsSet(BitWidth,
MVT::getSizeInBits(VT));
VT.getSizeInBits());
if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask,
KnownZero, KnownOne, TLO, Depth+1))
return true;
@ -962,7 +965,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
#if 0
// If this is an FP->Int bitcast and if the sign bit is the only thing that
// is demanded, turn this into a FGETSIGN.
if (NewMask == MVT::getIntVTSignBit(Op.getValueType()) &&
if (NewMask == MVT::getIntegerVTSignBit(Op.getValueType()) &&
MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
!MVT::isVector(Op.getOperand(0).getValueType())) {
// Only do this xform if FGETSIGN is valid or if before legalize.
@ -972,7 +975,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
// place. We expect the SHL to be eliminated by other optimizations.
SDOperand Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
Op.getOperand(0));
unsigned ShVal = MVT::getSizeInBits(Op.getValueType())-1;
unsigned ShVal = Op.getValueType().getSizeInBits()-1;
SDOperand ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
Sign, ShAmt));
@ -1030,7 +1033,7 @@ unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op,
/// SimplifySetCC - Try to simplify a setcc built with the specified operands
/// and cc. If it is unable to simplify it, return a null SDOperand.
SDOperand
TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1,
ISD::CondCode Cond, bool foldBooleans,
DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
@ -1057,7 +1060,7 @@ TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
N0.getOperand(1).getOpcode() == ISD::Constant) {
unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) {
ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
if ((C1 == 0) == (Cond == ISD::SETEQ)) {
// (srl (ctlz x), 5) == 0 -> X != 0
// (srl (ctlz x), 5) != 1 -> X != 0
@ -1075,7 +1078,7 @@ TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
// If the LHS is a ZERO_EXTEND, perform the comparison on the input.
if (N0.getOpcode() == ISD::ZERO_EXTEND) {
unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
// If the comparison constant has bits in the upper part, the
// zero-extended value could never match.
@ -1118,10 +1121,10 @@ TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
}
} else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
(Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
MVT::ValueType ExtDstTy = N0.getValueType();
unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
MVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
MVT ExtDstTy = N0.getValueType();
unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
// If the extended part has any inconsistent bits, it cannot ever
// compare equal. In other words, they have to be all ones or all
@ -1132,7 +1135,7 @@ TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
return DAG.getConstant(Cond == ISD::SETNE, VT);
SDOperand ZextOp;
MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
MVT Op0Ty = N0.getOperand(0).getValueType();
if (Op0Ty == ExtSrcTy) {
ZextOp = N0.getOperand(0);
} else {
@ -1161,7 +1164,7 @@ TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
// Invert the condition.
ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
CC = ISD::getSetCCInverse(CC,
MVT::isInteger(N0.getOperand(0).getValueType()));
N0.getOperand(0).getValueType().isInteger());
return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC);
}
@ -1196,7 +1199,7 @@ TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
}
APInt MinVal, MaxVal;
unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
if (ISD::isSignedIntSetCC(Cond)) {
MinVal = APInt::getSignedMinValue(OperandBitSize);
MaxVal = APInt::getSignedMaxValue(OperandBitSize);
@ -1313,7 +1316,7 @@ TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
if (N0 == N1) {
// We can always fold X == X for integer setcc's.
if (MVT::isInteger(N0.getValueType()))
if (N0.getValueType().isInteger())
return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
unsigned UOF = ISD::getUnorderedFlavor(Cond);
if (UOF == 2) // FP operators that are undefined on NaNs.
@ -1328,7 +1331,7 @@ TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
}
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
MVT::isInteger(N0.getValueType())) {
N0.getValueType().isInteger()) {
if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
N0.getOpcode() == ISD::XOR) {
// Simplify (X+Y) == (X+Z) --> Y == Z
@ -1517,8 +1520,8 @@ bool TargetLowering::isConsecutiveLoad(SDNode *LD, SDNode *Base,
const MachineFrameInfo *MFI) const {
if (LD->getOperand(0).Val != Base->getOperand(0).Val)
return false;
MVT::ValueType VT = LD->getValueType(0);
if (MVT::getSizeInBits(VT) / 8 != Bytes)
MVT VT = LD->getValueType(0);
if (VT.getSizeInBits() / 8 != Bytes)
return false;
SDOperand Loc = LD->getOperand(1);
@ -1593,10 +1596,10 @@ TargetLowering::getConstraintType(const std::string &Constraint) const {
/// LowerXConstraint - try to replace an X constraint, which matches anything,
/// with another that has more specific requirements based on the type of the
/// corresponding operand.
const char *TargetLowering::LowerXConstraint(MVT::ValueType ConstraintVT) const{
if (MVT::isInteger(ConstraintVT))
const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{
if (ConstraintVT.isInteger())
return "r";
if (MVT::isFloatingPoint(ConstraintVT))
if (ConstraintVT.isFloatingPoint())
return "f"; // works for many targets
return 0;
}
@ -1661,14 +1664,14 @@ void TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
std::vector<unsigned> TargetLowering::
getRegClassForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const {
MVT VT) const {
return std::vector<unsigned>();
}
std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const {
MVT VT) const {
if (Constraint[0] != '{')
return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
@ -2039,7 +2042,7 @@ static mu magicu64(uint64_t d)
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
std::vector<SDNode*>* Created) const {
MVT::ValueType VT = N->getValueType(0);
MVT VT = N->getValueType(0);
// Check to see if we can do this.
if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
@ -2080,7 +2083,7 @@ SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
}
// Extract the sign bit and add it to the quotient
SDOperand T =
DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1,
DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
getShiftAmountTy()));
if (Created)
Created->push_back(T.Val);
@ -2093,7 +2096,7 @@ SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
std::vector<SDNode*>* Created) const {
MVT::ValueType VT = N->getValueType(0);
MVT VT = N->getValueType(0);
// Check to see if we can do this.
if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))

10
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -660,7 +660,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
case ISD::LOAD: {
LoadSDNode *LD = cast<LoadSDNode>(Op);
ISD::MemIndexedMode AM = LD->getAddressingMode();
MVT::ValueType LoadedVT = LD->getMemoryVT();
MVT LoadedVT = LD->getMemoryVT();
if (AM != ISD::UNINDEXED) {
SDOperand Offset, AMOpc;
bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
@ -741,7 +741,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
}
case ARMISD::CMOV: {
bool isThumb = Subtarget->isThumb();
MVT::ValueType VT = Op.getValueType();
MVT VT = Op.getValueType();
SDOperand N0 = Op.getOperand(0);
SDOperand N1 = Op.getOperand(1);
SDOperand N2 = Op.getOperand(2);
@ -805,7 +805,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
SDOperand Ops[] = { N0, N1, Tmp2, N3, InFlag };
unsigned Opc = 0;
switch (VT) {
switch (VT.getSimpleVT()) {
default: assert(false && "Illegal conditional move type!");
break;
case MVT::i32:
@ -821,7 +821,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
return CurDAG->SelectNodeTo(Op.Val, Opc, VT, Ops, 5);
}
case ARMISD::CNEG: {
MVT::ValueType VT = Op.getValueType();
MVT VT = Op.getValueType();
SDOperand N0 = Op.getOperand(0);
SDOperand N1 = Op.getOperand(1);
SDOperand N2 = Op.getOperand(2);
@ -837,7 +837,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
SDOperand Ops[] = { N0, N1, Tmp2, N3, InFlag };
unsigned Opc = 0;
switch (VT) {
switch (VT.getSimpleVT()) {
default: assert(false && "Illegal conditional move type!");
break;
case MVT::f32:

68
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -363,7 +363,7 @@ static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
}
static void
HowToPassArgument(MVT::ValueType ObjectVT, unsigned NumGPRs,
HowToPassArgument(MVT ObjectVT, unsigned NumGPRs,
unsigned StackOffset, unsigned &NeededGPRs,
unsigned &NeededStackSize, unsigned &GPRPad,
unsigned &StackPad, ISD::ArgFlagsTy Flags) {
@ -375,7 +375,7 @@ HowToPassArgument(MVT::ValueType ObjectVT, unsigned NumGPRs,
GPRPad = NumGPRs % ((align + 3)/4);
StackPad = StackOffset % align;
unsigned firstGPR = NumGPRs + GPRPad;
switch (ObjectVT) {
switch (ObjectVT.getSimpleVT()) {
default: assert(0 && "Unhandled argument type!");
case MVT::i32:
case MVT::f32:
@ -400,7 +400,7 @@ HowToPassArgument(MVT::ValueType ObjectVT, unsigned NumGPRs,
/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
/// nodes.
SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
MVT::ValueType RetVT= Op.Val->getValueType(0);
MVT RetVT= Op.Val->getValueType(0);
SDOperand Chain = Op.getOperand(0);
unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
assert((CallConv == CallingConv::C ||
@ -419,7 +419,7 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
unsigned ObjGPRs;
unsigned StackPad;
unsigned GPRPad;
MVT::ValueType ObjectVT = Op.getOperand(5+2*i).getValueType();
MVT ObjectVT = Op.getOperand(5+2*i).getValueType();
ISD::ArgFlagsTy Flags =
cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags();
HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize,
@ -446,7 +446,7 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
SDOperand Arg = Op.getOperand(5+2*i);
ISD::ArgFlagsTy Flags =
cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags();
MVT::ValueType ArgVT = Arg.getValueType();
MVT ArgVT = Arg.getValueType();
unsigned ObjSize;
unsigned ObjGPRs;
@ -457,7 +457,7 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
NumGPRs += GPRPad;
ArgOffset += StackPad;
if (ObjGPRs > 0) {
switch (ArgVT) {
switch (ArgVT.getSimpleVT()) {
default: assert(0 && "Unexpected ValueType for argument!");
case MVT::i32:
RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg));
@ -587,7 +587,7 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
InFlag = Chain.getValue(1);
}
std::vector<MVT::ValueType> NodeTys;
std::vector<MVT> NodeTys;
NodeTys.push_back(MVT::Other); // Returns a chain
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
@ -617,7 +617,7 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
NodeTys.clear();
// If the call has results, copy the values out of the ret val registers.
switch (RetVT) {
switch (RetVT.getSimpleVT()) {
default: assert(0 && "Unexpected ret value!");
case MVT::Other:
break;
@ -708,7 +708,7 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
// be used to form addressing mode. These wrapped nodes will be selected
// into MOVi.
static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
MVT::ValueType PtrVT = Op.getValueType();
MVT PtrVT = Op.getValueType();
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
SDOperand Res;
if (CP->isMachineConstantPoolEntry())
@ -724,7 +724,7 @@ static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
SDOperand
ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
SelectionDAG &DAG) {
MVT::ValueType PtrVT = getPointerTy();
MVT PtrVT = getPointerTy();
unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
ARMConstantPoolValue *CPV =
new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
@ -758,7 +758,7 @@ ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
GlobalValue *GV = GA->getGlobal();
SDOperand Offset;
SDOperand Chain = DAG.getEntryNode();
MVT::ValueType PtrVT = getPointerTy();
MVT PtrVT = getPointerTy();
// Get the Thread Pointer
SDOperand ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
@ -807,7 +807,7 @@ ARMTargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
SDOperand ARMTargetLowering::LowerGlobalAddressELF(SDOperand Op,
SelectionDAG &DAG) {
MVT::ValueType PtrVT = getPointerTy();
MVT PtrVT = getPointerTy();
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
Reloc::Model RelocM = getTargetMachine().getRelocationModel();
if (RelocM == Reloc::PIC_) {
@ -840,7 +840,7 @@ static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op,
SelectionDAG &DAG) {
MVT::ValueType PtrVT = getPointerTy();
MVT PtrVT = getPointerTy();
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
Reloc::Model RelocM = getTargetMachine().getRelocationModel();
bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
@ -875,7 +875,7 @@ SDOperand ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDOperand Op,
SelectionDAG &DAG){
assert(Subtarget->isTargetELF() &&
"GLOBAL OFFSET TABLE not implemented for non-ELF targets");
MVT::ValueType PtrVT = getPointerTy();
MVT PtrVT = getPointerTy();
unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
ARMPCLabelIndex,
@ -888,7 +888,7 @@ SDOperand ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDOperand Op,
}
static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
switch (IntNo) {
default: return SDOperand(); // Don't custom lower most intrinsics.
@ -901,7 +901,7 @@ static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
unsigned VarArgsFrameIndex) {
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
@ -911,7 +911,7 @@ static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
unsigned ArgNo, unsigned &NumGPRs,
unsigned &ArgOffset) {
MachineFunction &MF = DAG.getMachineFunction();
MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
MVT ObjectVT = Op.getValue(ArgNo).getValueType();
SDOperand Root = Op.getOperand(0);
std::vector<SDOperand> ArgValues;
MachineRegisterInfo &RegInfo = MF.getRegInfo();
@ -1025,7 +1025,7 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
ArgValues.push_back(Root);
// Return the new list of results.
std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
std::vector<MVT> RetVT(Op.Val->value_begin(),
Op.Val->value_end());
return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
}
@ -1123,7 +1123,7 @@ static SDOperand getVFPCmp(SDOperand LHS, SDOperand RHS, SelectionDAG &DAG) {
static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG,
const ARMSubtarget *ST) {
MVT::ValueType VT = Op.getValueType();
MVT VT = Op.getValueType();
SDOperand LHS = Op.getOperand(0);
SDOperand RHS = Op.getOperand(1);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
@ -1195,7 +1195,7 @@ SDOperand ARMTargetLowering::LowerBR_JT(SDOperand Op, SelectionDAG &DAG) {
SDOperand Table = Op.getOperand(1);
SDOperand Index = Op.getOperand(2);
MVT::ValueType PTy = getPointerTy();
MVT PTy = getPointerTy();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
SDOperand UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
@ -1204,7 +1204,7 @@ SDOperand ARMTargetLowering::LowerBR_JT(SDOperand Op, SelectionDAG &DAG) {
Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy));
SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
Addr = DAG.getLoad(isPIC ? (MVT::ValueType)MVT::i32 : PTy,
Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy,
Chain, Addr, NULL, 0);
Chain = Addr.getValue(1);
if (isPIC)
@ -1220,7 +1220,7 @@ static SDOperand LowerFP_TO_INT(SDOperand Op, SelectionDAG &DAG) {
}
static SDOperand LowerINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
MVT::ValueType VT = Op.getValueType();
MVT VT = Op.getValueType();
unsigned Opc =
Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
@ -1232,8 +1232,8 @@ static SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
// Implement fcopysign with a fabs and a conditional fneg.
SDOperand Tmp0 = Op.getOperand(0);
SDOperand Tmp1 = Op.getOperand(1);
MVT::ValueType VT = Op.getValueType();
MVT::ValueType SrcVT = Tmp1.getValueType();
MVT VT = Op.getValueType();
MVT SrcVT = Tmp1.getValueType();
SDOperand AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0);
SDOperand Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG);
SDOperand ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
@ -1265,7 +1265,7 @@ ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
unsigned BytesLeft = SizeVal & 3;
unsigned NumMemOps = SizeVal >> 2;
unsigned EmittedNumMemOps = 0;
MVT::ValueType VT = MVT::i32;
MVT VT = MVT::i32;
unsigned VTSize = 4;
unsigned i = 0;
const unsigned MAX_LOADS_IN_LDM = 6;
@ -1536,7 +1536,7 @@ SDOperand ARMTargetLowering::PerformDAGCombine(SDNode *N,
/// isLegalAddressImmediate - Return true if the integer value can be used
/// as the offset of the target addressing mode for load / store of the
/// given type.
static bool isLegalAddressImmediate(int64_t V, MVT::ValueType VT,
static bool isLegalAddressImmediate(int64_t V, MVT VT,
const ARMSubtarget *Subtarget) {
if (V == 0)
return true;
@ -1546,7 +1546,7 @@ static bool isLegalAddressImmediate(int64_t V, MVT::ValueType VT,
return false;
unsigned Scale = 1;
switch (VT) {
switch (VT.getSimpleVT()) {
default: return false;
case MVT::i1:
case MVT::i8:
@ -1570,7 +1570,7 @@ static bool isLegalAddressImmediate(int64_t V, MVT::ValueType VT,
if (V < 0)
V = - V;
switch (VT) {
switch (VT.getSimpleVT()) {
default: return false;
case MVT::i1:
case MVT::i8:
@ -1615,7 +1615,7 @@ bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
return false;
int Scale = AM.Scale;
switch (getValueType(Ty)) {
switch (getValueType(Ty).getSimpleVT()) {
default: return false;
case MVT::i1:
case MVT::i8:
@ -1650,7 +1650,7 @@ bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
}
static bool getIndexedAddressParts(SDNode *Ptr, MVT::ValueType VT,
static bool getIndexedAddressParts(SDNode *Ptr, MVT VT,
bool isSEXTLoad, SDOperand &Base,
SDOperand &Offset, bool &isInc,
SelectionDAG &DAG) {
@ -1717,7 +1717,7 @@ ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
if (Subtarget->isThumb())
return false;
MVT::ValueType VT;
MVT VT;
SDOperand Ptr;
bool isSEXTLoad = false;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
@ -1751,7 +1751,7 @@ bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
if (Subtarget->isThumb())
return false;
MVT::ValueType VT;
MVT VT;
SDOperand Ptr;
bool isSEXTLoad = false;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
@ -1816,7 +1816,7 @@ ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
std::pair<unsigned, const TargetRegisterClass*>
ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const {
MVT VT) const {
if (Constraint.size() == 1) {
// GCC RS6000 Constraint Letters
switch (Constraint[0]) {
@ -1838,7 +1838,7 @@ ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
std::vector<unsigned> ARMTargetLowering::
getRegClassForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const {
MVT VT) const {
if (Constraint.size() != 1)
return std::vector<unsigned>();

4
lib/Target/ARM/ARMISelLowering.h
View File

@ -114,10 +114,10 @@ namespace llvm {
ConstraintType getConstraintType(const std::string &Constraint) const;
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
MVT VT) const;
std::vector<unsigned>
getRegClassForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
MVT VT) const;
virtual const ARMSubtarget* getSubtarget() {
return Subtarget;

16
lib/Target/Alpha/AlphaISelDAGToDAG.cpp
View File

@ -334,7 +334,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
case ISD::TargetConstantFP: {
ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
bool isDouble = N->getValueType(0) == MVT::f64;
MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
MVT T = isDouble ? MVT::f64 : MVT::f32;
if (CN->getValueAPF().isPosZero()) {
return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
T, CurDAG->getRegister(Alpha::F31, T),
@ -350,7 +350,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
}
case ISD::SETCC:
if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) {
if (N->getOperand(0).Val->getValueType(0).isFloatingPoint()) {
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
unsigned Opc = Alpha::WTF;
@ -404,9 +404,9 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
break;
case ISD::SELECT:
if (MVT::isFloatingPoint(N->getValueType(0)) &&
if (N->getValueType(0).isFloatingPoint() &&
(N->getOperand(0).getOpcode() != ISD::SETCC ||
!MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
!N->getOperand(0).getOperand(1).getValueType().isFloatingPoint())) {
//This should be the condition not covered by the Patterns
//FIXME: Don't have SelectCode die, but rather return something testable
// so that things like this can be caught in fall though code
@ -472,7 +472,7 @@ void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
AddToISelQueue(Chain);
std::vector<SDOperand> CallOperands;
std::vector<MVT::ValueType> TypeOperands;
std::vector<MVT> TypeOperands;
//grab the arguments
for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
@ -489,7 +489,7 @@ void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
for (int i = 6; i < count; ++i) {
unsigned Opc = Alpha::WTF;
if (MVT::isInteger(TypeOperands[i])) {
if (TypeOperands[i].isInteger()) {
Opc = Alpha::STQ;
} else if (TypeOperands[i] == MVT::f32) {
Opc = Alpha::STS;
@ -504,7 +504,7 @@ void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0);
}
for (int i = 0; i < std::min(6, count); ++i) {
if (MVT::isInteger(TypeOperands[i])) {
if (TypeOperands[i].isInteger()) {
Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
InFlag = Chain.getValue(1);
} else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
@ -533,7 +533,7 @@ void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
std::vector<SDOperand> CallResults;
switch (N->getValueType(0)) {
switch (N->getValueType(0).getSimpleVT()) {
default: assert(0 && "Unexpected ret value!");
case MVT::Other: break;
case MVT::i64:

42
lib/Target/Alpha/AlphaISelLowering.cpp
View File

@ -145,8 +145,7 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
computeRegisterProperties();
}
MVT::ValueType
AlphaTargetLowering::getSetCCResultType(const SDOperand &) const {
MVT AlphaTargetLowering::getSetCCResultType(const SDOperand &) const {
return MVT::i64;
}
@ -169,7 +168,7 @@ const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
}
static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
MVT::ValueType PtrVT = Op.getValueType();
MVT PtrVT = Op.getValueType();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
SDOperand Zero = DAG.getConstant(0, PtrVT);
@ -217,14 +216,13 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
SDOperand argt;
MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
MVT ObjectVT = Op.getValue(ArgNo).getValueType();
SDOperand ArgVal;
if (ArgNo < 6) {
switch (ObjectVT) {
switch (ObjectVT.getSimpleVT()) {
default:
cerr << "Unknown Type " << ObjectVT << "\n";
abort();
assert(false && "Invalid value type!");
case MVT::f64:
args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
&Alpha::F8RCRegClass);
@ -282,7 +280,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
ArgValues.push_back(Root);
// Return the new list of results.
std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
std::vector<MVT> RetVT(Op.Val->value_begin(),
Op.Val->value_end());
return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
}
@ -300,12 +298,12 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
break;
//return SDOperand(); // ret void is legal
case 3: {
MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
MVT ArgVT = Op.getOperand(1).getValueType();
unsigned ArgReg;
if (MVT::isInteger(ArgVT))
if (ArgVT.isInteger())
ArgReg = Alpha::R0;
else {
assert(MVT::isFloatingPoint(ArgVT));
assert(ArgVT.isFloatingPoint());
ArgReg = Alpha::F0;
}
Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
@ -332,7 +330,7 @@ AlphaTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
std::vector<SDOperand> args_to_use;
for (unsigned i = 0, e = Args.size(); i != e; ++i)
{
switch (getValueType(Args[i].Ty)) {
switch (getValueType(Args[i].Ty).getSimpleVT()) {
default: assert(0 && "Unexpected ValueType for argument!");
case MVT::i1:
case MVT::i8:
@ -355,9 +353,9 @@ AlphaTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
args_to_use.push_back(Args[i].Node);
}
std::vector<MVT::ValueType> RetVals;
MVT::ValueType RetTyVT = getValueType(RetTy);
MVT::ValueType ActualRetTyVT = RetTyVT;
std::vector<MVT> RetVals;
MVT RetTyVT = getValueType(RetTy);
MVT ActualRetTyVT = RetTyVT;
if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
ActualRetTyVT = MVT::i64;
@ -407,17 +405,17 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
case ISD::JumpTable: return LowerJumpTable(Op, DAG);
case ISD::SINT_TO_FP: {
assert(MVT::i64 == Op.getOperand(0).getValueType() &&
assert(Op.getOperand(0).getValueType() == MVT::i64 &&
"Unhandled SINT_TO_FP type in custom expander!");
SDOperand LD;
bool isDouble = MVT::f64 == Op.getValueType();
bool isDouble = Op.getValueType() == MVT::f64;
LD = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
isDouble?MVT::f64:MVT::f32, LD);
return FP;
}
case ISD::FP_TO_SINT: {
bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
bool isDouble = Op.getOperand(0).getValueType() == MVT::f64;
SDOperand src = Op.getOperand(0);
if (!isDouble) //Promote
@ -465,7 +463,7 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
case ISD::SREM:
//Expand only on constant case
if (Op.getOperand(1).getOpcode() == ISD::Constant) {
MVT::ValueType VT = Op.Val->getValueType(0);
MVT VT = Op.Val->getValueType(0);
SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
BuildUDIV(Op.Val, DAG, NULL) :
BuildSDIV(Op.Val, DAG, NULL);
@ -476,7 +474,7 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
//fall through
case ISD::SDIV:
case ISD::UDIV:
if (MVT::isInteger(Op.getValueType())) {
if (Op.getValueType().isInteger()) {
if (Op.getOperand(1).getOpcode() == ISD::Constant)
return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL)
: BuildUDIV(Op.Val, DAG, NULL);
@ -505,7 +503,7 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
Tmp, NULL, 0, MVT::i32);
SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
if (MVT::isFloatingPoint(Op.getValueType()))
if (Op.getValueType().isFloatingPoint())
{
//if fp && Offset < 6*8, then subtract 6*8 from DataPtr
SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
@ -596,7 +594,7 @@ AlphaTargetLowering::getConstraintType(const std::string &Constraint) const {
std::vector<unsigned> AlphaTargetLowering::
getRegClassForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const {
MVT VT) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
default: break; // Unknown constriant letter

4
lib/Target/Alpha/AlphaISelLowering.h
View File

@ -67,7 +67,7 @@ namespace llvm {
explicit AlphaTargetLowering(TargetMachine &TM);
/// getSetCCResultType - Get the SETCC result ValueType
virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
virtual MVT getSetCCResultType(const SDOperand &) const;
/// LowerOperation - Provide custom lowering hooks for some operations.
///
@ -88,7 +88,7 @@ namespace llvm {
std::vector<unsigned>
getRegClassForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
MVT VT) const;
bool hasITOF() { return useITOF; }

26
lib/Target/CellSPU/SPUISelDAGToDAG.cpp
View File

@ -110,7 +110,7 @@ namespace {
bool
isIntS16Immediate(ConstantSDNode *CN, short &Imm)
{
MVT::ValueType vt = CN->getValueType(0);
MVT vt = CN->getValueType(0);
Imm = (short) CN->getValue();
if (vt >= MVT::i1 && vt <= MVT::i16) {
return true;
@ -139,7 +139,7 @@ namespace {
static bool
isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
{
MVT::ValueType vt = FPN->getValueType(0);
MVT vt = FPN->getValueType(0);
if (vt == MVT::f32) {
int val = FloatToBits(FPN->getValueAPF().convertToFloat());
int sval = (int) ((val << 16) >> 16);
@ -161,10 +161,10 @@ namespace {
}
//===------------------------------------------------------------------===//
//! MVT::ValueType to "useful stuff" mapping structure:
//! MVT to "useful stuff" mapping structure:
struct valtype_map_s {
MVT::ValueType VT;
MVT VT;
unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
bool ldresult_imm; /// LDRESULT instruction requires immediate?
int prefslot_byte; /// Byte offset of the "preferred" slot
@ -189,7 +189,7 @@ namespace {
const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
const valtype_map_s *getValueTypeMapEntry(MVT::ValueType VT)
const valtype_map_s *getValueTypeMapEntry(MVT VT)
{
const valtype_map_s *retval = 0;
for (size_t i = 0; i < n_valtype_map; ++i) {
@ -203,7 +203,7 @@ namespace {
#ifndef NDEBUG
if (retval == 0) {
cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
<< MVT::getValueTypeString(VT)
<< VT.getMVTString()
<< "\n";
abort();
}
@ -364,7 +364,7 @@ bool
SPUDAGToDAGISel::SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
SDOperand &Index) {
// These match the addr256k operand type:
MVT::ValueType OffsVT = MVT::i16;
MVT OffsVT = MVT::i16;
SDOperand Zero = CurDAG->getTargetConstant(0, OffsVT);
switch (N.getOpcode()) {
@ -446,7 +446,7 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Bas
SDOperand &Index, int minOffset,
int maxOffset) {
unsigned Opc = N.getOpcode();
unsigned PtrTy = SPUtli.getPointerTy();
MVT PtrTy = SPUtli.getPointerTy();
if (Opc == ISD::FrameIndex) {
// Stack frame index must be less than 512 (divided by 16):
@ -587,7 +587,7 @@ SPUDAGToDAGISel::Select(SDOperand Op) {
unsigned Opc = N->getOpcode();
int n_ops = -1;
unsigned NewOpc;
MVT::ValueType OpVT = Op.getValueType();
MVT OpVT = Op.getValueType();
SDOperand Ops[8];
if (Opc >= ISD::BUILTIN_OP_END && Opc < SPUISD::FIRST_NUMBER) {
@ -596,7 +596,7 @@ SPUDAGToDAGISel::Select(SDOperand Op) {
// Selects to (add $sp, FI * stackSlotSize)
int FI =
SPUFrameInfo::FItoStackOffset(cast<FrameIndexSDNode>(N)->getIndex());
MVT::ValueType PtrVT = SPUtli.getPointerTy();
MVT PtrVT = SPUtli.getPointerTy();
// Adjust stack slot to actual offset in frame:
if (isS10Constant(FI)) {
@ -636,7 +636,7 @@ SPUDAGToDAGISel::Select(SDOperand Op) {
}
} else if (Opc == SPUISD::LDRESULT) {
// Custom select instructions for LDRESULT
unsigned VT = N->getValueType(0);
MVT VT = N->getValueType(0);
SDOperand Arg = N->getOperand(0);
SDOperand Chain = N->getOperand(1);
SDNode *Result;
@ -644,7 +644,7 @@ SPUDAGToDAGISel::Select(SDOperand Op) {
if (vtm->ldresult_ins == 0) {
cerr << "LDRESULT for unsupported type: "
<< MVT::getValueTypeString(VT)
<< VT.getMVTString()
<< "\n";
abort();
}
@ -670,7 +670,7 @@ SPUDAGToDAGISel::Select(SDOperand Op) {
/* || Op0.getOpcode() == SPUISD::AFormAddr) */
// (IndirectAddr (LDRESULT, imm))
SDOperand Op1 = Op.getOperand(1);
MVT::ValueType VT = Op.getValueType();
MVT VT = Op.getValueType();
DEBUG(cerr << "CellSPU: IndirectAddr(LDRESULT, imm):\nOp0 = ");
DEBUG(Op.getOperand(0).Val->dump(CurDAG));

267
lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -38,9 +38,9 @@ using namespace llvm;
namespace {
std::map<unsigned, const char *> node_names;
//! MVT::ValueType mapping to useful data for Cell SPU
//! MVT mapping to useful data for Cell SPU
struct valtype_map_s {
const MVT::ValueType valtype;
const MVT valtype;
const int prefslot_byte;
};
@ -57,7 +57,7 @@ namespace {
const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
const valtype_map_s *getValueTypeMapEntry(MVT::ValueType VT) {
const valtype_map_s *getValueTypeMapEntry(MVT VT) {
const valtype_map_s *retval = 0;
for (size_t i = 0; i < n_valtype_map; ++i) {
@ -70,7 +70,7 @@ namespace {
#ifndef NDEBUG
if (retval == 0) {
cerr << "getValueTypeMapEntry returns NULL for "
<< MVT::getValueTypeString(VT)
<< VT.getMVTString()
<< "\n";
abort();
}
@ -162,8 +162,10 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
// SPU's loads and stores have to be custom lowered:
for (unsigned sctype = (unsigned) MVT::i1; sctype < (unsigned) MVT::f128;
++sctype) {
setOperationAction(ISD::LOAD, sctype, Custom);
setOperationAction(ISD::STORE, sctype, Custom);
MVT VT = (MVT::SimpleValueType)sctype;
setOperationAction(ISD::LOAD, VT, Custom);
setOperationAction(ISD::STORE, VT, Custom);
}
// Custom lower BRCOND for i1, i8 to "promote" the result to
@ -296,9 +298,11 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
// appropriate instructions to materialize the address.
for (unsigned sctype = (unsigned) MVT::i1; sctype < (unsigned) MVT::f128;
++sctype) {
setOperationAction(ISD::GlobalAddress, sctype, Custom);
setOperationAction(ISD::ConstantPool, sctype, Custom);
setOperationAction(ISD::JumpTable, sctype, Custom);
MVT VT = (MVT::SimpleValueType)sctype;
setOperationAction(ISD::GlobalAddress, VT, Custom);
setOperationAction(ISD::ConstantPool, VT, Custom);
setOperationAction(ISD::JumpTable, VT, Custom);
}
// RET must be custom lowered, to meet ABI requirements
@ -335,36 +339,38 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
addRegisterClass(MVT::v4f32, SPU::VECREGRegisterClass);
addRegisterClass(MVT::v2f64, SPU::VECREGRegisterClass);
for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
// add/sub are legal for all supported vector VT's.
setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
// mul has to be custom lowered.
setOperationAction(ISD::MUL , (MVT::ValueType)VT, Custom);
for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
MVT VT = (MVT::SimpleValueType)i;
setOperationAction(ISD::AND , (MVT::ValueType)VT, Legal);
setOperationAction(ISD::OR , (MVT::ValueType)VT, Legal);
setOperationAction(ISD::XOR , (MVT::ValueType)VT, Legal);
setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Legal);
setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Legal);
setOperationAction(ISD::STORE, (MVT::ValueType)VT, Legal);
// add/sub are legal for all supported vector VT's.
setOperationAction(ISD::ADD , VT, Legal);
setOperationAction(ISD::SUB , VT, Legal);
// mul has to be custom lowered.
setOperationAction(ISD::MUL , VT, Custom);
setOperationAction(ISD::AND , VT, Legal);
setOperationAction(ISD::OR , VT, Legal);
setOperationAction(ISD::XOR , VT, Legal);
setOperationAction(ISD::LOAD , VT, Legal);
setOperationAction(ISD::SELECT, VT, Legal);
setOperationAction(ISD::STORE, VT, Legal);
// These operations need to be expanded:
setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Custom);
setOperationAction(ISD::SDIV, VT, Expand);
setOperationAction(ISD::SREM, VT, Expand);
setOperationAction(ISD::UDIV, VT, Expand);
setOperationAction(ISD::UREM, VT, Expand);
setOperationAction(ISD::FDIV, VT, Custom);
// Custom lower build_vector, constant pool spills, insert and
// extract vector elements:
setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom);
setOperationAction(ISD::ConstantPool, (MVT::ValueType)VT, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
setOperationAction(ISD::ConstantPool, VT, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
}
setOperationAction(ISD::MUL, MVT::v16i8, Custom);
@ -447,10 +453,9 @@ SPUTargetLowering::getTargetNodeName(unsigned Opcode) const
return ((i != node_names.end()) ? i->second : 0);
}
MVT::ValueType
SPUTargetLowering::getSetCCResultType(const SDOperand &Op) const {
MVT::ValueType VT = Op.getValueType();
if (MVT::isInteger(VT))
MVT SPUTargetLowering::getSetCCResultType(const SDOperand &Op) const {
MVT VT = Op.getValueType();
if (VT.isInteger())
return VT;
else
return MVT::i32;
@ -490,9 +495,9 @@ static SDOperand
AlignedLoad(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST,
LSBaseSDNode *LSN,
unsigned &alignment, int &alignOffs, int &prefSlotOffs,
MVT::ValueType &VT, bool &was16aligned)
MVT &VT, bool &was16aligned)
{
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
const valtype_map_s *vtm = getValueTypeMapEntry(VT);
SDOperand basePtr = LSN->getBasePtr();
SDOperand chain = LSN->getChain();
@ -573,8 +578,8 @@ static SDOperand
LowerLOAD(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
LoadSDNode *LN = cast<LoadSDNode>(Op);
SDOperand the_chain = LN->getChain();
MVT::ValueType VT = LN->getMemoryVT();
MVT::ValueType OpVT = Op.Val->getValueType(0);
MVT VT = LN->getMemoryVT();
MVT OpVT = Op.Val->getValueType(0);
ISD::LoadExtType ExtType = LN->getExtensionType();
unsigned alignment = LN->getAlignment();
SDOperand Ops[8];
@ -601,7 +606,7 @@ LowerLOAD(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
if (was16aligned) {
Ops[2] = DAG.getConstant(rotamt, MVT::i16);
} else {
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
LoadSDNode *LN1 = cast<LoadSDNode>(result);
Ops[2] = DAG.getNode(ISD::ADD, PtrVT, LN1->getBasePtr(),
DAG.getConstant(rotamt, PtrVT));
@ -613,15 +618,15 @@ LowerLOAD(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
if (VT == OpVT || ExtType == ISD::EXTLOAD) {
SDVTList scalarvts;
MVT::ValueType vecVT = MVT::v16i8;
MVT vecVT = MVT::v16i8;
// Convert the loaded v16i8 vector to the appropriate vector type
// specified by the operand:
if (OpVT == VT) {
if (VT != MVT::i1)
vecVT = MVT::getVectorType(VT, (128 / MVT::getSizeInBits(VT)));
vecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
} else
vecVT = MVT::getVectorType(OpVT, (128 / MVT::getSizeInBits(OpVT)));
vecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
Ops[0] = the_chain;
Ops[1] = DAG.getNode(ISD::BIT_CONVERT, vecVT, result);
@ -681,9 +686,9 @@ static SDOperand
LowerSTORE(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
StoreSDNode *SN = cast<StoreSDNode>(Op);
SDOperand Value = SN->getValue();
MVT::ValueType VT = Value.getValueType();
MVT::ValueType StVT = (!SN->isTruncatingStore() ? VT : SN->getMemoryVT());
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
MVT VT = Value.getValueType();
MVT StVT = (!SN->isTruncatingStore() ? VT : SN->getMemoryVT());
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
unsigned alignment = SN->getAlignment();
switch (SN->getAddressingMode()) {
@ -693,11 +698,11 @@ LowerSTORE(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
// The vector type we really want to load from the 16-byte chunk, except
// in the case of MVT::i1, which has to be v16i8.
unsigned vecVT, stVecVT = MVT::v16i8;
MVT vecVT, stVecVT = MVT::v16i8;
if (StVT != MVT::i1)
stVecVT = MVT::getVectorType(StVT, (128 / MVT::getSizeInBits(StVT)));
vecVT = MVT::getVectorType(VT, (128 / MVT::getSizeInBits(VT)));
stVecVT = MVT::getVectorVT(StVT, (128 / StVT.getSizeInBits()));
vecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
SDOperand alignLoadVec =
AlignedLoad(Op, DAG, ST, SN, alignment,
@ -773,7 +778,7 @@ LowerSTORE(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
/// Generate the address of a constant pool entry.
static SDOperand
LowerConstantPool(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
MVT::ValueType PtrVT = Op.getValueType();
MVT PtrVT = Op.getValueType();
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
Constant *C = CP->getConstVal();
SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
@ -798,7 +803,7 @@ LowerConstantPool(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
static SDOperand
LowerJumpTable(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
MVT::ValueType PtrVT = Op.getValueType();
MVT PtrVT = Op.getValueType();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
SDOperand Zero = DAG.getConstant(0, PtrVT);
@ -821,7 +826,7 @@ LowerJumpTable(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
static SDOperand
LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
MVT::ValueType PtrVT = Op.getValueType();
MVT PtrVT = Op.getValueType();
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
GlobalValue *GV = GSDN->getGlobal();
SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
@ -853,7 +858,7 @@ LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
*/
static SDOperand
LowerConstant(SDOperand Op, SelectionDAG &DAG) {
unsigned VT = Op.getValueType();
MVT VT = Op.getValueType();
ConstantSDNode *CN = cast<ConstantSDNode>(Op.Val);
if (VT == MVT::i64) {
@ -862,7 +867,7 @@ LowerConstant(SDOperand Op, SelectionDAG &DAG) {
DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i64, T, T));
} else {
cerr << "LowerConstant: unhandled constant type "
<< MVT::getValueTypeString(VT)
<< VT.getMVTString()
<< "\n";
abort();
/*NOTREACHED*/
@ -874,7 +879,7 @@ LowerConstant(SDOperand Op, SelectionDAG &DAG) {
//! Custom lower double precision floating point constants
static SDOperand
LowerConstantFP(SDOperand Op, SelectionDAG &DAG) {
unsigned VT = Op.getValueType();
MVT VT = Op.getValueType();
ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.Val);
assert((FP != 0) &&
@ -894,8 +899,8 @@ static SDOperand
LowerBRCOND(SDOperand Op, SelectionDAG &DAG)
{
SDOperand Cond = Op.getOperand(1);
MVT::ValueType CondVT = Cond.getValueType();
MVT::ValueType CondNVT;
MVT CondVT = Cond.getValueType();
MVT CondNVT;
if (CondVT == MVT::i1 || CondVT == MVT::i8) {
CondNVT = (CondVT == MVT::i1 ? MVT::i32 : MVT::i16);
@ -924,19 +929,19 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
unsigned ArgRegIdx = 0;
unsigned StackSlotSize = SPUFrameInfo::stackSlotSize();
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Add DAG nodes to load the arguments or copy them out of registers.
for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
SDOperand ArgVal;
bool needsLoad = false;
MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
MVT ObjectVT = Op.getValue(ArgNo).getValueType();
unsigned ObjSize = ObjectVT.getSizeInBits()/8;
switch (ObjectVT) {
switch (ObjectVT.getSimpleVT()) {
default: {
cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
<< MVT::getValueTypeString(ObjectVT)
<< ObjectVT.getMVTString()
<< "\n";
abort();
}
@ -1032,7 +1037,7 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
// If the function takes variable number of arguments, make a frame index for
// the start of the first vararg value... for expansion of llvm.va_start.
if (isVarArg) {
VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
ArgOffset);
SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
// If this function is vararg, store any remaining integer argument regs to
@ -1046,7 +1051,7 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
MemOps.push_back(Store);
// Increment the address by four for the next argument to store
SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
SDOperand PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
}
if (!MemOps.empty())
@ -1056,7 +1061,7 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
ArgValues.push_back(Root);
// Return the new list of results.
std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
std::vector<MVT> RetVT(Op.Val->value_begin(),
Op.Val->value_end());
return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
}
@ -1090,7 +1095,7 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs();
// Handy pointer type
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Accumulate how many bytes are to be pushed on the stack, including the
// linkage area, and parameter passing area. According to the SPU ABI,
@ -1120,7 +1125,7 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
switch (Arg.getValueType()) {
switch (Arg.getValueType().getSimpleVT()) {
default: assert(0 && "Unexpected ValueType for argument!");
case MVT::i32:
case MVT::i64:
@ -1174,7 +1179,7 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
InFlag = Chain.getValue(1);
}
std::vector<MVT::ValueType> NodeTys;
std::vector<MVT> NodeTys;
NodeTys.push_back(MVT::Other); // Returns a chain
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
@ -1186,7 +1191,7 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
// node so that legalize doesn't hack it.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
GlobalValue *GV = G->getGlobal();
unsigned CalleeVT = Callee.getValueType();
MVT CalleeVT = Callee.getValueType();
SDOperand Zero = DAG.getConstant(0, PtrVT);
SDOperand GA = DAG.getTargetGlobalAddress(GV, CalleeVT);
@ -1243,7 +1248,7 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
NodeTys.clear();
// If the call has results, copy the values out of the ret val registers.
switch (Op.Val->getValueType(0)) {
switch (Op.Val->getValueType(0).getSimpleVT()) {
default: assert(0 && "Unexpected ret value!");
case MVT::Other: break;
case MVT::i32:
@ -1365,7 +1370,7 @@ getVecImm(SDNode *N) {
/// and the value fits into an unsigned 18-bit constant, and if so, return the
/// constant
SDOperand SPU::get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
MVT::ValueType ValueType) {
MVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
uint64_t Value = CN->getValue();
if (ValueType == MVT::i64) {
@ -1387,7 +1392,7 @@ SDOperand SPU::get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
/// and the value fits into a signed 16-bit constant, and if so, return the
/// constant
SDOperand SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
MVT::ValueType ValueType) {
MVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
int64_t Value = CN->getSignExtended();
if (ValueType == MVT::i64) {
@ -1410,7 +1415,7 @@ SDOperand SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
/// and the value fits into a signed 10-bit constant, and if so, return the
/// constant
SDOperand SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
MVT::ValueType ValueType) {
MVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
int64_t Value = CN->getSignExtended();
if (ValueType == MVT::i64) {
@ -1436,7 +1441,7 @@ SDOperand SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
/// constant vectors. Thus, we test to see if the upper and lower bytes are the
/// same value.
SDOperand SPU::get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
MVT::ValueType ValueType) {
MVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
int Value = (int) CN->getValue();
if (ValueType == MVT::i16
@ -1455,7 +1460,7 @@ SDOperand SPU::get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
/// and the value fits into a signed 16-bit constant, and if so, return the
/// constant
SDOperand SPU::get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
MVT::ValueType ValueType) {
MVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
uint64_t Value = CN->getValue();
if ((ValueType == MVT::i32
@ -1495,7 +1500,7 @@ static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
// Start with zero'd results.
VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
unsigned EltBitSize = BV->getOperand(0).getValueType().getSizeInBits();
for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
SDOperand OpVal = BV->getOperand(i);
@ -1597,7 +1602,7 @@ static bool isConstantSplat(const uint64_t Bits128[2],
// this case more efficiently than a constant pool load, lower it to the
// sequence of ops that should be used.
static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
MVT::ValueType VT = Op.getValueType();
MVT VT = Op.getValueType();
// If this is a vector of constants or undefs, get the bits. A bit in
// UndefBits is set if the corresponding element of the vector is an
// ISD::UNDEF value. For undefs, the corresponding VectorBits values are
@ -1608,11 +1613,11 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
int SplatSize;
if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)
|| !isConstantSplat(VectorBits, UndefBits,
MVT::getSizeInBits(MVT::getVectorElementType(VT)),
VT.getVectorElementType().getSizeInBits(),
SplatBits, SplatUndef, SplatSize))
return SDOperand(); // Not a constant vector, not a splat.
switch (VT) {
switch (VT.getSimpleVT()) {
default:
case MVT::v4f32: {
uint32_t Value32 = SplatBits;
@ -1649,14 +1654,14 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
Value16 = (unsigned short) (SplatBits & 0xffff);
else
Value16 = (unsigned short) (SplatBits | (SplatBits << 8));
SDOperand T = DAG.getConstant(Value16, MVT::getVectorElementType(VT));
SDOperand T = DAG.getConstant(Value16, VT.getVectorElementType());
SDOperand Ops[8];
for (int i = 0; i < 8; ++i) Ops[i] = T;
return DAG.getNode(ISD::BUILD_VECTOR, VT, Ops, 8);
}
case MVT::v4i32: {
unsigned int Value = SplatBits;
SDOperand T = DAG.getConstant(Value, MVT::getVectorElementType(VT));
SDOperand T = DAG.getConstant(Value, VT.getVectorElementType());
return DAG.getNode(ISD::BUILD_VECTOR, VT, T, T, T, T);
}
case MVT::v2i64: {
@ -1772,7 +1777,7 @@ static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
// If we have a single element being moved from V1 to V2, this can be handled
// using the C*[DX] compute mask instructions, but the vector elements have
// to be monotonically increasing with one exception element.
MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType());
MVT EltVT = V1.getValueType().getVectorElementType();
unsigned EltsFromV2 = 0;
unsigned V2Elt = 0;
unsigned V2EltIdx0 = 0;
@ -1811,7 +1816,7 @@ static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
MachineFunction &MF = DAG.getMachineFunction();
MachineRegisterInfo &RegInfo = MF.getRegInfo();
unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Initialize temporary register to 0
SDOperand InitTempReg =
DAG.getCopyToReg(DAG.getEntryNode(), VReg, DAG.getConstant(0, PtrVT));
@ -1824,7 +1829,7 @@ static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
return DAG.getNode(SPUISD::SHUFB, V1.getValueType(), V2, V1, ShufMaskOp);
} else {
// Convert the SHUFFLE_VECTOR mask's input element units to the actual bytes.
unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
unsigned BytesPerElement = EltVT.getSizeInBits()/8;
SmallVector<SDOperand, 16> ResultMask;
for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
@ -1855,11 +1860,11 @@ static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
ConstantSDNode *CN = cast<ConstantSDNode>(Op0.Val);
SmallVector<SDOperand, 16> ConstVecValues;
MVT::ValueType VT;
MVT VT;
size_t n_copies;
// Create a constant vector:
switch (Op.getValueType()) {
switch (Op.getValueType().getSimpleVT()) {
default: assert(0 && "Unexpected constant value type in "
"LowerSCALAR_TO_VECTOR");
case MVT::v16i8: n_copies = 16; VT = MVT::i8; break;
@ -1878,7 +1883,7 @@ static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
&ConstVecValues[0], ConstVecValues.size());
} else {
// Otherwise, copy the value from one register to another:
switch (Op0.getValueType()) {
switch (Op0.getValueType().getSimpleVT()) {
default: assert(0 && "Unexpected value type in LowerSCALAR_TO_VECTOR");
case MVT::i8:
case MVT::i16:
@ -1894,7 +1899,14 @@ static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
}
static SDOperand LowerVectorMUL(SDOperand Op, SelectionDAG &DAG) {
switch (Op.getValueType()) {
switch (Op.getValueType().getSimpleVT()) {
default:
cerr << "CellSPU: Unknown vector multiplication, got "
<< Op.getValueType().getMVTString()
<< "\n";
abort();
/*NOTREACHED*/
case MVT::v4i32: {
SDOperand rA = Op.getOperand(0);
SDOperand rB = Op.getOperand(1);
@ -2020,13 +2032,6 @@ static SDOperand LowerVectorMUL(SDOperand Op, SelectionDAG &DAG) {
DAG.getNode(ISD::OR, MVT::v4i32,
LoProd, HiProd));
}
default:
cerr << "CellSPU: Unknown vector multiplication, got "
<< MVT::getValueTypeString(Op.getValueType())
<< "\n";
abort();
/*NOTREACHED*/
}
return SDOperand();
@ -2038,7 +2043,7 @@ static SDOperand LowerFDIVf32(SDOperand Op, SelectionDAG &DAG) {
SDOperand A = Op.getOperand(0);
SDOperand B = Op.getOperand(1);
unsigned VT = Op.getValueType();
MVT VT = Op.getValueType();
unsigned VRegBR, VRegC;
@ -2077,7 +2082,7 @@ static SDOperand LowerFDIVf32(SDOperand Op, SelectionDAG &DAG) {
}
static SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
unsigned VT = Op.getValueType();
MVT VT = Op.getValueType();
SDOperand N = Op.getOperand(0);
SDOperand Elt = Op.getOperand(1);
SDOperand ShufMask[16];
@ -2104,9 +2109,11 @@ static SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
// Need to generate shuffle mask and extract:
int prefslot_begin = -1, prefslot_end = -1;
int elt_byte = EltNo * MVT::getSizeInBits(VT) / 8;
int elt_byte = EltNo * VT.getSizeInBits() / 8;
switch (VT) {
switch (VT.getSimpleVT()) {
default:
assert(false && "Invalid value type!");
case MVT::i8: {
prefslot_begin = prefslot_end = 3;
break;
@ -2159,12 +2166,12 @@ static SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
SDOperand VecOp = Op.getOperand(0);
SDOperand ValOp = Op.getOperand(1);
SDOperand IdxOp = Op.getOperand(2);
MVT::ValueType VT = Op.getValueType();
MVT VT = Op.getValueType();
ConstantSDNode *CN = cast<ConstantSDNode>(IdxOp);
assert(CN != 0 && "LowerINSERT_VECTOR_ELT: Index is not constant!");
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Use $2 because it's always 16-byte aligned and it's available:
SDOperand PtrBase = DAG.getRegister(SPU::R2, PtrVT);
@ -2270,9 +2277,8 @@ static SDOperand LowerI8Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc)
static SDOperand LowerI64Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc)
{
MVT::ValueType VT = Op.getValueType();
unsigned VecVT =
MVT::getVectorType(VT, (128 / MVT::getSizeInBits(VT)));
MVT VT = Op.getValueType();
MVT VecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
SDOperand Op0 = Op.getOperand(0);
@ -2280,9 +2286,8 @@ static SDOperand LowerI64Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc)
case ISD::ZERO_EXTEND:
case ISD::SIGN_EXTEND:
case ISD::ANY_EXTEND: {
MVT::ValueType Op0VT = Op0.getValueType();
unsigned Op0VecVT =
MVT::getVectorType(Op0VT, (128 / MVT::getSizeInBits(Op0VT)));
MVT Op0VT = Op0.getValueType();
MVT Op0VecVT = MVT::getVectorVT(Op0VT, (128 / Op0VT.getSizeInBits()));
assert(Op0VT == MVT::i32
&& "CellSPU: Zero/sign extending something other than i32");
@ -2361,7 +2366,7 @@ static SDOperand LowerI64Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc)
case ISD::SHL: {
SDOperand ShiftAmt = Op.getOperand(1);
unsigned ShiftAmtVT = unsigned(ShiftAmt.getValueType());
MVT ShiftAmtVT = ShiftAmt.getValueType();
SDOperand Op0Vec = DAG.getNode(SPUISD::PROMOTE_SCALAR, VecVT, Op0);
SDOperand MaskLower =
DAG.getNode(SPUISD::SELB, VecVT,
@ -2386,9 +2391,9 @@ static SDOperand LowerI64Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc)
}
case ISD::SRL: {
unsigned VT = unsigned(Op.getValueType());
MVT VT = Op.getValueType();
SDOperand ShiftAmt = Op.getOperand(1);
unsigned ShiftAmtVT = unsigned(ShiftAmt.getValueType());
MVT ShiftAmtVT = ShiftAmt.getValueType();
SDOperand ShiftAmtBytes =
DAG.getNode(ISD::SRL, ShiftAmtVT,
ShiftAmt,
@ -2409,7 +2414,7 @@ static SDOperand LowerI64Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc)
SDOperand Op0 =
DAG.getNode(SPUISD::PROMOTE_SCALAR, MVT::v2i64, Op.getOperand(0));
SDOperand ShiftAmt = Op.getOperand(1);
unsigned ShiftVT = ShiftAmt.getValueType();
MVT ShiftVT = ShiftAmt.getValueType();
// Negate variable shift amounts
if (!isa<ConstantSDNode>(ShiftAmt)) {
@ -2450,7 +2455,7 @@ static SDOperand
LowerByteImmed(SDOperand Op, SelectionDAG &DAG) {
SDOperand ConstVec;
SDOperand Arg;
MVT::ValueType VT = Op.getValueType();
MVT VT = Op.getValueType();
ConstVec = Op.getOperand(0);
Arg = Op.getOperand(1);
@ -2474,7 +2479,7 @@ LowerByteImmed(SDOperand Op, SelectionDAG &DAG) {
if (!GetConstantBuildVectorBits(ConstVec.Val, VectorBits, UndefBits)
&& isConstantSplat(VectorBits, UndefBits,
MVT::getSizeInBits(MVT::getVectorElementType(VT)),
VT.getVectorElementType().getSizeInBits(),
SplatBits, SplatUndef, SplatSize)) {
SDOperand tcVec[16];
SDOperand tc = DAG.getTargetConstant(SplatBits & 0xff, MVT::i8);
@ -2493,12 +2498,12 @@ LowerByteImmed(SDOperand Op, SelectionDAG &DAG) {
}
//! Lower i32 multiplication
static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG, unsigned VT,
static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG, MVT VT,
unsigned Opc) {
switch (VT) {
switch (VT.getSimpleVT()) {
default:
cerr << "CellSPU: Unknown LowerMUL value type, got "
<< MVT::getValueTypeString(Op.getValueType())
<< Op.getValueType().getMVTString()
<< "\n";
abort();
/*NOTREACHED*/
@ -2525,10 +2530,12 @@ static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG, unsigned VT,
ones per byte, which then have to be accumulated.
*/
static SDOperand LowerCTPOP(SDOperand Op, SelectionDAG &DAG) {
unsigned VT = Op.getValueType();
unsigned vecVT = MVT::getVectorType(VT, (128 / MVT::getSizeInBits(VT)));
MVT VT = Op.getValueType();
MVT vecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
switch (VT) {
switch (VT.getSimpleVT()) {
default:
assert(false && "Invalid value type!");
case MVT::i8: {
SDOperand N = Op.getOperand(0);
SDOperand Elt0 = DAG.getConstant(0, MVT::i32);
@ -2630,7 +2637,7 @@ SDOperand
SPUTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG)
{
unsigned Opc = (unsigned) Op.getOpcode();
unsigned VT = (unsigned) Op.getValueType();
MVT VT = Op.getValueType();
switch (Opc) {
default: {
@ -2704,7 +2711,7 @@ SPUTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG)
// Vector and i8 multiply:
case ISD::MUL:
if (MVT::isVector(VT))
if (VT.isVector())
return LowerVectorMUL(Op, DAG);
else if (VT == MVT::i8)
return LowerI8Math(Op, DAG, Opc);
@ -2911,7 +2918,7 @@ SPUTargetLowering::getConstraintType(const std::string &ConstraintLetter) const
std::pair<unsigned, const TargetRegisterClass*>
SPUTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const
MVT VT) const
{
if (Constraint.size() == 1) {
// GCC RS6000 Constraint Letters
@ -2961,9 +2968,9 @@ SPUTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
case SPUISD::PROMOTE_SCALAR: {
SDOperand Op0 = Op.getOperand(0);
MVT::ValueType Op0VT = Op0.getValueType();
unsigned Op0VTBits = MVT::getSizeInBits(Op0VT);
uint64_t InMask = MVT::getIntVTBitMask(Op0VT);
MVT Op0VT = Op0.getValueType();
unsigned Op0VTBits = Op0VT.getSizeInBits();
uint64_t InMask = Op0VT.getIntegerVTBitMask();
KnownZero |= APInt(Op0VTBits, ~InMask, false);
KnownOne |= APInt(Op0VTBits, InMask, false);
break;
@ -2972,9 +2979,9 @@ SPUTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
case SPUISD::LDRESULT:
case SPUISD::EXTRACT_ELT0:
case SPUISD::EXTRACT_ELT0_CHAINED: {
MVT::ValueType OpVT = Op.getValueType();
unsigned OpVTBits = MVT::getSizeInBits(OpVT);
uint64_t InMask = MVT::getIntVTBitMask(OpVT);
MVT OpVT = Op.getValueType();
unsigned OpVTBits = OpVT.getSizeInBits();
uint64_t InMask = OpVT.getIntegerVTBitMask();
KnownZero |= APInt(OpVTBits, ~InMask, false);
KnownOne |= APInt(OpVTBits, InMask, false);
break;

14
lib/Target/CellSPU/SPUISelLowering.h
View File

@ -79,15 +79,15 @@ namespace llvm {
/// Predicates that are used for node matching:
namespace SPU {
SDOperand get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
MVT::ValueType ValueType);
MVT ValueType);
SDOperand get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
MVT::ValueType ValueType);
MVT ValueType);
SDOperand get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
MVT::ValueType ValueType);
MVT ValueType);
SDOperand get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
MVT::ValueType ValueType);
MVT ValueType);
SDOperand get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
MVT::ValueType ValueType);
MVT ValueType);
SDOperand get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
SDOperand get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
}
@ -109,7 +109,7 @@ namespace llvm {
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - Return the ValueType for ISD::SETCC
virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
virtual MVT getSetCCResultType(const SDOperand &) const;
/// LowerOperation - Provide custom lowering hooks for some operations.
///
@ -128,7 +128,7 @@ namespace llvm {
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
MVT VT) const;
void LowerAsmOperandForConstraint(SDOperand Op, char ConstraintLetter,
std::vector<SDOperand> &Ops,

10
lib/Target/IA64/IA64ISelDAGToDAG.cpp
View File

@ -119,7 +119,7 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
bool isFP=false;
if(MVT::isFloatingPoint(Tmp1.getValueType()))
if(Tmp1.getValueType().isFloatingPoint())
isFP=true;
bool isModulus=false; // is it a division or a modulus?
@ -469,9 +469,9 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
AddToISelQueue(Chain);
AddToISelQueue(Address);
MVT::ValueType TypeBeingLoaded = LD->getMemoryVT();
MVT TypeBeingLoaded = LD->getMemoryVT();
unsigned Opc;
switch (TypeBeingLoaded) {
switch (TypeBeingLoaded.getSimpleVT()) {
default:
#ifndef NDEBUG
N->dump(CurDAG);
@ -511,7 +511,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
unsigned Opc;
if (ISD::isNON_TRUNCStore(N)) {
switch (N->getOperand(1).getValueType()) {
switch (N->getOperand(1).getValueType().getSimpleVT()) {
default: assert(0 && "unknown type in store");
case MVT::i1: { // this is a bool
Opc = IA64::ST1; // we store either 0 or 1 as a byte
@ -531,7 +531,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
case MVT::f64: Opc = IA64::STF8; break;
}
} else { // Truncating store
switch(ST->getMemoryVT()) {
switch(ST->getMemoryVT().getSimpleVT()) {
default: assert(0 && "unknown type in truncstore");
case MVT::i8: Opc = IA64::ST1; break;
case MVT::i16: Opc = IA64::ST2; break;

31
lib/Target/IA64/IA64ISelLowering.cpp
View File

@ -139,8 +139,7 @@ const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const {
}
}
MVT::ValueType
IA64TargetLowering::getSetCCResultType(const SDOperand &) const {
MVT IA64TargetLowering::getSetCCResultType(const SDOperand &) const {
return MVT::i1;
}
@ -181,7 +180,7 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
SDOperand newroot, argt;
if(count < 8) { // need to fix this logic? maybe.
switch (getValueType(I->getType())) {
switch (getValueType(I->getType()).getSimpleVT()) {
default:
assert(0 && "ERROR in LowerArgs: can't lower this type of arg.\n");
case MVT::f32:
@ -286,7 +285,7 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
// Finally, inform the code generator which regs we return values in.
// (see the ISD::RET: case in the instruction selector)
switch (getValueType(F.getReturnType())) {
switch (getValueType(F.getReturnType()).getSimpleVT()) {
default: assert(0 && "i have no idea where to return this type!");
case MVT::isVoid: break;
case MVT::i1:
@ -347,10 +346,10 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
for (unsigned i = 0, e = Args.size(); i != e; ++i)
{
SDOperand Val = Args[i].Node;
MVT::ValueType ObjectVT = Val.getValueType();
MVT ObjectVT = Val.getValueType();
SDOperand ValToStore(0, 0), ValToConvert(0, 0);
unsigned ObjSize=8;
switch (ObjectVT) {
switch (ObjectVT.getSimpleVT()) {
default: assert(0 && "unexpected argument type!");
case MVT::i1:
case MVT::i8:
@ -442,7 +441,7 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
// flagged for now, but shouldn't have to be (TODO)
unsigned seenConverts = 0;
for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
if(MVT::isFloatingPoint(RegValuesToPass[i].getValueType())) {
if(RegValuesToPass[i].getValueType().isFloatingPoint()) {
Chain = DAG.getCopyToReg(Chain, IntArgRegs[i], Converts[seenConverts++],
InFlag);
InFlag = Chain.getValue(1);
@ -453,7 +452,7 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
unsigned usedFPArgs = 0;
for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
Chain = DAG.getCopyToReg(Chain,
MVT::isInteger(RegValuesToPass[i].getValueType()) ?
RegValuesToPass[i].getValueType().isInteger() ?
IntArgRegs[i] : FPArgRegs[usedFPArgs++], RegValuesToPass[i], InFlag);
InFlag = Chain.getValue(1);
}
@ -466,7 +465,7 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
}
*/
std::vector<MVT::ValueType> NodeTys;
std::vector<MVT> NodeTys;
std::vector<SDOperand> CallOperands;
NodeTys.push_back(MVT::Other); // Returns a chain
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
@ -492,14 +491,14 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
Chain = DAG.getCopyToReg(Chain, IA64::rp, RPBeforeCall, InFlag);
InFlag = Chain.getValue(1);
std::vector<MVT::ValueType> RetVals;
std::vector<MVT> RetVals;
RetVals.push_back(MVT::Other);
RetVals.push_back(MVT::Flag);
MVT::ValueType RetTyVT = getValueType(RetTy);
MVT RetTyVT = getValueType(RetTy);
SDOperand RetVal;
if (RetTyVT != MVT::isVoid) {
switch (RetTyVT) {
switch (RetTyVT.getSimpleVT()) {
default: assert(0 && "Unknown value type to return!");
case MVT::i1: { // bools are just like other integers (returned in r8)
// we *could* fall through to the truncate below, but this saves a
@ -573,8 +572,8 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, AR_PFSVal);
case 3: {
// Copy the result into the output register & restore ar.pfs
MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
unsigned ArgReg = MVT::isInteger(ArgVT) ? IA64::r8 : IA64::F8;
MVT ArgVT = Op.getOperand(1).getValueType();
unsigned ArgReg = ArgVT.isInteger() ? IA64::r8 : IA64::F8;
AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64);
Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), ArgReg, Op.getOperand(1),
@ -588,13 +587,13 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
return SDOperand();
}
case ISD::VAARG: {
MVT::ValueType VT = getPointerTy();
MVT VT = getPointerTy();
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1),
SV, 0);
// Increment the pointer, VAList, to the next vaarg
SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList,
DAG.getConstant(MVT::getSizeInBits(VT)/8,
DAG.getConstant(VT.getSizeInBits()/8,
VT));
// Store the incremented VAList to the legalized pointer
VAIncr = DAG.getStore(VAList.getValue(1), VAIncr,

2
lib/Target/IA64/IA64ISelLowering.h
View File

@ -49,7 +49,7 @@ namespace llvm {
const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType: return ISD::SETCC's result type.
virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
virtual MVT getSetCCResultType(const SDOperand &) const;
/// LowerArguments - This hook must be implemented to indicate how we should
/// lower the arguments for the specified function, into the specified DAG.

2
lib/Target/Mips/MipsISelDAGToDAG.cpp
View File

@ -250,7 +250,7 @@ Select(SDOperand N)
AddToISelQueue(LHS);
AddToISelQueue(RHS);
MVT::ValueType VT = LHS.getValueType();
MVT VT = LHS.getValueType();
SDNode *Carry = CurDAG->getTargetNode(Mips::SLTu, VT, Ops, 2);
SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, VT,
SDOperand(Carry,0), RHS);

22
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -108,8 +108,7 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
}
MVT::ValueType
MipsTargetLowering::getSetCCResultType(const SDOperand &) const {
MVT MipsTargetLowering::getSetCCResultType(const SDOperand &) const {
return MVT::i32;
}
@ -223,7 +222,7 @@ LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
SDOperand HiPart;
if (!isPIC) {
const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32);
const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
SDOperand Ops[] = { GA };
HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
} else // Emit Load from Global Pointer
@ -256,7 +255,7 @@ LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG)
SDOperand False = Op.getOperand(3);
SDOperand CC = Op.getOperand(4);
const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32);
const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
SDOperand Ops[] = { LHS, RHS, CC };
SDOperand SetCCRes = DAG.getNode(ISD::SETCC, VTs, 1, Ops, 3);
@ -270,12 +269,12 @@ LowerJumpTable(SDOperand Op, SelectionDAG &DAG)
SDOperand ResNode;
SDOperand HiPart;
MVT::ValueType PtrVT = Op.getValueType();
MVT PtrVT = Op.getValueType();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32);
const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
SDOperand Ops[] = { JTI };
HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
} else // Emit Load from Global Pointer
@ -341,7 +340,7 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
// To meet ABI, Mips must always allocate 16 bytes on
// the stack (even if less than 4 are used as arguments)
int VTsize = MVT::getSizeInBits(MVT::i32)/8;
int VTsize = MVT(MVT::i32).getSizeInBits()/8;
MFI->CreateFixedObject(VTsize, (VTsize*3));
CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
@ -391,7 +390,7 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
// This guarantees that when allocating Local Area the firsts
// 16 bytes which are alwayes reserved won't be overwritten.
LastStackLoc = (16 + VA.getLocMemOffset());
int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
LastStackLoc);
SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy());
@ -575,7 +574,7 @@ LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
// Arguments stored on registers
if (VA.isRegLoc()) {
MVT::ValueType RegVT = VA.getLocVT();
MVT RegVT = VA.getLocVT();
TargetRegisterClass *RC;
if (RegVT == MVT::i32)
@ -738,8 +737,7 @@ getConstraintType(const std::string &Constraint) const
}
std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const
getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
{
if (Constraint.size() == 1) {
switch (Constraint[0]) {
@ -753,7 +751,7 @@ getRegForInlineAsmConstraint(const std::string &Constraint,
std::vector<unsigned> MipsTargetLowering::
getRegClassForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const
MVT VT) const
{
if (Constraint.size() != 1)
return std::vector<unsigned>();

6
lib/Target/Mips/MipsISelLowering.h
View File

@ -66,7 +66,7 @@ namespace llvm {
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - get the ISD::SETCC result ValueType
MVT::ValueType getSetCCResultType(const SDOperand &) const;
MVT getSetCCResultType(const SDOperand &) const;
private:
// Lower Operand helpers
@ -93,11 +93,11 @@ namespace llvm {
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
MVT VT) const;
std::vector<unsigned>
getRegClassForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
MVT VT) const;
};
}

9
lib/Target/PIC16/PIC16ISelLowering.cpp
View File

@ -204,7 +204,7 @@ SDOperand PIC16TargetLowering:: LowerOperation(SDOperand Op, SelectionDAG &DAG)
SDOperand PIC16TargetLowering::LowerBR_CC(SDOperand Op, SelectionDAG &DAG)
{
MVT::ValueType VT = Op.getValueType();
MVT VT = Op.getValueType();
SDOperand Chain = Op.getOperand(0);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
SDOperand LHS = Op.getOperand(2);
@ -278,7 +278,7 @@ SDOperand PIC16TargetLowering::LowerBR_CC(SDOperand Op, SelectionDAG &DAG)
SDOperand
PIC16TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
{
MVT::ValueType PtrVT = getPointerTy();
MVT PtrVT = getPointerTy();
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
GlobalValue *GV = GSDN->getGlobal();
@ -626,7 +626,10 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N,
return Stores[0];
}
switch(Src.getValueType()) {
switch(Src.getValueType().getSimpleVT()) {
default:
assert(false && "Invalid value type!");
case MVT::i8:
break;

6
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -921,7 +921,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
case ISD::LOAD: {
// Handle preincrement loads.
LoadSDNode *LD = cast<LoadSDNode>(Op);
MVT::ValueType LoadedVT = LD->getMemoryVT();
MVT LoadedVT = LD->getMemoryVT();
// Normal loads are handled by code generated from the .td file.
if (LD->getAddressingMode() != ISD::PRE_INC)
@ -936,7 +936,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
if (LD->getValueType(0) != MVT::i64) {
// Handle PPC32 integer and normal FP loads.
assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
switch (LoadedVT) {
switch (LoadedVT.getSimpleVT()) {
default: assert(0 && "Invalid PPC load type!");
case MVT::f64: Opcode = PPC::LFDU; break;
case MVT::f32: Opcode = PPC::LFSU; break;
@ -948,7 +948,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
} else {
assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
switch (LoadedVT) {
switch (LoadedVT.getSimpleVT()) {
default: assert(0 && "Invalid PPC load type!");
case MVT::i64: Opcode = PPC::LDU; break;
case MVT::i32: Opcode = PPC::LWZU8; break;

269
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -256,50 +256,52 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
// First set operation action for all vector types to expand. Then we
// will selectively turn on ones that can be effectively codegen'd.
for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
MVT VT = (MVT::SimpleValueType)i;
// add/sub are legal for all supported vector VT's.
setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
setOperationAction(ISD::ADD , VT, Legal);
setOperationAction(ISD::SUB , VT, Legal);
// We promote all shuffles to v16i8.
setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
// We promote all non-typed operations to v4i32.
setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
setOperationAction(ISD::AND , VT, Promote);
AddPromotedToType (ISD::AND , VT, MVT::v4i32);
setOperationAction(ISD::OR , VT, Promote);
AddPromotedToType (ISD::OR , VT, MVT::v4i32);
setOperationAction(ISD::XOR , VT, Promote);
AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
setOperationAction(ISD::LOAD , VT, Promote);
AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
setOperationAction(ISD::SELECT, VT, Promote);
AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
setOperationAction(ISD::STORE, VT, Promote);
AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
// No other operations are legal.
setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::MUL , VT, Expand);
setOperationAction(ISD::SDIV, VT, Expand);
setOperationAction(ISD::SREM, VT, Expand);
setOperationAction(ISD::UDIV, VT, Expand);
setOperationAction(ISD::UREM, VT, Expand);
setOperationAction(ISD::FDIV, VT, Expand);
setOperationAction(ISD::FNEG, VT, Expand);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
setOperationAction(ISD::UMUL_LOHI, VT, Expand);
setOperationAction(ISD::SMUL_LOHI, VT, Expand);
setOperationAction(ISD::UDIVREM, VT, Expand);
setOperationAction(ISD::SDIVREM, VT, Expand);
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
setOperationAction(ISD::FPOW, VT, Expand);
setOperationAction(ISD::CTPOP, VT, Expand);
setOperationAction(ISD::CTLZ, VT, Expand);
setOperationAction(ISD::CTTZ, VT, Expand);
}
// We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
@ -420,8 +422,7 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
}
MVT::ValueType
PPCTargetLowering::getSetCCResultType(const SDOperand &) const {
MVT PPCTargetLowering::getSetCCResultType(const SDOperand &) const {
return MVT::i32;
}
@ -690,7 +691,7 @@ SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
uint64_t Value = 0;
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
Value = CN->getValue();
ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
ValSizeInBytes = CN->getValueType(0).getSizeInBits()/8;
} else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
Value = FloatToBits(CN->getValueAPF().convertToFloat());
@ -1007,7 +1008,7 @@ bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
if (!EnablePPCPreinc) return false;
SDOperand Ptr;
MVT::ValueType VT;
MVT VT;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
Ptr = LD->getBasePtr();
VT = LD->getMemoryVT();
@ -1020,7 +1021,7 @@ bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
return false;
// PowerPC doesn't have preinc load/store instructions for vectors.
if (MVT::isVector(VT))
if (VT.isVector())
return false;
// TODO: Check reg+reg first.
@ -1055,7 +1056,7 @@ bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
SDOperand PPCTargetLowering::LowerConstantPool(SDOperand Op,
SelectionDAG &DAG) {
MVT::ValueType PtrVT = Op.getValueType();
MVT PtrVT = Op.getValueType();
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
Constant *C = CP->getConstVal();
SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
@ -1086,7 +1087,7 @@ SDOperand PPCTargetLowering::LowerConstantPool(SDOperand Op,
}
SDOperand PPCTargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
MVT::ValueType PtrVT = Op.getValueType();
MVT PtrVT = Op.getValueType();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
SDOperand Zero = DAG.getConstant(0, PtrVT);
@ -1123,7 +1124,7 @@ SDOperand PPCTargetLowering::LowerGlobalTLSAddress(SDOperand Op,
SDOperand PPCTargetLowering::LowerGlobalAddress(SDOperand Op,
SelectionDAG &DAG) {
MVT::ValueType PtrVT = Op.getValueType();
MVT PtrVT = Op.getValueType();
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
GlobalValue *GV = GSDN->getGlobal();
SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
@ -1170,13 +1171,13 @@ SDOperand PPCTargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
// fold the new nodes.
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
if (C->isNullValue() && CC == ISD::SETEQ) {
MVT::ValueType VT = Op.getOperand(0).getValueType();
MVT VT = Op.getOperand(0).getValueType();
SDOperand Zext = Op.getOperand(0);
if (VT < MVT::i32) {
VT = MVT::i32;
Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
}
unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
unsigned Log2b = Log2_32(VT.getSizeInBits());
SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
DAG.getConstant(Log2b, MVT::i32));
@ -1194,9 +1195,9 @@ SDOperand PPCTargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
// condition register, reading it back out, and masking the correct bit. The
// normal approach here uses sub to do this instead of xor. Using xor exposes
// the result to other bit-twiddling opportunities.
MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
MVT::ValueType VT = Op.getValueType();
MVT LHSVT = Op.getOperand(0).getValueType();
if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
MVT VT = Op.getValueType();
SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
Op.getOperand(1));
return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
@ -1225,7 +1226,7 @@ SDOperand PPCTargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG,
if (Subtarget.isMachoABI()) {
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
@ -1260,15 +1261,15 @@ SDOperand PPCTargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG,
SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
SDOperand StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
uint64_t FrameOffset = MVT::getSizeInBits(PtrVT)/8;
uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
SDOperand ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
uint64_t StackOffset = MVT::getSizeInBits(PtrVT)/8 - 1;
uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
SDOperand ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
uint64_t FPROffset = 1;
@ -1325,9 +1326,9 @@ static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
/// the stack.
static unsigned CalculateStackSlotSize(SDOperand Arg, SDOperand Flag,
bool isVarArg, unsigned PtrByteSize) {
MVT::ValueType ArgVT = Arg.getValueType();
MVT ArgVT = Arg.getValueType();
ISD::ArgFlagsTy Flags = cast<ARG_FLAGSSDNode>(Flag)->getArgFlags();
unsigned ArgSize =MVT::getSizeInBits(ArgVT)/8;
unsigned ArgSize =ArgVT.getSizeInBits()/8;
if (Flags.isByVal())
ArgSize = Flags.getByValSize();
ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
@ -1352,7 +1353,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op,
SDOperand Root = Op.getOperand(0);
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
bool isPPC64 = PtrVT == MVT::i64;
bool isMachoABI = Subtarget.isMachoABI();
bool isELF32_ABI = Subtarget.isELF32_ABI();
@ -1402,8 +1403,8 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op,
if (!isVarArg && !isPPC64) {
for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e;
++ArgNo) {
MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
MVT ObjectVT = Op.getValue(ArgNo).getValueType();
unsigned ObjSize = ObjectVT.getSizeInBits()/8;
ISD::ArgFlagsTy Flags =
cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags();
@ -1416,7 +1417,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op,
continue;
}
switch(ObjectVT) {
switch(ObjectVT.getSimpleVT()) {
default: assert(0 && "Unhandled argument type!");
case MVT::i32:
case MVT::f32:
@ -1453,8 +1454,8 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op,
for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
SDOperand ArgVal;
bool needsLoad = false;
MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
MVT ObjectVT = Op.getValue(ArgNo).getValueType();
unsigned ObjSize = ObjectVT.getSizeInBits()/8;
unsigned ArgSize = ObjSize;
ISD::ArgFlagsTy Flags =
cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags();
@ -1535,7 +1536,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op,
continue;
}
switch (ObjectVT) {
switch (ObjectVT.getSimpleVT()) {
default: assert(0 && "Unhandled argument type!");
case MVT::i32:
if (!isPPC64) {
@ -1693,18 +1694,18 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op,
// Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame
// pointer.
depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 +
Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 +
MVT::getSizeInBits(PtrVT)/8);
depth = -(Num_GPR_Regs * PtrVT.getSizeInBits()/8 +
Num_FPR_Regs * MVT(MVT::f64).getSizeInBits()/8 +
PtrVT.getSizeInBits()/8);
VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
ArgOffset);
}
else
depth = ArgOffset;
VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
depth);
SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
@ -1716,7 +1717,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op,
SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
MemOps.push_back(Store);
// Increment the address by four for the next argument to store
SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
SDOperand PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
}
}
@ -1736,7 +1737,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op,
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
MemOps.push_back(Store);
// Increment the address by four for the next argument to store
SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
SDOperand PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
}
@ -1748,7 +1749,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op,
SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
MemOps.push_back(Store);
// Increment the address by eight for the next argument to store
SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
SDOperand PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
PtrVT);
FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
}
@ -1762,7 +1763,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op,
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
MemOps.push_back(Store);
// Increment the address by eight for the next argument to store
SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
SDOperand PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
PtrVT);
FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
}
@ -1775,7 +1776,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op,
ArgValues.push_back(Root);
// Return the new list of results.
std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
std::vector<MVT> RetVT(Op.Val->value_begin(),
Op.Val->value_end());
return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
}
@ -1807,7 +1808,7 @@ CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
for (unsigned i = 0; i != NumOps; ++i) {
SDOperand Arg = Call.getOperand(5+2*i);
SDOperand Flag = Call.getOperand(5+2*i+1);
MVT::ValueType ArgVT = Arg.getValueType();
MVT ArgVT = Arg.getValueType();
// Varargs Altivec parameters are padded to a 16 byte boundary.
if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
@ -1970,7 +1971,7 @@ static SDOperand EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
isMachoABI);
int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc);
MVT::ValueType VT = isPPC64 ? MVT::i64 : MVT::i32;
MVT VT = isPPC64 ? MVT::i64 : MVT::i32;
SDOperand NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
Chain = DAG.getStore(Chain, OldRetAddr, NewRetAddrFrIdx,
PseudoSourceValue::getFixedStack(), NewRetAddr);
@ -1988,9 +1989,9 @@ CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
SDOperand Arg, int SPDiff, unsigned ArgOffset,
SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
int Offset = ArgOffset + SPDiff;
uint32_t OpSize = (MVT::getSizeInBits(Arg.getValueType())+7)/8;
uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
MVT::ValueType VT = isPPC64 ? MVT::i64 : MVT::i32;
MVT VT = isPPC64 ? MVT::i64 : MVT::i32;
SDOperand FIN = DAG.getFrameIndex(FI, VT);
TailCallArgumentInfo Info;
Info.Arg = Arg;
@ -2009,7 +2010,7 @@ SDOperand PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
SDOperand &FPOpOut) {
if (SPDiff) {
// Load the LR and FP stack slot for later adjusting.
MVT::ValueType VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
MVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
LROpOut = getReturnAddrFrameIndex(DAG);
LROpOut = DAG.getLoad(VT, Chain, LROpOut, NULL, 0);
Chain = SDOperand(LROpOut.Val, 1);
@ -2043,7 +2044,7 @@ LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDOperand Chain,
unsigned ArgOffset, bool isPPC64, bool isTailCall,
bool isVector, SmallVector<SDOperand, 8> &MemOpChains,
SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
if (!isTailCall) {
if (isVector) {
SDOperand StackPtr;
@ -2074,7 +2075,7 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG,
bool isMachoABI = Subtarget.isMachoABI();
bool isELF32_ABI = Subtarget.isELF32_ABI();
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
bool isPPC64 = PtrVT == MVT::i64;
unsigned PtrByteSize = isPPC64 ? 8 : 4;
@ -2192,7 +2193,7 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG,
if (Size==1 || Size==2) {
// Very small objects are passed right-justified.
// Everything else is passed left-justified.
MVT::ValueType VT = (Size==1) ? MVT::i8 : MVT::i16;
MVT VT = (Size==1) ? MVT::i8 : MVT::i16;
if (GPR_idx != NumGPRs) {
SDOperand Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, Chain, Arg,
NULL, 0, VT);
@ -2244,7 +2245,7 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG,
continue;
}
switch (Arg.getValueType()) {
switch (Arg.getValueType().getSimpleVT()) {
default: assert(0 && "Unexpected ValueType for argument!");
case MVT::i32:
case MVT::i64:
@ -2384,7 +2385,7 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG,
ArgOffset += 12*16;
for (unsigned i = 0; i != NumOps; ++i) {
SDOperand Arg = Op.getOperand(5+2*i);
MVT::ValueType ArgType = Arg.getValueType();
MVT ArgType = Arg.getValueType();
if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
if (++j > NumVRs) {
@ -2450,7 +2451,7 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG,
InFlag = Chain.getValue(1);
}
std::vector<MVT::ValueType> NodeTys;
std::vector<MVT> NodeTys;
NodeTys.push_back(MVT::Other); // Returns a chain
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
@ -2544,7 +2545,7 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG,
// Copy all of the result registers out of their specified physreg.
for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
CCValAssign &VA = RVLocs[i];
MVT::ValueType VT = VA.getValVT();
MVT VT = VA.getValVT();
assert(VA.isRegLoc() && "Can only return in registers!");
Chain = DAG.getCopyFromReg(Chain, VA.getLocReg(), VT, InFlag).getValue(1);
ResultVals.push_back(Chain.getValue(0));
@ -2629,7 +2630,7 @@ SDOperand PPCTargetLowering::LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG,
// When we pop the dynamic allocation we need to restore the SP link.
// Get the corect type for pointers.
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Construct the stack pointer operand.
bool IsPPC64 = Subtarget.isPPC64();
@ -2657,7 +2658,7 @@ PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
MachineFunction &MF = DAG.getMachineFunction();
bool IsPPC64 = PPCSubTarget.isPPC64();
bool isMachoABI = PPCSubTarget.isMachoABI();
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Get current frame pointer save index. The users of this index will be
// primarily DYNALLOC instructions.
@ -2681,7 +2682,7 @@ PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
MachineFunction &MF = DAG.getMachineFunction();
bool IsPPC64 = PPCSubTarget.isPPC64();
bool isMachoABI = PPCSubTarget.isMachoABI();
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Get current frame pointer save index. The users of this index will be
// primarily DYNALLOC instructions.
@ -2709,7 +2710,7 @@ SDOperand PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
SDOperand Size = Op.getOperand(1);
// Get the corect type for pointers.
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Negate the size.
SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT,
DAG.getConstant(0, PtrVT), Size);
@ -2722,13 +2723,13 @@ SDOperand PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
}
SDOperand PPCTargetLowering::LowerAtomicLAS(SDOperand Op, SelectionDAG &DAG) {
MVT::ValueType VT = Op.Val->getValueType(0);
MVT VT = Op.Val->getValueType(0);
SDOperand Chain = Op.getOperand(0);
SDOperand Ptr = Op.getOperand(1);
SDOperand Incr = Op.getOperand(2);
// Issue a "load and reserve".
std::vector<MVT::ValueType> VTs;
std::vector<MVT> VTs;
VTs.push_back(VT);
VTs.push_back(MVT::Other);
@ -2758,14 +2759,14 @@ SDOperand PPCTargetLowering::LowerAtomicLAS(SDOperand Op, SelectionDAG &DAG) {
}
SDOperand PPCTargetLowering::LowerAtomicLCS(SDOperand Op, SelectionDAG &DAG) {
MVT::ValueType VT = Op.Val->getValueType(0);
MVT VT = Op.Val->getValueType(0);
SDOperand Chain = Op.getOperand(0);
SDOperand Ptr = Op.getOperand(1);
SDOperand NewVal = Op.getOperand(2);
SDOperand OldVal = Op.getOperand(3);
// Issue a "load and reserve".
std::vector<MVT::ValueType> VTs;
std::vector<MVT> VTs;
VTs.push_back(VT);
VTs.push_back(MVT::Other);
@ -2801,13 +2802,13 @@ SDOperand PPCTargetLowering::LowerAtomicLCS(SDOperand Op, SelectionDAG &DAG) {
}
SDOperand PPCTargetLowering::LowerAtomicSWAP(SDOperand Op, SelectionDAG &DAG) {
MVT::ValueType VT = Op.Val->getValueType(0);
MVT VT = Op.Val->getValueType(0);
SDOperand Chain = Op.getOperand(0);
SDOperand Ptr = Op.getOperand(1);
SDOperand NewVal = Op.getOperand(2);
// Issue a "load and reserve".
std::vector<MVT::ValueType> VTs;
std::vector<MVT> VTs;
VTs.push_back(VT);
VTs.push_back(MVT::Other);
@ -2837,8 +2838,8 @@ SDOperand PPCTargetLowering::LowerAtomicSWAP(SDOperand Op, SelectionDAG &DAG) {
/// possible.
SDOperand PPCTargetLowering::LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
// Not FP? Not a fsel.
if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
!MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
!Op.getOperand(2).getValueType().isFloatingPoint())
return SDOperand();
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
@ -2846,8 +2847,8 @@ SDOperand PPCTargetLowering::LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
// Cannot handle SETEQ/SETNE.
if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
MVT::ValueType ResVT = Op.getValueType();
MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
MVT ResVT = Op.getValueType();
MVT CmpVT = Op.getOperand(0).getValueType();
SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
@ -2916,13 +2917,13 @@ SDOperand PPCTargetLowering::LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
// FIXME: Split this code up when LegalizeDAGTypes lands.
SDOperand PPCTargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
assert(Op.getOperand(0).getValueType().isFloatingPoint());
SDOperand Src = Op.getOperand(0);
if (Src.getValueType() == MVT::f32)
Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
SDOperand Tmp;
switch (Op.getValueType()) {
switch (Op.getValueType().getSimpleVT()) {
default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
case MVT::i32:
Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
@ -2958,7 +2959,7 @@ SDOperand PPCTargetLowering::LowerFP_ROUND_INREG(SDOperand Op,
// This sequence changes FPSCR to do round-to-zero, adds the two halves
// of the long double, and puts FPSCR back the way it was. We do not
// actually model FPSCR.
std::vector<MVT::ValueType> NodeTys;
std::vector<MVT> NodeTys;
SDOperand Ops[4], Result, MFFSreg, InFlag, FPreg;
NodeTys.push_back(MVT::f64); // Return register
@ -3026,7 +3027,7 @@ SDOperand PPCTargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
// then lfd it and fcfid it.
MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
int FrameIdx = FrameInfo->CreateStackObject(8, 8);
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
@ -3069,9 +3070,9 @@ SDOperand PPCTargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) {
*/
MachineFunction &MF = DAG.getMachineFunction();
MVT::ValueType VT = Op.getValueType();
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
std::vector<MVT::ValueType> NodeTys;
MVT VT = Op.getValueType();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
std::vector<MVT> NodeTys;
SDOperand MFFSreg, InFlag;
// Save FP Control Word to register
@ -3105,13 +3106,13 @@ SDOperand PPCTargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) {
SDOperand RetVal =
DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2);
return DAG.getNode((MVT::getSizeInBits(VT) < 16 ?
return DAG.getNode((VT.getSizeInBits() < 16 ?
ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
}
SDOperand PPCTargetLowering::LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
MVT::ValueType VT = Op.getValueType();
unsigned BitWidth = MVT::getSizeInBits(VT);
MVT VT = Op.getValueType();
unsigned BitWidth = VT.getSizeInBits();
assert(Op.getNumOperands() == 3 &&
VT == Op.getOperand(1).getValueType() &&
"Unexpected SHL!");
@ -3121,7 +3122,7 @@ SDOperand PPCTargetLowering::LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
SDOperand Lo = Op.getOperand(0);
SDOperand Hi = Op.getOperand(1);
SDOperand Amt = Op.getOperand(2);
MVT::ValueType AmtVT = Amt.getValueType();
MVT AmtVT = Amt.getValueType();
SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
DAG.getConstant(BitWidth, AmtVT), Amt);
@ -3139,8 +3140,8 @@ SDOperand PPCTargetLowering::LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
}
SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
MVT::ValueType VT = Op.getValueType();
unsigned BitWidth = MVT::getSizeInBits(VT);
MVT VT = Op.getValueType();
unsigned BitWidth = VT.getSizeInBits();
assert(Op.getNumOperands() == 3 &&
VT == Op.getOperand(1).getValueType() &&
"Unexpected SRL!");
@ -3150,7 +3151,7 @@ SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
SDOperand Lo = Op.getOperand(0);
SDOperand Hi = Op.getOperand(1);
SDOperand Amt = Op.getOperand(2);
MVT::ValueType AmtVT = Amt.getValueType();
MVT AmtVT = Amt.getValueType();
SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
DAG.getConstant(BitWidth, AmtVT), Amt);
@ -3168,8 +3169,8 @@ SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
}
SDOperand PPCTargetLowering::LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
MVT::ValueType VT = Op.getValueType();
unsigned BitWidth = MVT::getSizeInBits(VT);
MVT VT = Op.getValueType();
unsigned BitWidth = VT.getSizeInBits();
assert(Op.getNumOperands() == 3 &&
VT == Op.getOperand(1).getValueType() &&
"Unexpected SRA!");
@ -3178,7 +3179,7 @@ SDOperand PPCTargetLowering::LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
SDOperand Lo = Op.getOperand(0);
SDOperand Hi = Op.getOperand(1);
SDOperand Amt = Op.getOperand(2);
MVT::ValueType AmtVT = Amt.getValueType();
MVT AmtVT = Amt.getValueType();
SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
DAG.getConstant(BitWidth, AmtVT), Amt);
@ -3210,7 +3211,7 @@ static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
// Start with zero'd results.
VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
unsigned EltBitSize = BV->getOperand(0).getValueType().getSizeInBits();
for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
SDOperand OpVal = BV->getOperand(i);
@ -3296,26 +3297,26 @@ static bool isConstantSplat(const uint64_t Bits128[2],
/// BuildSplatI - Build a canonical splati of Val with an element size of
/// SplatSize. Cast the result to VT.
static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT VT,
SelectionDAG &DAG) {
assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
static const MVT VTys[] = { // canonical VT to use for each size.
MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
};
MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
MVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
// Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
if (Val == -1)
SplatSize = 1;
MVT::ValueType CanonicalVT = VTys[SplatSize-1];
MVT CanonicalVT = VTys[SplatSize-1];
// Build a canonical splat for this value.
SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT));
SDOperand Elt = DAG.getConstant(Val, CanonicalVT.getVectorElementType());
SmallVector<SDOperand, 8> Ops;
Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
&Ops[0], Ops.size());
return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res);
@ -3325,7 +3326,7 @@ static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
/// specified intrinsic ID.
static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
SelectionDAG &DAG,
MVT::ValueType DestVT = MVT::Other) {
MVT DestVT = MVT::Other) {
if (DestVT == MVT::Other) DestVT = LHS.getValueType();
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
DAG.getConstant(IID, MVT::i32), LHS, RHS);
@ -3335,7 +3336,7 @@ static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
/// specified intrinsic ID.
static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
SDOperand Op2, SelectionDAG &DAG,
MVT::ValueType DestVT = MVT::Other) {
MVT DestVT = MVT::Other) {
if (DestVT == MVT::Other) DestVT = Op0.getValueType();
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
@ -3345,7 +3346,7 @@ static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
/// amount. The result has the specified value type.
static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
MVT::ValueType VT, SelectionDAG &DAG) {
MVT VT, SelectionDAG &DAG) {
// Force LHS/RHS to be the right type.
LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
@ -3705,8 +3706,8 @@ SDOperand PPCTargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op,
// The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
// that it is in input element units, not in bytes. Convert now.
MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType());
unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
MVT EltVT = V1.getValueType().getVectorElementType();
unsigned BytesPerElement = EltVT.getSizeInBits()/8;
SmallVector<SDOperand, 16> ResultMask;
for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
@ -3794,7 +3795,7 @@ SDOperand PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op,
Op.getOperand(3), // RHS
DAG.getConstant(CompareOpc, MVT::i32)
};
std::vector<MVT::ValueType> VTs;
std::vector<MVT> VTs;
VTs.push_back(Op.getOperand(2).getValueType());
VTs.push_back(MVT::Flag);
SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
@ -3843,7 +3844,7 @@ SDOperand PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op,
// Create a stack slot that is 16-byte aligned.
MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
int FrameIdx = FrameInfo->CreateStackObject(16, 16);
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
// Store the input value into Value#0 of the stack slot.
@ -4154,7 +4155,7 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
SDOperand Load = N->getOperand(0);
LoadSDNode *LD = cast<LoadSDNode>(Load);
// Create the byte-swapping load.
std::vector<MVT::ValueType> VTs;
std::vector<MVT> VTs;
VTs.push_back(MVT::i32);
VTs.push_back(MVT::Other);
SDOperand MO = DAG.getMemOperand(LD->getMemOperand());
@ -4264,7 +4265,7 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
// Create the PPCISD altivec 'dot' comparison node.
std::vector<MVT::ValueType> VTs;
std::vector<MVT> VTs;
SDOperand Ops[] = {
LHS.getOperand(2), // LHS of compare
LHS.getOperand(3), // RHS of compare
@ -4367,7 +4368,7 @@ PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
std::pair<unsigned, const TargetRegisterClass*>
PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const {
MVT VT) const {
if (Constraint.size() == 1) {
// GCC RS6000 Constraint Letters
switch (Constraint[0]) {
@ -4527,7 +4528,7 @@ SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
return SDOperand();
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
bool isPPC64 = PtrVT == MVT::i64;
MachineFunction &MF = DAG.getMachineFunction();

4
lib/Target/PowerPC/PPCISelLowering.h
View File

@ -235,7 +235,7 @@ namespace llvm {
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - Return the ISD::SETCC ValueType
virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
virtual MVT getSetCCResultType(const SDOperand &) const;
/// getPreIndexedAddressParts - returns true by value, base pointer and
/// offset pointer and addressing mode by reference if the node's address
@ -290,7 +290,7 @@ namespace llvm {
ConstraintType getConstraintType(const std::string &Constraint) const;
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
MVT VT) const;
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
/// function arguments in the caller parameter area. This is the actual

24
lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -91,9 +91,9 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
std::vector<SDOperand> OutChains;
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
MVT::ValueType ObjectVT = getValueType(I->getType());
MVT ObjectVT = getValueType(I->getType());
switch (ObjectVT) {
switch (ObjectVT.getSimpleVT()) {
default: assert(0 && "Unhandled argument type!");
case MVT::i1:
case MVT::i8:
@ -123,7 +123,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
// Sparc is big endian, so add an offset based on the ObjectVT.
unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
unsigned Offset = 4-std::max(1U, ObjectVT.getSizeInBits()/8);
FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
DAG.getConstant(Offset, MVT::i32));
Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
@ -246,7 +246,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
// Count the size of the outgoing arguments.
unsigned ArgsSize = 0;
for (unsigned i = 5, e = Op.getNumOperands(); i != e; i += 2) {
switch (Op.getOperand(i).getValueType()) {
switch (Op.getOperand(i).getValueType().getSimpleVT()) {
default: assert(0 && "Unknown value type!");
case MVT::i1:
case MVT::i8:
@ -323,10 +323,10 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
for (unsigned i = 5, e = Op.getNumOperands(); i != e; i += 2) {
SDOperand Val = Op.getOperand(i);
MVT::ValueType ObjectVT = Val.getValueType();
MVT ObjectVT = Val.getValueType();
SDOperand ValToStore(0, 0);
unsigned ObjSize;
switch (ObjectVT) {
switch (ObjectVT.getSimpleVT()) {
default: assert(0 && "Unhandled argument type!");
case MVT::i32:
ObjSize = 4;
@ -414,7 +414,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
std::vector<MVT::ValueType> NodeTys;
std::vector<MVT> NodeTys;
NodeTys.push_back(MVT::Other); // Returns a chain
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
SDOperand Ops[] = { Chain, Callee, InFlag };
@ -744,7 +744,7 @@ static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
// Get the condition flag.
SDOperand CompareFlag;
if (LHS.getValueType() == MVT::i32) {
std::vector<MVT::ValueType> VTs;
std::vector<MVT> VTs;
VTs.push_back(MVT::i32);
VTs.push_back(MVT::Flag);
SDOperand Ops[2] = { LHS, RHS };
@ -774,7 +774,7 @@ static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
SDOperand CompareFlag;
if (LHS.getValueType() == MVT::i32) {
std::vector<MVT::ValueType> VTs;
std::vector<MVT> VTs;
VTs.push_back(LHS.getValueType()); // subcc returns a value
VTs.push_back(MVT::Flag);
SDOperand Ops[2] = { LHS, RHS };
@ -804,14 +804,14 @@ static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG) {
SDNode *Node = Op.Val;
MVT::ValueType VT = Node->getValueType(0);
MVT VT = Node->getValueType(0);
SDOperand InChain = Node->getOperand(0);
SDOperand VAListPtr = Node->getOperand(1);
const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
SDOperand VAList = DAG.getLoad(MVT::i32, InChain, VAListPtr, SV, 0);
// Increment the pointer, VAList, to the next vaarg
SDOperand NextPtr = DAG.getNode(ISD::ADD, MVT::i32, VAList,
DAG.getConstant(MVT::getSizeInBits(VT)/8,
DAG.getConstant(VT.getSizeInBits()/8,
MVT::i32));
// Store the incremented VAList to the legalized pointer
InChain = DAG.getStore(VAList.getValue(1), NextPtr,
@ -846,7 +846,7 @@ static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG) {
// to provide a register spill area.
SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
DAG.getConstant(96, MVT::i32));
std::vector<MVT::ValueType> Tys;
std::vector<MVT> Tys;
Tys.push_back(MVT::i32);
Tys.push_back(MVT::Other);
SDOperand Ops[2] = { NewVal, Chain };

3
lib/Target/TargetRegisterInfo.cpp
View File

@ -48,8 +48,7 @@ namespace {
/// register of the given type. If type is MVT::Other, then just return any
/// register class the register belongs to.
const TargetRegisterClass *
TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg,
MVT::ValueType VT) const {
TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, MVT VT) const {
assert(isPhysicalRegister(reg) && "reg must be a physical register");
// Pick the register class of the right type that contains this physreg.

8
lib/Target/TargetSelectionDAG.td
View File

@ -53,8 +53,8 @@ class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
/// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
/// vector types, and that ThisOp is the result of
/// MVT::getIntVectorWithNumElements with the number of elements that ThisOp
/// has.
/// MVT::getIntVectorWithNumElements with the number of elements
/// that ThisOp has.
class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp>
: SDTypeConstraint<ThisOp> {
int OtherOpNum = OtherOp;
@ -467,8 +467,8 @@ class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
// Leaf fragments.
def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>;
def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
def immAllOnesV: PatLeaf<(build_vector), [{

2
lib/Target/X86/X86ATTAsmPrinter.cpp
View File

@ -215,7 +215,7 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
O << '%';
unsigned Reg = MO.getReg();
if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
MVT::ValueType VT = (strcmp(Modifier+6,"64") == 0) ?
MVT VT = (strcmp(Modifier+6,"64") == 0) ?
MVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? MVT::i32 :
((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
Reg = getX86SubSuperRegister(Reg, VT);

60
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -215,7 +215,7 @@ namespace {
/// getTruncate - return an SDNode that implements a subreg based truncate
/// of the specified operand to the the specified value type.
SDNode *getTruncate(SDOperand N0, MVT::ValueType VT);
SDNode *getTruncate(SDOperand N0, MVT VT);
#ifndef NDEBUG
unsigned Indent;
@ -329,7 +329,7 @@ bool X86DAGToDAGISel::CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const {
// NU), then TF is a predecessor of FU and a successor of NU. But since
// NU and FU are flagged together, this effectively creates a cycle.
bool HasFlagUse = false;
MVT::ValueType VT = Root->getValueType(Root->getNumValues()-1);
MVT VT = Root->getValueType(Root->getNumValues()-1);
while ((VT == MVT::Flag && !Root->use_empty())) {
SDNode *FU = findFlagUse(Root);
if (FU == NULL)
@ -440,8 +440,8 @@ void X86DAGToDAGISel::PreprocessForRMW(SelectionDAG &DAG) {
SDOperand N1 = I->getOperand(1);
SDOperand N2 = I->getOperand(2);
if ((MVT::isFloatingPoint(N1.getValueType()) &&
!MVT::isVector(N1.getValueType())) ||
if ((N1.getValueType().isFloatingPoint() &&
!N1.getValueType().isVector()) ||
!N1.hasOneUse())
continue;
@ -505,8 +505,8 @@ void X86DAGToDAGISel::PreprocessForFPConvert(SelectionDAG &DAG) {
// If the source and destination are SSE registers, then this is a legal
// conversion that should not be lowered.
MVT::ValueType SrcVT = N->getOperand(0).getValueType();
MVT::ValueType DstVT = N->getValueType(0);
MVT SrcVT = N->getOperand(0).getValueType();
MVT DstVT = N->getValueType(0);
bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT);
bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT);
if (SrcIsSSE && DstIsSSE)
@ -524,7 +524,7 @@ void X86DAGToDAGISel::PreprocessForFPConvert(SelectionDAG &DAG) {
// Here we could have an FP stack truncation or an FPStack <-> SSE convert.
// FPStack has extload and truncstore. SSE can fold direct loads into other
// operations. Based on this, decide what we want to do.
MVT::ValueType MemVT;
MVT MemVT;
if (N->getOpcode() == ISD::FP_ROUND)
MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
else
@ -942,7 +942,7 @@ bool X86DAGToDAGISel::SelectAddr(SDOperand Op, SDOperand N, SDOperand &Base,
if (MatchAddress(N, AM))
return false;
MVT::ValueType VT = N.getValueType();
MVT VT = N.getValueType();
if (AM.BaseType == X86ISelAddressMode::RegBase) {
if (!AM.Base.Reg.Val)
AM.Base.Reg = CurDAG->getRegister(0, VT);
@ -1016,7 +1016,7 @@ bool X86DAGToDAGISel::SelectLEAAddr(SDOperand Op, SDOperand N,
if (MatchAddress(N, AM))
return false;
MVT::ValueType VT = N.getValueType();
MVT VT = N.getValueType();
unsigned Complexity = 0;
if (AM.BaseType == X86ISelAddressMode::RegBase)
if (AM.Base.Reg.Val)
@ -1110,16 +1110,17 @@ static SDNode *FindCallStartFromCall(SDNode *Node) {
return FindCallStartFromCall(Node->getOperand(0).Val);
}
SDNode *X86DAGToDAGISel::getTruncate(SDOperand N0, MVT::ValueType VT) {
SDNode *X86DAGToDAGISel::getTruncate(SDOperand N0, MVT VT) {
SDOperand SRIdx;
switch (VT) {
switch (VT.getSimpleVT()) {
default: assert(0 && "Unknown truncate!");
case MVT::i8:
SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
// Ensure that the source register has an 8-bit subreg on 32-bit targets
if (!Subtarget->is64Bit()) {
unsigned Opc;
MVT::ValueType VT;
switch (N0.getValueType()) {
MVT VT;
switch (N0.getValueType().getSimpleVT()) {
default: assert(0 && "Unknown truncate!");
case MVT::i16:
Opc = X86::MOV16to16_;
@ -1141,7 +1142,6 @@ SDNode *X86DAGToDAGISel::getTruncate(SDOperand N0, MVT::ValueType VT) {
case MVT::i32:
SRIdx = CurDAG->getTargetConstant(3, MVT::i32); // SubRegSet 3
break;
default: assert(0 && "Unknown truncate!"); break;
}
return CurDAG->getTargetNode(X86::EXTRACT_SUBREG, VT, N0, SRIdx);
}
@ -1149,7 +1149,7 @@ SDNode *X86DAGToDAGISel::getTruncate(SDOperand N0, MVT::ValueType VT) {
SDNode *X86DAGToDAGISel::Select(SDOperand N) {
SDNode *Node = N.Val;
MVT::ValueType NVT = Node->getValueType(0);
MVT NVT = Node->getValueType(0);
unsigned Opc, MOpc;
unsigned Opcode = Node->getOpcode();
@ -1183,7 +1183,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
// RIP-relative addressing.
if (TM.getCodeModel() != CodeModel::Small)
break;
MVT::ValueType PtrVT = TLI.getPointerTy();
MVT PtrVT = TLI.getPointerTy();
SDOperand N0 = N.getOperand(0);
SDOperand N1 = N.getOperand(1);
if (N.Val->getValueType(0) == PtrVT &&
@ -1224,7 +1224,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
bool isSigned = Opcode == ISD::SMUL_LOHI;
if (!isSigned)
switch (NVT) {
switch (NVT.getSimpleVT()) {
default: assert(0 && "Unsupported VT!");
case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
@ -1232,7 +1232,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
}
else
switch (NVT) {
switch (NVT.getSimpleVT()) {
default: assert(0 && "Unsupported VT!");
case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
@ -1241,7 +1241,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
}
unsigned LoReg, HiReg;
switch (NVT) {
switch (NVT.getSimpleVT()) {
default: assert(0 && "Unsupported VT!");
case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
@ -1334,7 +1334,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
bool isSigned = Opcode == ISD::SDIVREM;
if (!isSigned)
switch (NVT) {
switch (NVT.getSimpleVT()) {
default: assert(0 && "Unsupported VT!");
case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
@ -1342,7 +1342,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
}
else
switch (NVT) {
switch (NVT.getSimpleVT()) {
default: assert(0 && "Unsupported VT!");
case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
@ -1352,7 +1352,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
unsigned LoReg, HiReg;
unsigned ClrOpcode, SExtOpcode;
switch (NVT) {
switch (NVT.getSimpleVT()) {
default: assert(0 && "Unsupported VT!");
case MVT::i8:
LoReg = X86::AL; HiReg = X86::AH;
@ -1493,7 +1493,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
SDOperand N0 = Node->getOperand(0);
// Get the subregsiter index for the type to extend.
MVT::ValueType N0VT = N0.getValueType();
MVT N0VT = N0.getValueType();
unsigned Idx = (N0VT == MVT::i32) ? X86::SUBREG_32BIT :
(N0VT == MVT::i16) ? X86::SUBREG_16BIT :
(Subtarget->is64Bit()) ? X86::SUBREG_8BIT : 0;
@ -1523,30 +1523,30 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
SDOperand N0 = Node->getOperand(0);
AddToISelQueue(N0);
MVT::ValueType SVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
MVT SVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
SDOperand TruncOp = SDOperand(getTruncate(N0, SVT), 0);
unsigned Opc = 0;
switch (NVT) {
switch (NVT.getSimpleVT()) {
default: assert(0 && "Unknown sign_extend_inreg!");
case MVT::i16:
if (SVT == MVT::i8) Opc = X86::MOVSX16rr8;
else assert(0 && "Unknown sign_extend_inreg!");
break;
case MVT::i32:
switch (SVT) {
switch (SVT.getSimpleVT()) {
default: assert(0 && "Unknown sign_extend_inreg!");
case MVT::i8: Opc = X86::MOVSX32rr8; break;
case MVT::i16: Opc = X86::MOVSX32rr16; break;
default: assert(0 && "Unknown sign_extend_inreg!");
}
break;
case MVT::i64:
switch (SVT) {
switch (SVT.getSimpleVT()) {
default: assert(0 && "Unknown sign_extend_inreg!");
case MVT::i8: Opc = X86::MOVSX64rr8; break;
case MVT::i16: Opc = X86::MOVSX64rr16; break;
case MVT::i32: Opc = X86::MOVSX64rr32; break;
default: assert(0 && "Unknown sign_extend_inreg!");
}
break;
default: assert(0 && "Unknown sign_extend_inreg!");
}
SDNode *ResNode = CurDAG->getTargetNode(Opc, NVT, TruncOp);

476
lib/Target/X86/X86ISelLowering.cpp
View File

File diff suppressed because it is too large Load Diff

23
lib/Target/X86/X86ISelLowering.h
View File

@ -345,8 +345,8 @@ namespace llvm {
/// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
/// determining it.
virtual
MVT::ValueType getOptimalMemOpType(uint64_t Size, unsigned Align,
bool isSrcConst, bool isSrcStr) const;
MVT getOptimalMemOpType(uint64_t Size, unsigned Align,
bool isSrcConst, bool isSrcStr) const;
/// LowerOperation - Provide custom lowering hooks for some operations.
///
@ -369,7 +369,7 @@ namespace llvm {
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - Return the ISD::SETCC ValueType
virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
virtual MVT getSetCCResultType(const SDOperand &) const;
/// computeMaskedBitsForTargetNode - Determine which of the bits specified
/// in Mask are known to be either zero or one and return them in the
@ -390,9 +390,9 @@ namespace llvm {
std::vector<unsigned>
getRegClassForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
MVT VT) const;
virtual const char *LowerXConstraint(MVT::ValueType ConstraintVT) const;
virtual const char *LowerXConstraint(MVT ConstraintVT) const;
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops.
@ -407,7 +407,7 @@ namespace llvm {
/// error, this returns a register number of 0.
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
MVT VT) const;
/// isLegalAddressingMode - Return true if the addressing mode represented
/// by AM is legal for this target, for a load/store of the specified type.
@ -417,26 +417,25 @@ namespace llvm {
/// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
/// register EAX to i16 by referencing its sub-register AX.
virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
virtual bool isTruncateFree(MVT::ValueType VT1, MVT::ValueType VT2) const;
virtual bool isTruncateFree(MVT VT1, MVT VT2) const;
/// isShuffleMaskLegal - Targets can use this to indicate that they only
/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask
/// values are assumed to be legal.
virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const;
virtual bool isShuffleMaskLegal(SDOperand Mask, MVT VT) const;
/// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
/// used by Targets can use this to indicate if there is a suitable
/// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
/// pool entry.
virtual bool isVectorClearMaskLegal(const std::vector<SDOperand> &BVOps,
MVT::ValueType EVT,
SelectionDAG &DAG) const;
MVT EVT, SelectionDAG &DAG) const;
/// ShouldShrinkFPConstant - If true, then instruction selection should
/// seek to shrink the FP constant of the specified type to a smaller type
/// in order to save space and / or reduce runtime.
virtual bool ShouldShrinkFPConstant(MVT::ValueType VT) const {
virtual bool ShouldShrinkFPConstant(MVT VT) const {
// Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
// expensive than a straight movsd. On the other hand, it's important to
// shrink long double fp constant since fldt is very slow.
@ -456,7 +455,7 @@ namespace llvm {
/// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
/// computed in an SSE register, not on the X87 floating point stack.
bool isScalarFPTypeInSSEReg(MVT::ValueType VT) const {
bool isScalarFPTypeInSSEReg(MVT VT) const {
return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
(VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
}

6
lib/Target/X86/X86InstrInfo.cpp
View File

@ -2193,14 +2193,14 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
// Emit the load instruction.
SDNode *Load = 0;
if (FoldedLoad) {
MVT::ValueType VT = *RC->vt_begin();
MVT VT = *RC->vt_begin();
Load = DAG.getTargetNode(getLoadRegOpcode(RC, RI.getStackAlignment()), VT,
MVT::Other, &AddrOps[0], AddrOps.size());
NewNodes.push_back(Load);
}
// Emit the data processing instruction.
std::vector<MVT::ValueType> VTs;
std::vector<MVT> VTs;
const TargetRegisterClass *DstRC = 0;
if (TID.getNumDefs() > 0) {
const TargetOperandInfo &DstTOI = TID.OpInfo[0];
@ -2209,7 +2209,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
VTs.push_back(*DstRC->vt_begin());
}
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
MVT::ValueType VT = N->getValueType(i);
MVT VT = N->getValueType(i);
if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
VTs.push_back(VT);
}

2
lib/Target/X86/X86IntelAsmPrinter.cpp
View File

@ -120,7 +120,7 @@ void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
unsigned Reg = MO.getReg();
if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
MVT::ValueType VT = (strcmp(Modifier,"subreg64") == 0) ?
MVT VT = (strcmp(Modifier,"subreg64") == 0) ?
MVT::i64 : ((strcmp(Modifier, "subreg32") == 0) ? MVT::i32 :
((strcmp(Modifier,"subreg16") == 0) ? MVT::i16 :MVT::i8));
Reg = getX86SubSuperRegister(Reg, VT);

4
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -946,8 +946,8 @@ unsigned X86RegisterInfo::getEHHandlerRegister() const {
}
namespace llvm {
unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
switch (VT) {
unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) {
switch (VT.getSimpleVT()) {
default: return Reg;
case MVT::i8:
if (High) {

2
lib/Target/X86/X86RegisterInfo.h
View File

@ -150,7 +150,7 @@ public:
// getX86SubSuperRegister - X86 utility function. It returns the sub or super
// register of a specific X86 register.
// e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) return X86:AX
unsigned getX86SubSuperRegister(unsigned, MVT::ValueType, bool High=false);
unsigned getX86SubSuperRegister(unsigned, MVT, bool High=false);
} // End llvm namespace

6
lib/Transforms/Scalar/CodeGenPrepare.cpp
View File

@ -333,11 +333,11 @@ static void SplitEdgeNicely(TerminatorInst *TI, unsigned SuccNum, Pass *P) {
/// Return true if any changes are made.
static bool OptimizeNoopCopyExpression(CastInst *CI, const TargetLowering &TLI){
// If this is a noop copy,
MVT::ValueType SrcVT = TLI.getValueType(CI->getOperand(0)->getType());
MVT::ValueType DstVT = TLI.getValueType(CI->getType());
MVT SrcVT = TLI.getValueType(CI->getOperand(0)->getType());
MVT DstVT = TLI.getValueType(CI->getType());
// This is an fp<->int conversion?
if (MVT::isInteger(SrcVT) != MVT::isInteger(DstVT))
if (SrcVT.isInteger() != DstVT.isInteger())
return false;
// If this is an extension, it will be a zero or sign extension, which

2
lib/VMCore/Function.cpp
View File

@ -336,7 +336,7 @@ std::string Intrinsic::getName(ID id, const Type **Tys, unsigned numTys) {
std::string Result(Table[id]);
for (unsigned i = 0; i < numTys; ++i)
if (Tys[i])
Result += "." + MVT::getValueTypeString(MVT::getValueType(Tys[i]));
Result += "." + MVT::getMVT(Tys[i]).getMVTString();
return Result;
}

62
lib/VMCore/ValueTypes.cpp
View File

@ -1,4 +1,4 @@
//===-- ValueTypes.cpp - Implementation of MVT::ValueType methods ---------===//
//===----------- ValueTypes.cpp - Implementation of MVT methods -----------===//
//
// The LLVM Compiler Infrastructure
//
@ -17,17 +17,17 @@
#include "llvm/DerivedTypes.h"
using namespace llvm;
/// MVT::getValueTypeString - This function returns value type as a string,
/// e.g. "i32".
std::string MVT::getValueTypeString(MVT::ValueType VT) {
switch (VT) {
/// getMVTString - This function returns value type as a string, e.g. "i32".
std::string MVT::getMVTString() const {
switch (V) {
default:
if (isVector(VT))
return "v" + utostr(getVectorNumElements(VT)) +
getValueTypeString(getVectorElementType(VT));
if (isInteger(VT))
return "i" + utostr(getSizeInBits(VT));
assert(0 && "Invalid ValueType!");
if (isVector())
return "v" + utostr(getVectorNumElements()) +
getVectorElementType().getMVTString();
if (isInteger())
return "i" + utostr(getSizeInBits());
assert(0 && "Invalid MVT!");
return "?";
case MVT::i1: return "i1";
case MVT::i8: return "i8";
case MVT::i16: return "i16";
@ -58,19 +58,20 @@ std::string MVT::getValueTypeString(MVT::ValueType VT) {
}
}
/// MVT::getTypeForValueType - This method returns an LLVM type corresponding
/// to the specified ValueType. Note that this will abort for types that cannot
/// be represented.
const Type *MVT::getTypeForValueType(MVT::ValueType VT) {
switch (VT) {
/// getTypeForMVT - This method returns an LLVM type corresponding to the
/// specified MVT. For integer types, this returns an unsigned type. Note
/// that this will abort for types that cannot be represented.
const Type *MVT::getTypeForMVT() const {
switch (V) {
default:
if (isVector(VT))
return VectorType::get(getTypeForValueType(getVectorElementType(VT)),
getVectorNumElements(VT));
if (isInteger(VT))
return IntegerType::get(getSizeInBits(VT));
assert(0 && "ValueType does not correspond to LLVM type!");
case MVT::isVoid:return Type::VoidTy;
if (isVector())
return VectorType::get(getVectorElementType().getTypeForMVT(),
getVectorNumElements());
if (isInteger())
return IntegerType::get(getSizeInBits());
assert(0 && "MVT does not correspond to LLVM type!");
return Type::VoidTy;
case MVT::isVoid: return Type::VoidTy;
case MVT::i1: return Type::Int1Ty;
case MVT::i8: return Type::Int8Ty;
case MVT::i16: return Type::Int16Ty;
@ -98,18 +99,19 @@ const Type *MVT::getTypeForValueType(MVT::ValueType VT) {
}
}
/// MVT::getValueType - Return the value type corresponding to the specified
/// type. This returns all pointers as MVT::iPTR. If HandleUnknown is true,
/// unknown types are returned as Other, otherwise they are invalid.
MVT::ValueType MVT::getValueType(const Type *Ty, bool HandleUnknown) {
/// getMVT - Return the value type corresponding to the specified type. This
/// returns all pointers as MVT::iPTR. If HandleUnknown is true, unknown types
/// are returned as Other, otherwise they are invalid.
MVT MVT::getMVT(const Type *Ty, bool HandleUnknown){
switch (Ty->getTypeID()) {
default:
if (HandleUnknown) return MVT::Other;
assert(0 && "Unknown type!");
return MVT::isVoid;
case Type::VoidTyID:
return MVT::isVoid;
case Type::IntegerTyID:
return getIntegerType(cast<IntegerType>(Ty)->getBitWidth());
return getIntegerVT(cast<IntegerType>(Ty)->getBitWidth());
case Type::FloatTyID: return MVT::f32;
case Type::DoubleTyID: return MVT::f64;
case Type::X86_FP80TyID: return MVT::f80;
@ -118,8 +120,8 @@ MVT::ValueType MVT::getValueType(const Type *Ty, bool HandleUnknown) {
case Type::PointerTyID: return MVT::iPTR;
case Type::VectorTyID: {
const VectorType *VTy = cast<VectorType>(Ty);
return getVectorType(getValueType(VTy->getElementType(), false),
VTy->getNumElements());
return getVectorVT(getMVT(VTy->getElementType(), false),
VTy->getNumElements());
}
}
}

17
lib/VMCore/Verifier.cpp
View File

@ -1331,7 +1331,7 @@ void Verifier::VerifyIntrinsicPrototype(Intrinsic::ID ID,
// Note that "arg#0" is the return type.
for (unsigned ArgNo = 0; ArgNo < Count; ++ArgNo) {
MVT::ValueType VT = va_arg(VA, MVT::ValueType);
int VT = va_arg(VA, int); // An MVT::SimpleValueType when non-negative.
if (VT == MVT::isVoid && ArgNo > 0) {
if (!FTy->isVarArg())
@ -1351,8 +1351,8 @@ void Verifier::VerifyIntrinsicPrototype(Intrinsic::ID ID,
EltTy = VTy->getElementType();
NumElts = VTy->getNumElements();
}
if ((int)VT < 0) {
if (VT < 0) {
int Match = ~VT;
if (Match == 0) {
if (Ty != FTy->getReturnType()) {
@ -1403,7 +1403,7 @@ void Verifier::VerifyIntrinsicPrototype(Intrinsic::ID ID,
Suffix += ".";
if (EltTy != Ty)
Suffix += "v" + utostr(NumElts);
Suffix += MVT::getValueTypeString(MVT::getValueType(EltTy));
Suffix += MVT::getMVT(EltTy).getMVTString();
} else if (VT == MVT::iPTR) {
if (!isa<PointerType>(Ty)) {
if (ArgNo == 0)
@ -1414,19 +1414,20 @@ void Verifier::VerifyIntrinsicPrototype(Intrinsic::ID ID,
"pointer and a pointer is required.", F);
break;
}
} else if (MVT::isVector(VT)) {
} else if (MVT((MVT::SimpleValueType)VT).isVector()) {
MVT VVT = MVT((MVT::SimpleValueType)VT);
// If this is a vector argument, verify the number and type of elements.
if (MVT::getVectorElementType(VT) != MVT::getValueType(EltTy)) {
if (VVT.getVectorElementType() != MVT::getMVT(EltTy)) {
CheckFailed("Intrinsic prototype has incorrect vector element type!",
F);
break;
}
if (MVT::getVectorNumElements(VT) != NumElts) {
if (VVT.getVectorNumElements() != NumElts) {
CheckFailed("Intrinsic prototype has incorrect number of "
"vector elements!",F);
break;
}
} else if (MVT::getTypeForValueType(VT) != EltTy) {
} else if (MVT((MVT::SimpleValueType)VT).getTypeForMVT() != EltTy) {
if (ArgNo == 0)
CheckFailed("Intrinsic prototype has incorrect result type!", F);
else

12
utils/TableGen/CallingConvEmitter.cpp
View File

@ -26,9 +26,9 @@ void CallingConvEmitter::run(std::ostream &O) {
// other.
for (unsigned i = 0, e = CCs.size(); i != e; ++i) {
O << "static bool " << CCs[i]->getName()
<< "(unsigned ValNo, MVT::ValueType ValVT,\n"
<< "(unsigned ValNo, MVT ValVT,\n"
<< std::string(CCs[i]->getName().size()+13, ' ')
<< "MVT::ValueType LocVT, CCValAssign::LocInfo LocInfo,\n"
<< "MVT LocVT, CCValAssign::LocInfo LocInfo,\n"
<< std::string(CCs[i]->getName().size()+13, ' ')
<< "ISD::ArgFlagsTy ArgFlags, CCState &State);\n";
}
@ -44,9 +44,9 @@ void CallingConvEmitter::EmitCallingConv(Record *CC, std::ostream &O) {
Counter = 0;
O << "\n\nstatic bool " << CC->getName()
<< "(unsigned ValNo, MVT::ValueType ValVT,\n"
<< "(unsigned ValNo, MVT ValVT,\n"
<< std::string(CC->getName().size()+13, ' ')
<< "MVT::ValueType LocVT, CCValAssign::LocInfo LocInfo,\n"
<< "MVT LocVT, CCValAssign::LocInfo LocInfo,\n"
<< std::string(CC->getName().size()+13, ' ')
<< "ISD::ArgFlagsTy ArgFlags, CCState &State) {\n";
// Emit all of the actions, in order.
@ -163,12 +163,12 @@ void CallingConvEmitter::EmitAction(Record *Action,
O << Size << ", ";
else
O << "\n" << IndentStr << " State.getTarget().getTargetData()"
"->getABITypeSize(MVT::getTypeForValueType(LocVT)), ";
"->getABITypeSize(LocVT.getTypeForMVT()), ";
if (Align)
O << Align;
else
O << "\n" << IndentStr << " State.getTarget().getTargetData()"
"->getABITypeAlignment(MVT::getTypeForValueType(LocVT))";
"->getABITypeAlignment(LocVT.getTypeForMVT())";
O << ");\n" << IndentStr
<< "State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset"
<< Counter << ", LocVT, LocInfo));\n";

163
utils/TableGen/CodeGenDAGPatterns.cpp
View File

@ -27,9 +27,9 @@ using namespace llvm;
/// FilterVTs - Filter a list of VT's according to a predicate.
///
template<typename T>
static std::vector<MVT::ValueType>
FilterVTs(const std::vector<MVT::ValueType> &InVTs, T Filter) {
std::vector<MVT::ValueType> Result;
static std::vector<MVT::SimpleValueType>
FilterVTs(const std::vector<MVT::SimpleValueType> &InVTs, T Filter) {
std::vector<MVT::SimpleValueType> Result;
for (unsigned i = 0, e = InVTs.size(); i != e; ++i)
if (Filter(InVTs[i]))
Result.push_back(InVTs[i]);
@ -41,19 +41,31 @@ static std::vector<unsigned char>
FilterEVTs(const std::vector<unsigned char> &InVTs, T Filter) {
std::vector<unsigned char> Result;
for (unsigned i = 0, e = InVTs.size(); i != e; ++i)
if (Filter((MVT::ValueType)InVTs[i]))
if (Filter((MVT::SimpleValueType)InVTs[i]))
Result.push_back(InVTs[i]);
return Result;
}
static std::vector<unsigned char>
ConvertVTs(const std::vector<MVT::ValueType> &InVTs) {
ConvertVTs(const std::vector<MVT::SimpleValueType> &InVTs) {
std::vector<unsigned char> Result;
for (unsigned i = 0, e = InVTs.size(); i != e; ++i)
Result.push_back(InVTs[i]);
return Result;
}
static inline bool isInteger(MVT::SimpleValueType VT) {
return MVT(VT).isInteger();
}
static inline bool isFloatingPoint(MVT::SimpleValueType VT) {
return MVT(VT).isFloatingPoint();
}
static inline bool isVector(MVT::SimpleValueType VT) {
return MVT(VT).isVector();
}
static bool LHSIsSubsetOfRHS(const std::vector<unsigned char> &LHS,
const std::vector<unsigned char> &RHS) {
if (LHS.size() > RHS.size()) return false;
@ -66,7 +78,7 @@ static bool LHSIsSubsetOfRHS(const std::vector<unsigned char> &LHS,
/// isExtIntegerVT - Return true if the specified extended value type vector
/// contains isInt or an integer value type.
namespace llvm {
namespace MVT {
namespace EMVT {
bool isExtIntegerInVTs(const std::vector<unsigned char> &EVTs) {
assert(!EVTs.empty() && "Cannot check for integer in empty ExtVT list!");
return EVTs[0] == isInt || !(FilterEVTs(EVTs, isInteger).empty());
@ -78,7 +90,7 @@ bool isExtFloatingPointInVTs(const std::vector<unsigned char> &EVTs) {
assert(!EVTs.empty() && "Cannot check for integer in empty ExtVT list!");
return EVTs[0] == isFP || !(FilterEVTs(EVTs, isFloatingPoint).empty());
}
} // end namespace MVT.
} // end namespace EMVT.
} // end namespace llvm.
@ -223,23 +235,23 @@ bool SDTypeConstraint::ApplyTypeConstraint(TreePatternNode *N,
}
case SDTCisInt: {
// If there is only one integer type supported, this must be it.
std::vector<MVT::ValueType> IntVTs =
FilterVTs(CGT.getLegalValueTypes(), MVT::isInteger);
std::vector<MVT::SimpleValueType> IntVTs =
FilterVTs(CGT.getLegalValueTypes(), isInteger);
// If we found exactly one supported integer type, apply it.
if (IntVTs.size() == 1)
return NodeToApply->UpdateNodeType(IntVTs[0], TP);
return NodeToApply->UpdateNodeType(MVT::isInt, TP);
return NodeToApply->UpdateNodeType(EMVT::isInt, TP);
}
case SDTCisFP: {
// If there is only one FP type supported, this must be it.
std::vector<MVT::ValueType> FPVTs =
FilterVTs(CGT.getLegalValueTypes(), MVT::isFloatingPoint);
std::vector<MVT::SimpleValueType> FPVTs =
FilterVTs(CGT.getLegalValueTypes(), isFloatingPoint);
// If we found exactly one supported FP type, apply it.
if (FPVTs.size() == 1)
return NodeToApply->UpdateNodeType(FPVTs[0], TP);
return NodeToApply->UpdateNodeType(MVT::isFP, TP);
return NodeToApply->UpdateNodeType(EMVT::isFP, TP);
}
case SDTCisSameAs: {
TreePatternNode *OtherNode =
@ -255,9 +267,9 @@ bool SDTypeConstraint::ApplyTypeConstraint(TreePatternNode *N,
!static_cast<DefInit*>(NodeToApply->getLeafValue())->getDef()
->isSubClassOf("ValueType"))
TP.error(N->getOperator()->getName() + " expects a VT operand!");
MVT::ValueType VT =
MVT::SimpleValueType VT =
getValueType(static_cast<DefInit*>(NodeToApply->getLeafValue())->getDef());
if (!MVT::isInteger(VT))
if (!isInteger(VT))
TP.error(N->getOperator()->getName() + " VT operand must be integer!");
TreePatternNode *OtherNode =
@ -265,7 +277,7 @@ bool SDTypeConstraint::ApplyTypeConstraint(TreePatternNode *N,
// It must be integer.
bool MadeChange = false;
MadeChange |= OtherNode->UpdateNodeType(MVT::isInt, TP);
MadeChange |= OtherNode->UpdateNodeType(EMVT::isInt, TP);
// This code only handles nodes that have one type set. Assert here so
// that we can change this if we ever need to deal with multiple value
@ -285,26 +297,26 @@ bool SDTypeConstraint::ApplyTypeConstraint(TreePatternNode *N,
// This code does not currently handle nodes which have multiple types,
// where some types are integer, and some are fp. Assert that this is not
// the case.
assert(!(MVT::isExtIntegerInVTs(NodeToApply->getExtTypes()) &&
MVT::isExtFloatingPointInVTs(NodeToApply->getExtTypes())) &&
!(MVT::isExtIntegerInVTs(BigOperand->getExtTypes()) &&
MVT::isExtFloatingPointInVTs(BigOperand->getExtTypes())) &&
assert(!(EMVT::isExtIntegerInVTs(NodeToApply->getExtTypes()) &&
EMVT::isExtFloatingPointInVTs(NodeToApply->getExtTypes())) &&
!(EMVT::isExtIntegerInVTs(BigOperand->getExtTypes()) &&
EMVT::isExtFloatingPointInVTs(BigOperand->getExtTypes())) &&
"SDTCisOpSmallerThanOp does not handle mixed int/fp types!");
if (MVT::isExtIntegerInVTs(NodeToApply->getExtTypes()))
MadeChange |= BigOperand->UpdateNodeType(MVT::isInt, TP);
else if (MVT::isExtFloatingPointInVTs(NodeToApply->getExtTypes()))
MadeChange |= BigOperand->UpdateNodeType(MVT::isFP, TP);
if (MVT::isExtIntegerInVTs(BigOperand->getExtTypes()))
MadeChange |= NodeToApply->UpdateNodeType(MVT::isInt, TP);
else if (MVT::isExtFloatingPointInVTs(BigOperand->getExtTypes()))
MadeChange |= NodeToApply->UpdateNodeType(MVT::isFP, TP);
if (EMVT::isExtIntegerInVTs(NodeToApply->getExtTypes()))
MadeChange |= BigOperand->UpdateNodeType(EMVT::isInt, TP);
else if (EMVT::isExtFloatingPointInVTs(NodeToApply->getExtTypes()))
MadeChange |= BigOperand->UpdateNodeType(EMVT::isFP, TP);
if (EMVT::isExtIntegerInVTs(BigOperand->getExtTypes()))
MadeChange |= NodeToApply->UpdateNodeType(EMVT::isInt, TP);
else if (EMVT::isExtFloatingPointInVTs(BigOperand->getExtTypes()))
MadeChange |= NodeToApply->UpdateNodeType(EMVT::isFP, TP);
std::vector<MVT::ValueType> VTs = CGT.getLegalValueTypes();
if (MVT::isExtIntegerInVTs(NodeToApply->getExtTypes())) {
VTs = FilterVTs(VTs, MVT::isInteger);
} else if (MVT::isExtFloatingPointInVTs(NodeToApply->getExtTypes())) {
VTs = FilterVTs(VTs, MVT::isFloatingPoint);
std::vector<MVT::SimpleValueType> VTs = CGT.getLegalValueTypes();
if (EMVT::isExtIntegerInVTs(NodeToApply->getExtTypes())) {
VTs = FilterVTs(VTs, isInteger);
} else if (EMVT::isExtFloatingPointInVTs(NodeToApply->getExtTypes())) {
VTs = FilterVTs(VTs, isFloatingPoint);
} else {
VTs.clear();
}
@ -331,11 +343,12 @@ bool SDTypeConstraint::ApplyTypeConstraint(TreePatternNode *N,
getOperandNum(x.SDTCisIntVectorOfSameSize_Info.OtherOperandNum,
N, NumResults);
if (OtherOperand->hasTypeSet()) {
if (!MVT::isVector(OtherOperand->getTypeNum(0)))
if (!isVector(OtherOperand->getTypeNum(0)))
TP.error(N->getOperator()->getName() + " VT operand must be a vector!");
MVT::ValueType IVT = OtherOperand->getTypeNum(0);
IVT = MVT::getIntVectorWithNumElements(MVT::getVectorNumElements(IVT));
return NodeToApply->UpdateNodeType(IVT, TP);
MVT IVT = OtherOperand->getTypeNum(0);
unsigned NumElements = IVT.getVectorNumElements();
IVT = MVT::getIntVectorWithNumElements(NumElements);
return NodeToApply->UpdateNodeType(IVT.getSimpleVT(), TP);
}
return false;
}
@ -344,11 +357,11 @@ bool SDTypeConstraint::ApplyTypeConstraint(TreePatternNode *N,
getOperandNum(x.SDTCisIntVectorOfSameSize_Info.OtherOperandNum,
N, NumResults);
if (OtherOperand->hasTypeSet()) {
if (!MVT::isVector(OtherOperand->getTypeNum(0)))
if (!isVector(OtherOperand->getTypeNum(0)))
TP.error(N->getOperator()->getName() + " VT operand must be a vector!");
MVT::ValueType IVT = OtherOperand->getTypeNum(0);
IVT = MVT::getVectorElementType(IVT);
return NodeToApply->UpdateNodeType(IVT, TP);
MVT IVT = OtherOperand->getTypeNum(0);
IVT = IVT.getVectorElementType();
return NodeToApply->UpdateNodeType(IVT.getSimpleVT(), TP);
}
return false;
}
@ -421,7 +434,7 @@ bool TreePatternNode::UpdateNodeType(const std::vector<unsigned char> &ExtVTs,
TreePattern &TP) {
assert(!ExtVTs.empty() && "Cannot update node type with empty type vector!");
if (ExtVTs[0] == MVT::isUnknown || LHSIsSubsetOfRHS(getExtTypes(), ExtVTs))
if (ExtVTs[0] == EMVT::isUnknown || LHSIsSubsetOfRHS(getExtTypes(), ExtVTs))
return false;
if (isTypeCompletelyUnknown() || LHSIsSubsetOfRHS(ExtVTs, getExtTypes())) {
setTypes(ExtVTs);
@ -429,10 +442,10 @@ bool TreePatternNode::UpdateNodeType(const std::vector<unsigned char> &ExtVTs,
}
if (getExtTypeNum(0) == MVT::iPTR) {
if (ExtVTs[0] == MVT::iPTR || ExtVTs[0] == MVT::isInt)
if (ExtVTs[0] == MVT::iPTR || ExtVTs[0] == EMVT::isInt)
return false;
if (MVT::isExtIntegerInVTs(ExtVTs)) {
std::vector<unsigned char> FVTs = FilterEVTs(ExtVTs, MVT::isInteger);
if (EMVT::isExtIntegerInVTs(ExtVTs)) {
std::vector<unsigned char> FVTs = FilterEVTs(ExtVTs, isInteger);
if (FVTs.size()) {
setTypes(ExtVTs);
return true;
@ -440,17 +453,17 @@ bool TreePatternNode::UpdateNodeType(const std::vector<unsigned char> &ExtVTs,
}
}
if (ExtVTs[0] == MVT::isInt && MVT::isExtIntegerInVTs(getExtTypes())) {
if (ExtVTs[0] == EMVT::isInt && EMVT::isExtIntegerInVTs(getExtTypes())) {
assert(hasTypeSet() && "should be handled above!");
std::vector<unsigned char> FVTs = FilterEVTs(getExtTypes(), MVT::isInteger);
std::vector<unsigned char> FVTs = FilterEVTs(getExtTypes(), isInteger);
if (getExtTypes() == FVTs)
return false;
setTypes(FVTs);
return true;
}
if (ExtVTs[0] == MVT::iPTR && MVT::isExtIntegerInVTs(getExtTypes())) {
if (ExtVTs[0] == MVT::iPTR && EMVT::isExtIntegerInVTs(getExtTypes())) {
//assert(hasTypeSet() && "should be handled above!");
std::vector<unsigned char> FVTs = FilterEVTs(getExtTypes(), MVT::isInteger);
std::vector<unsigned char> FVTs = FilterEVTs(getExtTypes(), isInteger);
if (getExtTypes() == FVTs)
return false;
if (FVTs.size()) {
@ -458,10 +471,10 @@ bool TreePatternNode::UpdateNodeType(const std::vector<unsigned char> &ExtVTs,
return true;
}
}
if (ExtVTs[0] == MVT::isFP && MVT::isExtFloatingPointInVTs(getExtTypes())) {
if (ExtVTs[0] == EMVT::isFP && EMVT::isExtFloatingPointInVTs(getExtTypes())) {
assert(hasTypeSet() && "should be handled above!");
std::vector<unsigned char> FVTs =
FilterEVTs(getExtTypes(), MVT::isFloatingPoint);
FilterEVTs(getExtTypes(), isFloatingPoint);
if (getExtTypes() == FVTs)
return false;
setTypes(FVTs);
@ -473,12 +486,14 @@ bool TreePatternNode::UpdateNodeType(const std::vector<unsigned char> &ExtVTs,
//
// Similarly, we should probably set the type here to the intersection of
// {isInt|isFP} and ExtVTs
if ((getExtTypeNum(0) == MVT::isInt && MVT::isExtIntegerInVTs(ExtVTs)) ||
(getExtTypeNum(0) == MVT::isFP && MVT::isExtFloatingPointInVTs(ExtVTs))){
if ((getExtTypeNum(0) == EMVT::isInt &&
EMVT::isExtIntegerInVTs(ExtVTs)) ||
(getExtTypeNum(0) == EMVT::isFP &&
EMVT::isExtFloatingPointInVTs(ExtVTs))) {
setTypes(ExtVTs);
return true;
}
if (getExtTypeNum(0) == MVT::isInt && ExtVTs[0] == MVT::iPTR) {
if (getExtTypeNum(0) == EMVT::isInt && ExtVTs[0] == MVT::iPTR) {
setTypes(ExtVTs);
return true;
}
@ -506,9 +521,9 @@ void TreePatternNode::print(std::ostream &OS) const {
// nodes that are multiply typed.
switch (getExtTypeNum(0)) {
case MVT::Other: OS << ":Other"; break;
case MVT::isInt: OS << ":isInt"; break;
case MVT::isFP : OS << ":isFP"; break;
case MVT::isUnknown: ; /*OS << ":?";*/ break;
case EMVT::isInt: OS << ":isInt"; break;
case EMVT::isFP : OS << ":isFP"; break;
case EMVT::isUnknown: ; /*OS << ":?";*/ break;
case MVT::iPTR: OS << ":iPTR"; break;
default: {
std::string VTName = llvm::getName(getTypeNum(0));
@ -672,7 +687,7 @@ TreePatternNode *TreePatternNode::InlinePatternFragments(TreePattern &TP) {
static std::vector<unsigned char> getImplicitType(Record *R, bool NotRegisters,
TreePattern &TP) {
// Some common return values
std::vector<unsigned char> Unknown(1, MVT::isUnknown);
std::vector<unsigned char> Unknown(1, EMVT::isUnknown);
std::vector<unsigned char> Other(1, MVT::Other);
// Check to see if this is a register or a register class...
@ -740,27 +755,29 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
return UpdateNodeType(getImplicitType(DI->getDef(), NotRegisters, TP),TP);
} else if (IntInit *II = dynamic_cast<IntInit*>(getLeafValue())) {
// Int inits are always integers. :)
bool MadeChange = UpdateNodeType(MVT::isInt, TP);
bool MadeChange = UpdateNodeType(EMVT::isInt, TP);
if (hasTypeSet()) {
// At some point, it may make sense for this tree pattern to have
// multiple types. Assert here that it does not, so we revisit this
// code when appropriate.
assert(getExtTypes().size() >= 1 && "TreePattern doesn't have a type!");
MVT::ValueType VT = getTypeNum(0);
MVT::SimpleValueType VT = getTypeNum(0);
for (unsigned i = 1, e = getExtTypes().size(); i != e; ++i)
assert(getTypeNum(i) == VT && "TreePattern has too many types!");
VT = getTypeNum(0);
if (VT != MVT::iPTR) {
unsigned Size = MVT::getSizeInBits(VT);
unsigned Size = MVT(VT).getSizeInBits();
// Make sure that the value is representable for this type.
if (Size < 32) {
int Val = (II->getValue() << (32-Size)) >> (32-Size);
if (Val != II->getValue()) {
// If sign-extended doesn't fit, does it fit as unsigned?
unsigned ValueMask = unsigned(MVT::getIntVTBitMask(VT));
unsigned UnsignedVal = unsigned(II->getValue());
unsigned ValueMask;
unsigned UnsignedVal;
ValueMask = unsigned(MVT(VT).getIntegerVTBitMask());
UnsignedVal = unsigned(II->getValue());
if ((ValueMask & UnsignedVal) != UnsignedVal) {
TP.error("Integer value '" + itostr(II->getValue())+
@ -803,10 +820,10 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
return MadeChange;
} else if (const CodeGenIntrinsic *Int = getIntrinsicInfo(CDP)) {
bool MadeChange = false;
// Apply the result type to the node.
MadeChange = UpdateNodeType(Int->ArgVTs[0], TP);
if (getNumChildren() != Int->ArgVTs.size())
TP.error("Intrinsic '" + Int->Name + "' expects " +
utostr(Int->ArgVTs.size()-1) + " operands, not " +
@ -816,7 +833,7 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
MadeChange |= getChild(0)->UpdateNodeType(MVT::iPTR, TP);
for (unsigned i = 1, e = getNumChildren(); i != e; ++i) {
MVT::ValueType OpVT = Int->ArgVTs[i];
MVT::SimpleValueType OpVT = Int->ArgVTs[i];
MadeChange |= getChild(i)->UpdateNodeType(OpVT, TP);
MadeChange |= getChild(i)->ApplyTypeConstraints(TP, NotRegisters);
}
@ -838,11 +855,11 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
if (getOperator()->getName() == "vector_shuffle" &&
getChild(2)->getOperator()->getName() == "build_vector") {
TreePatternNode *BV = getChild(2);
const std::vector<MVT::ValueType> &LegalVTs
const std::vector<MVT::SimpleValueType> &LegalVTs
= CDP.getTargetInfo().getLegalValueTypes();
MVT::ValueType LegalIntVT = MVT::Other;
MVT::SimpleValueType LegalIntVT = MVT::Other;
for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i)
if (MVT::isInteger(LegalVTs[i]) && !MVT::isVector(LegalVTs[i])) {
if (isInteger(LegalVTs[i]) && !isVector(LegalVTs[i])) {
LegalIntVT = LegalVTs[i];
break;
}
@ -874,7 +891,7 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
MadeChange = UpdateNodeType(VT, TP);
} else if (ResultNode->getName() == "unknown") {
std::vector<unsigned char> VT;
VT.push_back(MVT::isUnknown);
VT.push_back(EMVT::isUnknown);
MadeChange = UpdateNodeType(VT, TP);
} else {
assert(ResultNode->isSubClassOf("RegisterClass") &&
@ -903,7 +920,7 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
TP.error("Instruction '" + getOperator()->getName() +
"' expects more operands than were provided.");
MVT::ValueType VT;
MVT::SimpleValueType VT;
TreePatternNode *Child = getChild(ChildNo++);
if (OperandNode->isSubClassOf("RegisterClass")) {
const CodeGenRegisterClass &RC =
@ -915,7 +932,7 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
} else if (OperandNode->getName() == "ptr_rc") {
MadeChange |= Child->UpdateNodeType(MVT::iPTR, TP);
} else if (OperandNode->getName() == "unknown") {
MadeChange |= Child->UpdateNodeType(MVT::isUnknown, TP);
MadeChange |= Child->UpdateNodeType(EMVT::isUnknown, TP);
} else {
assert(0 && "Unknown operand type!");
abort();

24
utils/TableGen/CodeGenDAGPatterns.h
View File

@ -31,15 +31,15 @@ namespace llvm {
class CodeGenDAGPatterns;
class ComplexPattern;
/// MVT::DAGISelGenValueType - These are some extended forms of MVT::ValueType
/// that we use as lattice values during type inferrence.
namespace MVT {
/// EMVT::DAGISelGenValueType - These are some extended forms of
/// MVT::SimpleValueType that we use as lattice values during type inference.
namespace EMVT {
enum DAGISelGenValueType {
isFP = MVT::LAST_VALUETYPE,
isInt,
isUnknown
};
/// isExtIntegerVT - Return true if the specified extended value type vector
/// contains isInt or an integer value type.
bool isExtIntegerInVTs(const std::vector<unsigned char> &EVTs);
@ -66,7 +66,7 @@ struct SDTypeConstraint {
union { // The discriminated union.
struct {
MVT::ValueType VT;
unsigned char VT;
} SDTCisVT_Info;
struct {
unsigned OtherOperandNum;
@ -142,7 +142,7 @@ public:
/// patterns), and as such should be ref counted. We currently just leak all
/// TreePatternNode objects!
class TreePatternNode {
/// The inferred type for this node, or MVT::isUnknown if it hasn't
/// The inferred type for this node, or EMVT::isUnknown if it hasn't
/// been determined yet.
std::vector<unsigned char> Types;
@ -170,10 +170,10 @@ class TreePatternNode {
public:
TreePatternNode(Record *Op, const std::vector<TreePatternNode*> &Ch)
: Types(), Operator(Op), Val(0), TransformFn(0),
Children(Ch) { Types.push_back(MVT::isUnknown); }
Children(Ch) { Types.push_back(EMVT::isUnknown); }
TreePatternNode(Init *val) // leaf ctor
: Types(), Operator(0), Val(val), TransformFn(0) {
Types.push_back(MVT::isUnknown);
Types.push_back(EMVT::isUnknown);
}
~TreePatternNode();
@ -185,15 +185,15 @@ public:
return (Types[0] < MVT::LAST_VALUETYPE) || (Types[0] == MVT::iPTR);
}
bool isTypeCompletelyUnknown() const {
return Types[0] == MVT::isUnknown;
return Types[0] == EMVT::isUnknown;
}
bool isTypeDynamicallyResolved() const {
return Types[0] == MVT::iPTR;
}
MVT::ValueType getTypeNum(unsigned Num) const {
MVT::SimpleValueType getTypeNum(unsigned Num) const {
assert(hasTypeSet() && "Doesn't have a type yet!");
assert(Types.size() > Num && "Type num out of range!");
return (MVT::ValueType)Types[Num];
return (MVT::SimpleValueType)Types[Num];
}
unsigned char getExtTypeNum(unsigned Num) const {
assert(Types.size() > Num && "Extended type num out of range!");
@ -201,7 +201,7 @@ public:
}
const std::vector<unsigned char> &getExtTypes() const { return Types; }
void setTypes(const std::vector<unsigned char> &T) { Types = T; }
void removeTypes() { Types = std::vector<unsigned char>(1,MVT::isUnknown); }
void removeTypes() { Types = std::vector<unsigned char>(1, EMVT::isUnknown); }
Init *getLeafValue() const { assert(isLeaf()); return Val; }
Record *getOperator() const { assert(!isLeaf()); return Operator; }

14
utils/TableGen/CodeGenIntrinsics.h
View File

@ -29,13 +29,13 @@ namespace llvm {
std::string EnumName; // The name of the enum "bswap_i32"
std::string GCCBuiltinName;// Name of the corresponding GCC builtin, or "".
std::string TargetPrefix; // Target prefix, e.g. "ppc" for t-s intrinsics.
/// ArgVTs - The MVT::ValueType for each argument type. Note that this list
/// is only populated when in the context of a target .td file. When
/// building Intrinsics.td, this isn't available, because we don't know the
/// target pointer size.
std::vector<MVT::ValueType> ArgVTs;
/// ArgVTs - The MVT::SimpleValueType for each argument type. Note that
/// this list is only populated when in the context of a target .td file.
/// When building Intrinsics.td, this isn't available, because we don't know
/// the target pointer size.
std::vector<MVT::SimpleValueType> ArgVTs;
/// ArgTypeDefs - The records for each argument type.
///
std::vector<Record*> ArgTypeDefs;

6
utils/TableGen/CodeGenRegisters.h
View File

@ -36,7 +36,7 @@ namespace llvm {
Record *TheDef;
std::string Namespace;
std::vector<Record*> Elements;
std::vector<MVT::ValueType> VTs;
std::vector<MVT::SimpleValueType> VTs;
unsigned SpillSize;
unsigned SpillAlignment;
int CopyCost;
@ -44,10 +44,10 @@ namespace llvm {
std::string MethodProtos, MethodBodies;
const std::string &getName() const;
const std::vector<MVT::ValueType> &getValueTypes() const { return VTs; }
const std::vector<MVT::SimpleValueType> &getValueTypes() const {return VTs;}
unsigned getNumValueTypes() const { return VTs.size(); }
MVT::ValueType getValueTypeNum(unsigned VTNum) const {
MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
if (VTNum < VTs.size())
return VTs[VTNum];
assert(0 && "VTNum greater than number of ValueTypes in RegClass!");

18
utils/TableGen/CodeGenTarget.cpp
View File

@ -27,13 +27,13 @@ static cl::opt<unsigned>
AsmWriterNum("asmwriternum", cl::init(0),
cl::desc("Make -gen-asm-writer emit assembly writer #N"));
/// getValueType - Return the MCV::ValueType that the specified TableGen record
/// corresponds to.
MVT::ValueType llvm::getValueType(Record *Rec) {
return (MVT::ValueType)Rec->getValueAsInt("Value");
/// getValueType - Return the MVT::SimpleValueType that the specified TableGen
/// record corresponds to.
MVT::SimpleValueType llvm::getValueType(Record *Rec) {
return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
}
std::string llvm::getName(MVT::ValueType T) {
std::string llvm::getName(MVT::SimpleValueType T) {
switch (T) {
case MVT::Other: return "UNKNOWN";
case MVT::i1: return "MVT::i1";
@ -69,7 +69,7 @@ std::string llvm::getName(MVT::ValueType T) {
}
}
std::string llvm::getEnumName(MVT::ValueType T) {
std::string llvm::getEnumName(MVT::SimpleValueType T) {
switch (T) {
case MVT::Other: return "MVT::Other";
case MVT::i1: return "MVT::i1";
@ -181,7 +181,7 @@ std::vector<unsigned char> CodeGenTarget::getRegisterVTs(Record *R) const {
const CodeGenRegisterClass &RC = RegisterClasses[i];
for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
if (R == RC.Elements[ei]) {
const std::vector<MVT::ValueType> &InVTs = RC.getValueTypes();
const std::vector<MVT::SimpleValueType> &InVTs = RC.getValueTypes();
for (unsigned i = 0, e = InVTs.size(); i != e; ++i)
Result.push_back(InVTs[i]);
}
@ -231,7 +231,7 @@ CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
unsigned Size = R->getValueAsInt("Size");
Namespace = R->getValueAsString("Namespace");
SpillSize = Size ? Size : MVT::getSizeInBits(VTs[0]);
SpillSize = Size ? Size : MVT(VTs[0]).getSizeInBits();
SpillAlignment = R->getValueAsInt("Alignment");
CopyCost = R->getValueAsInt("CopyCost");
MethodBodies = R->getValueAsCode("MethodBodies");
@ -443,7 +443,7 @@ CodeGenIntrinsic::CodeGenIntrinsic(Record *R) {
for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) {
Record *TyEl = TypeList->getElementAsRecord(i);
assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
MVT::ValueType VT = getValueType(TyEl->getValueAsDef("VT"));
MVT::SimpleValueType VT = getValueType(TyEl->getValueAsDef("VT"));
isOverloaded |= VT == MVT::iAny || VT == MVT::fAny;
ArgVTs.push_back(VT);
ArgTypeDefs.push_back(TyEl);

24
utils/TableGen/CodeGenTarget.h
View File

@ -45,12 +45,12 @@ enum SDNP {
// ComplexPattern attributes.
enum CPAttr { CPAttrParentAsRoot };
/// getValueType - Return the MVT::ValueType that the specified TableGen record
/// corresponds to.
MVT::ValueType getValueType(Record *Rec);
/// getValueType - Return the MVT::SimpleValueType that the specified TableGen
/// record corresponds to.
MVT::SimpleValueType getValueType(Record *Rec);
std::string getName(MVT::ValueType T);
std::string getEnumName(MVT::ValueType T);
std::string getName(MVT::SimpleValueType T);
std::string getEnumName(MVT::SimpleValueType T);
/// getQualifiedName - Return the name of the specified record, with a
/// namespace qualifier if the record contains one.
@ -64,7 +64,7 @@ class CodeGenTarget {
mutable std::map<std::string, CodeGenInstruction> Instructions;
mutable std::vector<CodeGenRegister> Registers;
mutable std::vector<CodeGenRegisterClass> RegisterClasses;
mutable std::vector<MVT::ValueType> LegalValueTypes;
mutable std::vector<MVT::SimpleValueType> LegalValueTypes;
void ReadRegisters() const;
void ReadRegisterClasses() const;
void ReadInstructions() const;
@ -121,19 +121,19 @@ public:
return FoundRC;
}
/// getRegisterVTs - Find the union of all possible ValueTypes for the
/// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
/// specified physical register.
std::vector<unsigned char> getRegisterVTs(Record *R) const;
const std::vector<MVT::ValueType> &getLegalValueTypes() const {
const std::vector<MVT::SimpleValueType> &getLegalValueTypes() const {
if (LegalValueTypes.empty()) ReadLegalValueTypes();
return LegalValueTypes;
}
/// isLegalValueType - Return true if the specified value type is natively
/// supported by the target (i.e. there are registers that directly hold it).
bool isLegalValueType(MVT::ValueType VT) const {
const std::vector<MVT::ValueType> &LegalVTs = getLegalValueTypes();
bool isLegalValueType(MVT::SimpleValueType VT) const {
const std::vector<MVT::SimpleValueType> &LegalVTs = getLegalValueTypes();
for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i)
if (LegalVTs[i] == VT) return true;
return false;
@ -175,7 +175,7 @@ public:
/// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
/// tablegen class in TargetSelectionDAG.td
class ComplexPattern {
MVT::ValueType Ty;
MVT::SimpleValueType Ty;
unsigned NumOperands;
std::string SelectFunc;
std::vector<Record*> RootNodes;
@ -185,7 +185,7 @@ public:
ComplexPattern() : NumOperands(0) {};
ComplexPattern(Record *R);
MVT::ValueType getValueType() const { return Ty; }
MVT::SimpleValueType getValueType() const { return Ty; }
unsigned getNumOperands() const { return NumOperands; }
const std::string &getSelectFunc() const { return SelectFunc; }
const std::vector<Record*> &getRootNodes() const {

32
utils/TableGen/DAGISelEmitter.cpp
View File

@ -51,8 +51,8 @@ static const ComplexPattern *NodeGetComplexPattern(TreePatternNode *N,
/// patterns before small ones. This is used to determine the size of a
/// pattern.
static unsigned getPatternSize(TreePatternNode *P, CodeGenDAGPatterns &CGP) {
assert((MVT::isExtIntegerInVTs(P->getExtTypes()) ||
MVT::isExtFloatingPointInVTs(P->getExtTypes()) ||
assert((EMVT::isExtIntegerInVTs(P->getExtTypes()) ||
EMVT::isExtFloatingPointInVTs(P->getExtTypes()) ||
P->getExtTypeNum(0) == MVT::isVoid ||
P->getExtTypeNum(0) == MVT::Flag ||
P->getExtTypeNum(0) == MVT::iPTR) &&
@ -160,7 +160,7 @@ struct PatternSortingPredicate {
/// getRegisterValueType - Look up and return the first ValueType of specified
/// RegisterClass record
static MVT::ValueType getRegisterValueType(Record *R, const CodeGenTarget &T) {
static MVT::SimpleValueType getRegisterValueType(Record *R, const CodeGenTarget &T) {
if (const CodeGenRegisterClass *RC = T.getRegisterClassForRegister(R))
return RC->getValueTypeNum(0);
return MVT::Other;
@ -932,7 +932,7 @@ public:
// How many results is this pattern expected to produce?
unsigned NumPatResults = 0;
for (unsigned i = 0, e = Pattern->getExtTypes().size(); i != e; i++) {
MVT::ValueType VT = Pattern->getTypeNum(i);
MVT::SimpleValueType VT = Pattern->getTypeNum(i);
if (VT != MVT::isVoid && VT != MVT::Flag)
NumPatResults++;
}
@ -1045,7 +1045,7 @@ public:
for (unsigned i = 0; i < NumDstRegs; i++) {
Record *RR = DstRegs[i];
if (RR->isSubClassOf("Register")) {
MVT::ValueType RVT = getRegisterValueType(RR, CGT);
MVT::SimpleValueType RVT = getRegisterValueType(RR, CGT);
Code += ", " + getEnumName(RVT);
}
}
@ -1311,7 +1311,7 @@ private:
Record *RR = DI->getDef();
if (RR->isSubClassOf("Register")) {
MVT::ValueType RVT = getRegisterValueType(RR, T);
MVT::SimpleValueType RVT = getRegisterValueType(RR, T);
if (RVT == MVT::Flag) {
if (!InFlagDecled) {
emitCode("SDOperand InFlag = " + RootName + utostr(OpNo) + ";");
@ -1634,12 +1634,13 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
PatternSortingPredicate(CGP));
// Split them into groups by type.
std::map<MVT::ValueType, std::vector<const PatternToMatch*> >PatternsByType;
std::map<MVT::SimpleValueType,
std::vector<const PatternToMatch*> > PatternsByType;
for (unsigned i = 0, e = PatternsOfOp.size(); i != e; ++i) {
const PatternToMatch *Pat = PatternsOfOp[i];
TreePatternNode *SrcPat = Pat->getSrcPattern();
MVT::ValueType VT = SrcPat->getTypeNum(0);
std::map<MVT::ValueType,
MVT::SimpleValueType VT = SrcPat->getTypeNum(0);
std::map<MVT::SimpleValueType,
std::vector<const PatternToMatch*> >::iterator TI =
PatternsByType.find(VT);
if (TI != PatternsByType.end())
@ -1651,10 +1652,11 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
}
}
for (std::map<MVT::ValueType, std::vector<const PatternToMatch*> >::iterator
for (std::map<MVT::SimpleValueType,
std::vector<const PatternToMatch*> >::iterator
II = PatternsByType.begin(), EE = PatternsByType.end(); II != EE;
++II) {
MVT::ValueType OpVT = II->first;
MVT::SimpleValueType OpVT = II->first;
std::vector<const PatternToMatch*> &Patterns = II->second;
typedef std::vector<std::pair<unsigned,std::string> > CodeList;
typedef std::vector<std::pair<unsigned,std::string> >::iterator CodeListI;
@ -1734,7 +1736,7 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
CallerCode += ", " + TargetOpcodes[j];
}
for (unsigned j = 0, e = TargetVTs.size(); j != e; ++j) {
CalleeCode += ", MVT::ValueType VT" + utostr(j);
CalleeCode += ", MVT VT" + utostr(j);
CallerCode += ", " + TargetVTs[j];
}
for (std::set<std::string>::iterator
@ -1852,7 +1854,7 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
<< " for (unsigned j = 0, e = Ops.size(); j != e; ++j)\n"
<< " AddToISelQueue(Ops[j]);\n\n"
<< " std::vector<MVT::ValueType> VTs;\n"
<< " std::vector<MVT> VTs;\n"
<< " VTs.push_back(MVT::Other);\n"
<< " VTs.push_back(MVT::Flag);\n"
<< " SDOperand New = CurDAG->getNode(ISD::INLINEASM, VTs, &Ops[0], "
@ -1931,7 +1933,7 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
<< "INSTRUCTION_LIST_END)) {\n"
<< " return NULL; // Already selected.\n"
<< " }\n\n"
<< " MVT::ValueType NVT = N.Val->getValueType(0);\n"
<< " MVT::SimpleValueType NVT = N.Val->getValueType(0).getSimpleVT();\n"
<< " switch (N.getOpcode()) {\n"
<< " default: break;\n"
<< " case ISD::EntryToken: // These leaves remain the same.\n"
@ -2008,7 +2010,7 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
// If there is an iPTR result version of this pattern, emit it here.
if (HasPtrPattern) {
OS << " if (NVT == TLI.getPointerTy())\n";
OS << " if (TLI.getPointerTy() == NVT)\n";
OS << " return Select_" << getLegalCName(OpName) <<"_iPTR(N);\n";
}
if (HasDefaultPattern) {

17
utils/TableGen/IntrinsicEmitter.cpp
View File

@ -114,9 +114,9 @@ EmitIntrinsicToNameTable(const std::vector<CodeGenIntrinsic> &Ints,
OS << "#endif\n\n";
}
static void EmitTypeForValueType(std::ostream &OS, MVT::ValueType VT) {
if (MVT::isInteger(VT)) {
unsigned BitWidth = MVT::getSizeInBits(VT);
static void EmitTypeForValueType(std::ostream &OS, MVT::SimpleValueType VT) {
if (MVT(VT).isInteger()) {
unsigned BitWidth = MVT(VT).getSizeInBits();
OS << "IntegerType::get(" << BitWidth << ")";
} else if (VT == MVT::Other) {
// MVT::OtherVT is used to mean the empty struct type here.
@ -140,7 +140,7 @@ static void EmitTypeForValueType(std::ostream &OS, MVT::ValueType VT) {
static void EmitTypeGenerate(std::ostream &OS, Record *ArgType,
unsigned &ArgNo) {
MVT::ValueType VT = getValueType(ArgType->getValueAsDef("VT"));
MVT::SimpleValueType VT = getValueType(ArgType->getValueAsDef("VT"));
if (ArgType->isSubClassOf("LLVMMatchType")) {
unsigned Number = ArgType->getValueAsInt("Number");
@ -153,10 +153,11 @@ static void EmitTypeGenerate(std::ostream &OS, Record *ArgType,
// increment it when we actually hit an overloaded type. Getting this wrong
// leads to very subtle bugs!
OS << "Tys[" << ArgNo++ << "]";
} else if (MVT::isVector(VT)) {
} else if (MVT(VT).isVector()) {
MVT VVT = VT;
OS << "VectorType::get(";
EmitTypeForValueType(OS, MVT::getVectorElementType(VT));
OS << ", " << MVT::getVectorNumElements(VT) << ")";
EmitTypeForValueType(OS, VVT.getVectorElementType().getSimpleVT());
OS << ", " << VVT.getVectorNumElements() << ")";
} else if (VT == MVT::iPTR) {
OS << "PointerType::getUnqual(";
EmitTypeGenerate(OS, ArgType->getValueAsDef("ElTy"), ArgNo);
@ -225,7 +226,7 @@ void IntrinsicEmitter::EmitVerifier(const std::vector<CodeGenIntrinsic> &Ints,
assert(Number < j && "Invalid matching number!");
OS << "~" << Number;
} else {
MVT::ValueType VT = getValueType(ArgType->getValueAsDef("VT"));
MVT::SimpleValueType VT = getValueType(ArgType->getValueAsDef("VT"));
OS << getEnumName(VT);
if (VT == MVT::isVoid && j != 0 && j != ArgTypes.size()-1)
throw "Var arg type not last argument";

2
utils/TableGen/RegisterInfoEmitter.cpp
View File

@ -221,7 +221,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
// Emit the register list now.
OS << " // " << Name
<< " Register Class Value Types...\n"
<< " static const MVT::ValueType " << Name
<< " static const MVT " << Name
<< "[] = {\n ";
for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
OS << getEnumName(RC.VTs[i]) << ", ";