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83ec4b6711
and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
114 lines
4.0 KiB
C++
114 lines
4.0 KiB
C++
//===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the TargetRegisterInfo interface.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/ADT/BitVector.h"
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using namespace llvm;
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TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
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regclass_iterator RCB, regclass_iterator RCE,
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int CFSO, int CFDO)
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: Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE) {
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assert(NumRegs < FirstVirtualRegister &&
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"Target has too many physical registers!");
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CallFrameSetupOpcode = CFSO;
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CallFrameDestroyOpcode = CFDO;
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}
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TargetRegisterInfo::~TargetRegisterInfo() {}
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namespace {
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// Sort according to super- / sub- class relations.
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// i.e. super- register class < sub- register class.
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struct RCCompare {
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bool operator()(const TargetRegisterClass* const &LHS,
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const TargetRegisterClass* const &RHS) {
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return RHS->hasSuperClass(LHS);
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}
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};
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}
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/// getPhysicalRegisterRegClass - Returns the Register Class of a physical
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/// register of the given type. If type is MVT::Other, then just return any
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/// register class the register belongs to.
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const TargetRegisterClass *
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TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, MVT VT) const {
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assert(isPhysicalRegister(reg) && "reg must be a physical register");
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// Pick the register class of the right type that contains this physreg.
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SmallVector<const TargetRegisterClass*, 4> RCs;
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for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
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if ((VT == MVT::Other || (*I)->hasType(VT)) && (*I)->contains(reg))
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RCs.push_back(*I);
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}
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if (RCs.size() == 1)
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return RCs[0];
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if (RCs.size()) {
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// Multiple compatible register classes. Get the super- class.
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std::stable_sort(RCs.begin(), RCs.end(), RCCompare());
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return RCs[0];
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}
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assert(false && "Couldn't find the register class");
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return 0;
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}
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/// getAllocatableSetForRC - Toggle the bits that represent allocatable
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/// registers for the specific register class.
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static void getAllocatableSetForRC(MachineFunction &MF,
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const TargetRegisterClass *RC, BitVector &R){
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for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
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E = RC->allocation_order_end(MF); I != E; ++I)
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R.set(*I);
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}
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BitVector TargetRegisterInfo::getAllocatableSet(MachineFunction &MF,
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const TargetRegisterClass *RC) const {
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BitVector Allocatable(NumRegs);
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if (RC) {
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getAllocatableSetForRC(MF, RC, Allocatable);
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return Allocatable;
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}
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for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
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E = regclass_end(); I != E; ++I)
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getAllocatableSetForRC(MF, *I, Allocatable);
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return Allocatable;
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}
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/// getFrameIndexOffset - Returns the displacement from the frame register to
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/// the stack frame of the specified index. This is the default implementation
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/// which is likely incorrect for the target.
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int TargetRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
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const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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return MFI->getObjectOffset(FI) + MFI->getStackSize() -
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TFI.getOffsetOfLocalArea() + MFI->getOffsetAdjustment();
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}
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/// getInitialFrameState - Returns a list of machine moves that are assumed
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/// on entry to a function.
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void
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TargetRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
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// Default is to do nothing.
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}
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