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rev, rev16, and revsh do not set CPSR.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78561 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-08-10 07:58:45 +00:00
parent 0d3007bb32
commit 8442d00a0e
1 changed files with 3 additions and 3 deletions
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6
lib/Target/ARM/Thumb2SizeReduction.cpp
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@ -71,9 +71,9 @@ namespace {
{ ARM::t2MUL, 0, ARM::tMUL, 0, 0, 0, 1, 0,0, 0 },
{ ARM::t2MVNr, ARM::tMVN, 0, 0, 0, 1, 0, 0,0, 0 },
{ ARM::t2ORRrr, 0, ARM::tORR, 0, 0, 0, 1, 0,0, 0 },
{ ARM::t2REV, ARM::tREV, 0, 0, 0, 1, 0, 0,0, 0 },
{ ARM::t2REV16, ARM::tREV16, 0, 0, 0, 1, 0, 0,0, 0 },
{ ARM::t2REVSH, ARM::tREVSH, 0, 0, 0, 1, 0, 0,0, 0 },
{ ARM::t2REV, ARM::tREV, 0, 0, 0, 1, 0, 1,0, 0 },
{ ARM::t2REV16, ARM::tREV16, 0, 0, 0, 1, 0, 1,0, 0 },
{ ARM::t2REVSH, ARM::tREVSH, 0, 0, 0, 1, 0, 1,0, 0 },
{ ARM::t2RORrr, 0, ARM::tROR, 0, 0, 0, 1, 0,0, 0 },
// FIXME: T2RSBri immediate must be zero. Also need entry for T2RSBS
//{ ARM::t2RSBri, ARM::tRSB, 0, 0, 0, 1, 0, 0,0, 0 },