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skeleton of a lowerCall implementation for ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29159 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -156,9 +156,11 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
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assert(0 && "not implemented");
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abort();
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return;
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case MachineOperand::MO_GlobalAddress:
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assert(0 && "not implemented");
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abort();
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case MachineOperand::MO_GlobalAddress: {
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GlobalValue *GV = MO.getGlobal();
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std::string Name = Mang->getValueName(GV);
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O << Name;
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}
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break;
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case MachineOperand::MO_ExternalSymbol:
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assert(0 && "not implemented");
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@ -13,6 +13,7 @@
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#include "ARM.h"
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#include "ARMTargetMachine.h"
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#include "llvm/CallingConv.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/Intrinsics.h"
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@ -33,6 +34,7 @@ namespace {
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public:
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ARMTargetLowering(TargetMachine &TM);
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virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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};
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}
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@ -42,9 +44,73 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::RET, MVT::Other, Custom);
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}
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namespace llvm {
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namespace ARMISD {
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enum NodeType {
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// Start the numbering where the builting ops and target ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
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/// CALL - A direct function call.
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CALL
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};
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}
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}
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const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default: return 0;
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case ARMISD::CALL: return "ARMISD::CALL";
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}
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}
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// This transforms a ISD::CALL node into a
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// callseq_star <- ARMISD:CALL <- callseq_end
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// chain
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static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
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assert(0 && "Not implemented");
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abort();
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SDOperand Chain = Op.getOperand(0);
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unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
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assert(CallConv == CallingConv::C && "unknown calling convention");
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bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
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assert(isVarArg == false && "VarArg not supported");
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bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
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assert(isTailCall == false && "tail call not supported");
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SDOperand Callee = Op.getOperand(4);
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unsigned NumOps = (Op.getNumOperands() - 5) / 2;
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assert(NumOps == 0);
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// Count how many bytes are to be pushed on the stack. Initially
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// only the link register.
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unsigned NumBytes = 4;
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// Adjust the stack pointer for the new arguments...
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// These operations are automatically eliminated by the prolog/epilog pass
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Chain = DAG.getCALLSEQ_START(Chain,
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DAG.getConstant(NumBytes, MVT::i32));
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std::vector<MVT::ValueType> NodeTys;
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NodeTys.push_back(MVT::Other); // Returns a chain
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NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
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// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
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// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
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// node so that legalize doesn't hack it.
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
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Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
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// If this is a direct call, pass the chain and the callee.
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assert (Callee.Val);
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std::vector<SDOperand> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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unsigned CallOpc = ARMISD::CALL;
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Chain = DAG.getNode(CallOpc, NodeTys, Ops);
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assert(Op.Val->getValueType(0) == MVT::Other);
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Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
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DAG.getConstant(NumBytes, MVT::i32));
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return Chain;
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}
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static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
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@ -41,6 +41,10 @@ def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq, [SDNPHasChain]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq, [SDNPHasChain]>;
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def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
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def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
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"!ADJCALLSTACKUP $amt",
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[(callseq_end imm:$amt)]>;
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@ -51,6 +55,8 @@ def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
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def bxr: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
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def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
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def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
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"ldr $dst, [$addr]",
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[(set IntRegs:$dst, (load iaddr:$addr))]>;
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