mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29159 91177308-0d34-0410-b5e6-96231b3b80d8
282 lines
8.9 KiB
C++
282 lines
8.9 KiB
C++
//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the ARM target.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMTargetMachine.h"
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#include "llvm/CallingConv.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Support/Debug.h"
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#include <iostream>
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#include <set>
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using namespace llvm;
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namespace {
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class ARMTargetLowering : public TargetLowering {
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public:
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ARMTargetLowering(TargetMachine &TM);
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virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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};
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}
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ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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: TargetLowering(TM) {
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setOperationAction(ISD::RET, MVT::Other, Custom);
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}
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namespace llvm {
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namespace ARMISD {
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enum NodeType {
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// Start the numbering where the builting ops and target ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
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/// CALL - A direct function call.
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CALL
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};
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}
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}
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const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default: return 0;
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case ARMISD::CALL: return "ARMISD::CALL";
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}
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}
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// This transforms a ISD::CALL node into a
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// callseq_star <- ARMISD:CALL <- callseq_end
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// chain
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static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
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SDOperand Chain = Op.getOperand(0);
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unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
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assert(CallConv == CallingConv::C && "unknown calling convention");
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bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
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assert(isVarArg == false && "VarArg not supported");
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bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
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assert(isTailCall == false && "tail call not supported");
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SDOperand Callee = Op.getOperand(4);
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unsigned NumOps = (Op.getNumOperands() - 5) / 2;
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assert(NumOps == 0);
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// Count how many bytes are to be pushed on the stack. Initially
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// only the link register.
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unsigned NumBytes = 4;
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// Adjust the stack pointer for the new arguments...
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// These operations are automatically eliminated by the prolog/epilog pass
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Chain = DAG.getCALLSEQ_START(Chain,
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DAG.getConstant(NumBytes, MVT::i32));
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std::vector<MVT::ValueType> NodeTys;
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NodeTys.push_back(MVT::Other); // Returns a chain
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NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
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// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
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// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
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// node so that legalize doesn't hack it.
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
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Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
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// If this is a direct call, pass the chain and the callee.
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assert (Callee.Val);
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std::vector<SDOperand> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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unsigned CallOpc = ARMISD::CALL;
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Chain = DAG.getNode(CallOpc, NodeTys, Ops);
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assert(Op.Val->getValueType(0) == MVT::Other);
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Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
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DAG.getConstant(NumBytes, MVT::i32));
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return Chain;
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}
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static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
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SDOperand Copy;
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SDOperand Chain = Op.getOperand(0);
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switch(Op.getNumOperands()) {
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default:
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assert(0 && "Do not know how to return this many arguments!");
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abort();
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case 1: {
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SDOperand LR = DAG.getRegister(ARM::R14, MVT::i32);
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return DAG.getNode(ISD::BRIND, MVT::Other, Chain, LR);
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}
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case 3:
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Copy = DAG.getCopyToReg(Chain, ARM::R0, Op.getOperand(1), SDOperand());
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if (DAG.getMachineFunction().liveout_empty())
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DAG.getMachineFunction().addLiveOut(ARM::R0);
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break;
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}
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SDOperand LR = DAG.getRegister(ARM::R14, MVT::i32);
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//bug: the copy and branch should be linked with a flag so that the
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//scheduller can't move an instruction that destroys R0 in between them
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//return DAG.getNode(ISD::BRIND, MVT::Other, Copy, LR, Copy.getValue(1));
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return DAG.getNode(ISD::BRIND, MVT::Other, Copy, LR);
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}
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static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
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unsigned ArgNo) {
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MachineFunction &MF = DAG.getMachineFunction();
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MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
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assert (ObjectVT == MVT::i32);
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SDOperand Root = Op.getOperand(0);
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SSARegMap *RegMap = MF.getSSARegMap();
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unsigned num_regs = 4;
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static const unsigned REGS[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3
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};
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if(ArgNo < num_regs) {
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unsigned VReg = RegMap->createVirtualRegister(&ARM::IntRegsRegClass);
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MF.addLiveIn(REGS[ArgNo], VReg);
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return DAG.getCopyFromReg(Root, VReg, MVT::i32);
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} else {
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// If the argument is actually used, emit a load from the right stack
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// slot.
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if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
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unsigned ArgOffset = (ArgNo - num_regs) * 4;
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MachineFrameInfo *MFI = MF.getFrameInfo();
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unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
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int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
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SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
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return DAG.getLoad(ObjectVT, Root, FIN,
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DAG.getSrcValue(NULL));
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} else {
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// Don't emit a dead load.
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return DAG.getNode(ISD::UNDEF, ObjectVT);
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}
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}
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}
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static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
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std::vector<SDOperand> ArgValues;
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SDOperand Root = Op.getOperand(0);
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for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
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SDOperand ArgVal = LowerFORMAL_ARGUMENT(Op, DAG, ArgNo);
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ArgValues.push_back(ArgVal);
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}
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bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
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assert(!isVarArg);
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ArgValues.push_back(Root);
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// Return the new list of results.
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std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
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Op.Val->value_end());
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return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
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}
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SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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switch (Op.getOpcode()) {
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default:
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assert(0 && "Should not custom lower this!");
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abort();
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case ISD::FORMAL_ARGUMENTS:
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return LowerFORMAL_ARGUMENTS(Op, DAG);
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case ISD::CALL:
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return LowerCALL(Op, DAG);
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case ISD::RET:
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return LowerRET(Op, DAG);
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}
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}
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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/// ARMDAGToDAGISel - ARM specific code to select ARM machine
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/// instructions for SelectionDAG operations.
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///
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namespace {
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class ARMDAGToDAGISel : public SelectionDAGISel {
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ARMTargetLowering Lowering;
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public:
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ARMDAGToDAGISel(TargetMachine &TM)
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: SelectionDAGISel(Lowering), Lowering(TM) {
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}
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void Select(SDOperand &Result, SDOperand Op);
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base);
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// Include the pieces autogenerated from the target description.
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#include "ARMGenDAGISel.inc"
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};
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void ARMDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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DAG.setRoot(SelectRoot(DAG.getRoot()));
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assert(InFlightSet.empty() && "ISel InFlightSet has not been emptied!");
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CodeGenMap.clear();
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HandleMap.clear();
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ReplaceMap.clear();
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DAG.RemoveDeadNodes();
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ScheduleAndEmitDAG(DAG);
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}
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//register plus/minus 12 bit offset
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bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand N, SDOperand &Offset,
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SDOperand &Base) {
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
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Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
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}
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else
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Base = N;
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return true; //any address fits in a register
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}
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void ARMDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
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SDNode *N = Op.Val;
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switch (N->getOpcode()) {
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default:
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SelectCode(Result, Op);
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break;
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}
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}
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} // end anonymous namespace
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/// createARMISelDag - This pass converts a legalized DAG into a
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/// ARM-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createARMISelDag(TargetMachine &TM) {
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return new ARMDAGToDAGISel(TM);
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}
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