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ARM vector compare to zero instruction assembly parsing support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137389 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2865,6 +2865,21 @@ bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
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Operands.erase(Operands.begin() + 1);
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delete Op;
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}
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// The vector-compare-to-zero instructions have a literal token "#0" at
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// the end that comes to here as an immediate operand. Convert it to a
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// token to play nicely with the matcher.
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if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
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Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
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static_cast<ARMOperand*>(Operands[5])->isImm()) {
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ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
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if (CE && CE->getValue() == 0) {
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Operands.erase(Operands.begin() + 5);
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Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
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delete Op;
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}
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}
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return false;
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}
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@ -1,11 +1,4 @@
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@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
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@ XFAIL: *
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@ FIXME: We cannot currently test the following instructions, which are
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@ currently marked as for-disassembly only in the .td files:
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@ - VCEQz
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@ - VCGEz, VCLEz
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@ - VCGTz, VCLTz
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@ CHECK: vceq.i8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf3]
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vceq.i8 d16, d16, d17
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