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Add a case we were missing that was causing us to fail CodeGen/PowerPC/rlwinm.ll:test3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23755 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -803,6 +803,20 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
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WorkList.push_back(ANDNode.Val);
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return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
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}
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// fold (and (sra)) -> (and (srl)) when possible.
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if (N0.getOpcode() == ISD::SRA && N0.Val->hasOneUse())
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if (ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
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// If the RHS of the AND has zeros where the sign bits of the SRA will
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// land, turn the SRA into an SRL.
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if (MaskedValueIsZero(N1, (~0ULL << N01C->getValue()) &
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(~0ULL>>(64-OpSizeInBits)), TLI)) {
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WorkList.push_back(N);
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CombineTo(N0.Val, DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
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N0.getOperand(1)));
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return SDOperand();
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}
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}
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// fold (zext_inreg (extload x)) -> (zextload x)
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if (N0.getOpcode() == ISD::EXTLOAD) {
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MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
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