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Clean up LEApcrel instuction(s) a bit. It's not really a Pseudo, so don't mark
it as such. Add some encoding information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119588 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -455,6 +455,14 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
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llvm_unreachable("Unhandled instruction encoding format!");
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break;
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}
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case ARMII::MiscFrm:
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if (MI.getOpcode() == ARM::LEApcrelJT) {
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// Materialize jumptable address.
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emitLEApcrelJTInstruction(MI);
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break;
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}
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llvm_unreachable("Unhandled instruction encoding!");
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break;
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case ARMII::Pseudo:
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emitPseudoInstruction(MI);
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break;
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@ -1168,21 +1168,27 @@ def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
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// LEApcrel - Load a pc-relative address into a register without offending the
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// assembler.
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// FIXME: These are marked as pseudos, but they're really not(?). They're just
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// the ADR instruction. Is this the right way to handle that? They need
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// encoding information regardless.
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let neverHasSideEffects = 1 in {
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let isReMaterializable = 1 in
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def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
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Pseudo, IIC_iALUi,
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"adr$p\t$dst, #$label", []>;
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// FIXME: We want one cannonical LEApcrel instruction and to express one or
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// both of these as pseudo-instructions that get expanded to it.
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def LEApcrel : AXI1<0, (outs GPR:$Rd), (ins i32imm:$label, pred:$p),
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MiscFrm, IIC_iALUi,
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"adr$p\t$Rd, #$label", []>;
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} // neverHasSideEffects
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def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
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def LEApcrelJT : AXI1<0b0100, (outs GPR:$Rd),
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(ins i32imm:$label, nohash_imm:$id, pred:$p),
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Pseudo, IIC_iALUi,
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"adr$p\t$dst, #${label}_${id}", []> {
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let Inst{25} = 1;
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MiscFrm, IIC_iALUi,
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"adr$p\t$Rd, #${label}_${id}", []> {
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bits<4> p;
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bits<4> Rd;
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let Inst{31-28} = p;
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let Inst{27-25} = 0b001;
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let Inst{20} = 0;
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let Inst{19-16} = 0b1111;
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let Inst{15-12} = Rd;
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// FIXME: Add label encoding/fixup
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}
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//===----------------------------------------------------------------------===//
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